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$ xfel version
AWUSBFEX ID=0x00185900(R528/T113) dflag=0x44 dlength=0x08 scratchpad=0x00045000

$ xfel sid
d3402000ec1408140140082114cb5bcb

$ xfel ddr t113-s3
Initial ddr controller succeeded

xfel ddr t113-s3
xfel write 0x40000000 spi.bin
xfel exec 0x40000000

void sys_uart_init(void)
{
	virtual_addr_t addr;
	uint32_t val;

	/* Config GPIOE2 and GPIOE3 to txd0 and rxd0 */
	addr = 0x020000c0 + 0x0;
	val = readl(addr);
	val &= ~(0xf << ((2 & 0x7) << 2));
	val |= ((0x6 & 0xf) << ((2 & 0x7) << 2));
	write32(addr, val);
	............
}

void sys_uart_putc(char c)
{
	virtual_addr_t addr = 0x02500000;

	while((readl(addr + 0x7c) & (0x1 << 1)) == 0);
	write32(addr + 0x00, c);
}

.globl _reset
_reset:
    ldr r1, [r1]
    bl sys_uart_init
    mov r0, ='R'
    bl sys_uart_putc
    mov r0, ='T'
    bl sys_uart_putc
    mov r0, ='T'
    bl sys_uart_putc

struct mem_desc platform_mem_desc[] = {
    {0x00000000, 0xFFFFFFFF, 0x00000000, DEVICE_MEM},
    {0x40000000, 0x47FFFFFF, 0x40000000, NORMAL_MEM},
};

/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
    return 0x03021000;
}

rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
{
    return 0x03022000;
}

/*
The Soft Entry Address Register of CPU0 is 0x070005C4.
The Soft Entry Address Register of CPU1 is 0x070005C8.
*/
void rt_hw_secondary_cpu_up(void)
{
    uint32_t cpuboot_membase = 0x070005c4;
    uint32_t cpuxcfg_membase = 0x09010000;
    uint32_t cpu, reg;

    cpu = 1;
    /* Set CPU boot address */
    writel((uint32_t)(secondary_cpu_start), cpuboot_membase + 4 * cpu);

    /* Deassert the CPU core in reset */
    reg = readl(cpuxcfg_membase);
    writel(reg | (1 << cpu), cpuxcfg_membase);

    __asm__ volatile ("isb":::"memory");
}

void secondary_cpu_c_start(void)
{
    // int timer_irq_number;

    // timer_irq_number = aw_get_irq_num("TIMER1");

    rt_hw_vector_init();

    rt_hw_spin_lock(&_cpus_lock);

    arm_gic_cpu_init(0, platform_get_gic_cpu_base());
    // arm_gic_set_cpu(0, timer_irq_number, 0x2); //timer1

    // timer1_init(); 
    // rt_hw_interrupt_install(timer_irq_number, rt_hw_timer1_isr, RT_NULL, "tick1");
    // rt_hw_interrupt_umask(timer_irq_number);

    rt_system_scheduler_start();
}

 \ | /
- RT -     Thread Operating System
 / | \     4.1.0 build Apr  9 2022 21:17:55
 2006 - 2022 Copyright by RT-Thread team
[I/sal.skt] Socket Abstraction Layer initialize success.
cpuxcfg_membase = 0x13FF0101 // 启动之前的值
cpuxcfg_membase = 0x13FF0103 // 启动之后的值

Hello T113 RT-Thread SMP!

msh />ps
thread   cpu bind pri  status      sp     stack size max used left tick  error
-------- --- ---- ---  ------- ---------- ----------  ------  ---------- ---
tshell     0   2   20  running 0x00000140 0x00001000    15%   0x0000000a 000
aio      N/A   2   16  suspend 0x00000080 0x00000800    07%   0x0000000a 000
sys work N/A   2   23  suspend 0x00000084 0x00000800    06%   0x0000000a 000
tsystem  N/A   2   30  suspend 0x00000098 0x00000400    22%   0x00000020 000
tidle1     1   1   31  running 0x0000005c 0x00000400    19%   0x00000020 000
tidle0   N/A   0   31  ready   0x0000005c 0x00000400    19%   0x00000020 000
timer    N/A   2    4  suspend 0x0000007c 0x00000400    12%   0x0000000a 000