WhyCan Forum(哇酷开发者社区)

	AREA WB_INIT, CODE, READONLY
		
USR_MODE	EQU		0x10
FIQ_MODE	EQU		0x11
IRQ_MODE	EQU		0x12
SVC_MODE	EQU		0x13
ABT_MODE	EQU		0x17
UDF_MODE	EQU		0x1B
SYS_MODE	EQU		0x1F
	
I_BIT		EQU		0x80
F_BIT		EQU		0x40
	
IRQ_RAMStack EQU	0x81FA0000		
DRAM_Limit	EQU		0x81F00000		;DDR栈顶
RAM_Limit	EQU		0x4000 ;内存大小 32k
UND_Stack	EQU		RAM_Limit - 128
Abort_Stack	EQU		RAM_Limit - 256
IRQ_Stack	EQU		RAM_Limit - 512
FIQ_Stack	EQU		RAM_Limit - 768
SVC_Stack	EQU		RAM_Limit - 1024
USR_Stack	EQU		RAM_Limit - 2048

	ENTRY
;	EXPORT	Reset_Go
;	EXPORT 	Vector_Table
	IMPORT  ||Load$$ER_IROM1$$Length||
	IMPORT	||Image$$RW_RAM1$$RW$$Length||	

; 链接器产生代码链接运行位置	
_start
;	/* Boot head information for BROM */
	
	DCD 0xea000016
	DCB 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
	DCD 0, ||Load$$ER_IROM1$$Length||
;	DCD 0, __bootloader_size
	DCB 'S', 'P', 'L', 2
	DCD 0, 0
	DCD 0, 0, 0, 0, 0, 0, 0, 0
	DCD 0, 0, 0, 0, 0, 0, 0, 0	;/* 0x40 - boot params, 0x58 - fel boot type, 0x5c - dram size */

Vector_Table
	B		Reset_Go
	LDR     PC, Undefined_Addr
	LDR     PC, SWI_Addr
	LDR     PC, Prefetch_Addr
	LDR     PC, Abort_Addr
	DCD		0x0
	LDR     PC, IRQ_Addr
	LDR     PC, FIQ_Addr
	
	
Reset_Addr      DCD     Reset_Go
Undefined_Addr  DCD     Undefined_Handler
SWI_Addr        DCD     SWI_Handler1
Prefetch_Addr   DCD     Prefetch_Handler
Abort_Addr      DCD     Abort_Handler
				DCD		0
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler
	
Undefined_Handler
        B       Undefined_Handler
SWI_Handler1
        B       SWI_Handler1     
Prefetch_Handler
        B       Prefetch_Handler
Abort_Handler
        B       Abort_Handler
		IMPORT	arm32_do_irq
		PRESERVE8
IRQ_Handler
	ldr sp,=IRQ_RAMStack
	sub sp, sp, #72
	stmia sp, {r0 - r12}
	add r8, sp, #60
	stmdb r8, {sp, lr}^
	str lr, [r8, #0]
	mrs r6, spsr
	str r6, [r8, #4]
	str r0, [r8, #8]
	mov r0, sp
	bl arm32_do_irq
	ldmia sp, {r0 - lr}^
	mov r0, r0
	ldr lr, [sp, #60]
	add sp, sp, #72
	subs pc, lr, #4
	
FIQ_Handler
        B       FIQ_Handler

	EXPORT	__CodeAddr__
; 引入链接器产生符号，以确定代码运行位置，编译生成的大小
	IMPORT  ||Load$$ER_IROM1$$Base||
	IMPORT	||Load$$RW_RAM1$$RW$$Length||	
	IMPORT  ||Load$$ER_IROM2$$Length||
;	IMPORT  ||Image$$ER_IROM2$$Length||	
; 链接器产生代码链接运行位置
__CodeAddr__	DCD		||Load$$ER_IROM1$$Base||
__CodeSize__    DCD 	||Load$$ER_IROM1$$Length|| + ||Load$$ER_IROM2$$Length|| + ||Load$$RW_RAM1$$RW$$Length||

Reset_Go
;/* Save boot params to 0x00000040 */
	ldr r0, =0x01c20890
	ldr r1, = 0x11111111
	str r1,[r0]
	
	ldr r0, =0x01c20894
	ldr r1, = 0x11111111
	str r1,[r0]
	
	;ldr r0, =0x01c208a0
	;ldr r1, = 0xffffffff
	;str r1,[r0]
	
	ldr r0, =0x00000040
	str sp, [r0, #0]
	str lr, [r0, #4]
	mrs lr, cpsr
	str lr, [r0, #8]
	mrc p15, 0, lr, c1, c0, 0
	str lr, [r0, #12]
	mrc p15, 0, lr, c1, c0, 0
	str lr, [r0, #16]

;	/* Check boot type just for fel */
	mov r0, #0x0
	ldr r1, [r0, #8]
	ldr r2, =0x4c45462e
	cmp r1, r2
	bne lab1
;	ldr r1, =0x1
;	str r1, [r0, #0x58]
lab1	nop
;	/* Enter svc mode and mask interrupts */
	mrs r0, cpsr
	bic r0, r0, #0x1f
	orr r0, r0, #0xd3
	msr CPSR_cxsf, r0
	
;	/* Set vector to the low address */
	mrc p15, 0, r0, c1, c0, 0
	bic r0, #(1<<13)
	mcr p15, 0, r0, c1, c0, 0
	
;	/* Copy vector to the correct address */
	adr r0, Vector_Table
	mrc p15, 0, r2, c1, c0, 0
	ands r2, r2, #(1 << 13)
	ldreq r1, =0x00000000
	ldrne r1, =0xffff0000
;	mcr p15, 0, r2, c1, c0, 0
	ldmia r0!, {r2-r8, r10}
	stmia r1!, {r2-r8, r10}
	ldmia r0!, {r2-r8, r10}
	stmia r1!, {r2-r8, r10}
	
	IMPORT	sys_clock_init
	IMPORT	sys_dram_init
	IMPORT	sys_spi_flash_init
	IMPORT	sys_spi_flash_read
	IMPORT	sys_spi_flash_exit
	IMPORT	memcpy
	IMPORT	memset
	IMPORT	MMU_Init
		
	PRESERVE8
;	/* Boot speed up, leave slower sram */
	adr r0, _start
	ldr r1, =_start
	cmp r0, r1
	
	beq _speedup
	bl sys_dram_init
	bl sys_clock_init
	bl sys_spi_flash_init
	bl MMU_Init	
	
	ldr r0,=0x00
	ldr r1,__CodeAddr__
	ldr r2,__CodeSize__
	bl sys_spi_flash_read
;	bl sys_spi_flash_exit
_speedup    	
	nop
	
	MSR	CPSR_c, #UDF_MODE :OR: I_BIT :OR: F_BIT
	LDR	SP, =UND_Stack + DRAM_Limit
	
	MSR	CPSR_c, #ABT_MODE :OR:	I_BIT :OR: F_BIT
	LDR	SP, =Abort_Stack + DRAM_Limit

	MSR	CPSR_c, #IRQ_MODE :OR: I_BIT :OR: F_BIT
	LDR     SP, =IRQ_Stack + DRAM_Limit

	MSR	CPSR_c, #FIQ_MODE :OR: I_BIT :OR: F_BIT
	LDR     SP, =FIQ_Stack + DRAM_Limit

	MSR	CPSR_c, #SYS_MODE :OR: I_BIT :OR: F_BIT
	LDR     SP, =USR_Stack + DRAM_Limit

	MSR	CPSR_c, #SVC_MODE :OR: I_BIT :OR: F_BIT
	
	LDR     SP, =SVC_Stack + DRAM_Limit

	MRS r1, CPSR
;		BIC r1, #0x1f
;		ORR r1, #0x7f;进入IRQ模式
	AND r1, #0x7f;允许IRQ中断
	MSR CPSR_c,r1
	                                      
;	MRC	p15, 0, r0 , c1, c0   	; r0 := cp15 register 1
;	BIC r0, r0, #0x2000			; Clear bit13 in r1
;	MCR p15, 0, r0 , c1, c0     ; cp15 register 1 := r0
	
	IMPORT	__main	
	adr r0, _start
	ldr r1, =_start
	cmp r0, r1
	bne _NoDdr
	bl sys_clock_init
	bl sys_spi_flash_init
	bl MMU_Init	
_NoDdr	
	 LDR     R0, =__main
     BX      R0
;	B __main
	end