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void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
        struct sunxi_ccm_reg *const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

        /* uart clock source is apb2 */
        writel(APB2_CLK_SRC_OSC24M|      //这里改为APB2_CLK_SRC_PLL6，从内部pll6时钟分频
            APB2_CLK_RATE_N_1|
            APB2_CLK_RATE_M(1),
            &ccm->apb2_div);

int sunxi_clock_set_corepll(int frequency, int core_vol)
{
    unsigned int reg_val;
    unsigned int i;
    struct core_pll_freq_tbl  pll_factor;
    //检查时钟是否合法,为0或者超过2G
    if(!frequency)
    {
        //默认频率
        frequency = 408;
    }
    else if(frequency < 24)
    {
		frequency = 24;
    }
    //切换到24M
    reg_val = readl(CCM_CPU_L2_AXI_CTRL);
    reg_val &= ~(0x03 << 16);
    reg_val |=  (0x01 << 16);
    writel(reg_val, CCM_CPU_L2_AXI_CTRL);
    //延时，等待时钟稳定
    for(i=0; i<0x400; i++);
    //调整时钟频率
	clk_get_pll_para(&pll_factor, frequency);
	//回写PLL1
    reg_val = readl(CCM_PLL1_CPUX_CTRL);
    reg_val &= ~((0x03 << 16) | (0x1f << 8) | (0x03 << 4) | (0x03 << 0));
	reg_val |=  (pll_factor.FactorP << 16) | (pll_factor.FactorN<<8) | (pll_factor.FactorK<<4) | (0 << 0) ;
    writel(reg_val, CCM_PLL1_CPUX_CTRL);
    //延时，等待时钟稳定
#ifndef CONFIG_A67_FPGA
	do
	{
		reg_val = readl(CCM_PLL1_CPUX_CTRL);
	}
	while(!(reg_val & (0x1 << 28)));
#endif
    //修改AXI,AHB,APB分频
    clk_set_divd();
    //切换时钟到COREPLL上
    reg_val = readl(CCM_CPU_L2_AXI_CTRL);
    reg_val &= ~(0x03 << 16);
    reg_val |=  (0x02 << 16);
    writel(reg_val, CCM_CPU_L2_AXI_CTRL);
    
    //修改apb2时钟源，自己添加。。
    return  0;
}

/*
************************************************************************************************************
*
*                                             function
*
*    函数名称：
*
*    参数列表：
*
*
*
*    返回值  ：
*
*    说明    ：
*
*
************************************************************************************************************
*/
int sunxi_clock_get_apb2(void)
{
        //return 24;
	return 600;//改成600
}