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void sys_dma_init()
{
	/* Enable gate for DMA clock, and perform softreset */
	write32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0, read32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0) | (0x1 << 6));
	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) & ~(0x1 << 6));
	for(int i = 0; i < 10; i++)
		continue;
	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) | (0x1 << 6));
}

void sys_dma_wait_end(int ch)
{
	u32_t cfg_reg = 0x80000000;
	/* when the dma end, it clear this bit automatically */
	while ((cfg_reg & 0x80000000) ) {
		cfg_reg = read32(NDMA_CHANNEL_REG_BASE(ch) +
						NDMA_CFG_REG);
	}
}

void sys_dma_dram_copy(int dma_ch, void * dest, void *src, size_t len)
{
	virtual_addr_t addr = NDMA_CHANNEL_REG_BASE(dma_ch);
	u32_t val = 0;
	u32_t bytes_cnt;

	while(len)
	{
		if(len >= SZ_128K)
		{
			bytes_cnt = SZ_128K;
		}
		else
		{
			bytes_cnt = len;
		}
		len -= bytes_cnt;

		/* Set source address */
		write32(addr + NDMA_SRC_ADR_REG, (u32_t)src);

		/* Set dst address */
		write32(addr + NDMA_DST_ADR_REG, (u32_t)dest);

		/* Set byte number */
		write32(addr + NDMA_BYTE_CNT_REG, bytes_cnt);

		/* Set config and start */
		val = (1 << 31) | (2 << 24) | (1 << 23) | (0x11 << 16) | (2 << 8) | (1 << 7) | (0x11 << 0);
		// val = NDMA_SDRAM2SDRAM_CFG;
		write32(addr + NDMA_CFG_REG, val);

		/* Wait end */
		sys_dma_wait_end(dma_ch);
		src += bytes_cnt;
		dest += bytes_cnt;
	}
}

static void sys_ddma_wait_end(int ch)
{
	u32_t cfg_reg = 0x80000000;
	/* when the dma end, it clear this bit automatically */
	while ((cfg_reg & 0x80000000) ) {
		cfg_reg = read32(DDMA_CHANNEL_REG_BASE(ch) +
						DDMA_CFG_REG);
	}
}

void sys_ddma_dram_copy(int dma_ch, void * dest, void *src, size_t bytes_cnt)
{
	virtual_addr_t base = DDMA_CHANNEL_REG_BASE(dma_ch);
	u32_t val = 0;

	if (bytes_cnt > SZ_16M)
	{
		bytes_cnt = SZ_16M;
	}

	/* Set source address */
	write32(base + DDMA_SRC_ADR_REG, (u32_t)src);

	/* Set dst address */
	write32(base + DDMA_DST_ADR_REG, (u32_t)dest);

	/* Set byte number */
	write32(base + DDMA_BYTE_CNT_REG, bytes_cnt);

	/* Set config and start */
	val = (1 << 31) | (2 << 24) | (1 << 23) | (0x1 << 16) | (2 << 8) | (1 << 7) | (0x1 << 0);
	// val = NDMA_SDRAM2SDRAM_CFG;
	write32(base + DDMA_CFG_REG, val);

	/* Wait end */
	sys_ddma_wait_end(dma_ch);
}