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楼主 # 2021-08-06 19:00:05

tigger
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[V3x] u-boot 支持

#克隆 uboot v2021.07 代码
git clone --branch v2021.07 https://github.com/u-boot/u-boot u-boot-v3x

#实用pine cube 的配置文件 (DDR3)
ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make pinecube_defconfig

#编译
ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make

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楼主 #1 2021-08-06 19:35:18

tigger
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Re: [V3x] u-boot 支持

以下是 u-boot 2017 的修改方法:
以下是 u-boot 2017 的修改方法:
以下是 u-boot 2017 的修改方法:

-----------------------------------------------


感谢小智极客赠送的全志/索智S3开发板样品!小巧精致,漂亮大方! (多图预警)
https://whycan.com/t_2227.html#p16284




把荔枝派的 u-boot 弄到 S3 跑跑:

参考链接: https://whycan.cn/t_561.html

1. 克隆源码: git clone https://github.com/Lichee-Pi/u-boot.git -b v3s-spi-experimental

2. ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make LicheePi_Zero_defconfig (默认)


3. 修改 arch/arm/mach-sunxi/dram_sun8i_h3.c:

#ifdef CONFIG_SUNXI_H3_DRAM_DDR2
    u8 bank_bits;
#endif

改为:

u8 bank_bits;

4. 修改 board/sunxi/Kconfig
删除第 138 行:

select SUNXI_H3_DRAM_DDR2

5. .config 文件 删除以下行: CONFIG_SUNXI_H3_DRAM_DDR2


可以用 sunxi-fel 烧录到 S3 板子,

调试串口是 PB8, PB9  也就是 示意图上面 B6, C6

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#2 2021-08-06 20:09:42

孤星泪
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注册时间： 2020-03-18
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Re: [V3x] u-boot 支持

比较了以下 ddr3 和 ddr2 初始化:

https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

#include <common.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>

void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	u8 tccd		= 2;
	u8 tfaw		= ns_to_t(50);
	u8 trrd		= max(ns_to_t(10), 4);
	u8 trcd		= ns_to_t(15);
	u8 trc		= ns_to_t(53);
	u8 txp		= max(ns_to_t(8), 3);
	u8 twtr		= max(ns_to_t(8), 4);
	u8 trtp		= max(ns_to_t(8), 4);
	u8 twr		= max(ns_to_t(15), 3);
	u8 trp		= ns_to_t(15);
	u8 tras		= ns_to_t(38);
	u16 trefi	= ns_to_t(7800) / 32;
	u16 trfc	= ns_to_t(350);

	u8 tmrw		= 0;
	u8 tmrd		= 4;
	u8 tmod		= 12;
	u8 tcke		= 3;
	u8 tcksrx	= 5;
	u8 tcksre	= 5;
	u8 tckesr	= 4;
	u8 trasmax	= 24;

	u8 tcl		= 6; /* CL 12 */
	u8 tcwl		= 4; /* CWL 8 */
	u8 t_rdata_en	= 4;
	u8 wr_latency	= 2;

	u32 tdinit0	= (500 * CONFIG_DRAM_CLK) + 1;		/* 500us */
	u32 tdinit1	= (360 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 360ns */
	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */

	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */

	/* set mode register */
	writel(0x1c70, &mctl_ctl->mr[0]);	/* CL=11, WR=12 */
	writel(0x40, &mctl_ctl->mr[1]);
	writel(0x18, &mctl_ctl->mr[2]);		/* CWL=8 */
	writel(0x0, &mctl_ctl->mr[3]);

	if (socid == SOCID_R40)
		writel(0x3, &mctl_ctl->lp3mr11);	/* odt_en[7:4] */

	/* set DRAM timing */
	writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
	       DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
	       &mctl_ctl->dramtmg[0]);
	writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
	       &mctl_ctl->dramtmg[1]);
	writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
	       DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
	       &mctl_ctl->dramtmg[2]);
	writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
	       &mctl_ctl->dramtmg[3]);
	writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
	       DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
	writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
	       DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
	       &mctl_ctl->dramtmg[5]);

	/* set two rank timing */
	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
			((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));

	/* set PHY interface timing, write latency and read latency configure */
	writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
	       (wr_latency << 0), &mctl_ctl->pitmg[0]);

	/* set PHY timing, PTR0-2 use default */
	writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
	writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);

	/* set refresh timing */
	writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
}

https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c

#include <common.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>

void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	u8 tccd		= 1;
	u8 tfaw		= ns_to_t(50);
	u8 trrd		= max(ns_to_t(10), 2);
	u8 trcd		= ns_to_t(20);
	u8 trc		= ns_to_t(65);
	u8 txp		= 2;
	u8 twtr		= max(ns_to_t(8), 2);
	u8 trtp		= max(ns_to_t(8), 2);
	u8 twr		= max(ns_to_t(15), 3);
	u8 trp		= ns_to_t(15);
	u8 tras		= ns_to_t(45);
	u16 trefi	= ns_to_t(7800) / 32;
	u16 trfc	= ns_to_t(328);

	u8 tmrw		= 0;
	u8 tmrd		= 2;
	u8 tmod		= 12;
	u8 tcke		= 3;
	u8 tcksrx	= 5;
	u8 tcksre	= 5;
	u8 tckesr	= 4;
	u8 trasmax	= 27;

	u8 tcl		= 3; /* CL 6 */
	u8 tcwl		= 3; /* CWL 6 */
	u8 t_rdata_en	= 1;
	u8 wr_latency	= 1;

	u32 tdinit0	= (400 * CONFIG_DRAM_CLK) + 1;		/* 400us */
	u32 tdinit1	= (500 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 500ns */
	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */

	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */

	/* set mode register */
	writel(0x263, &mctl_ctl->mr[0]);
	writel(0x4, &mctl_ctl->mr[1]);
	writel(0x0, &mctl_ctl->mr[2]);
	writel(0x0, &mctl_ctl->mr[3]);

	/* set DRAM timing */
	writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
	       DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
	       &mctl_ctl->dramtmg[0]);
	writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
	       &mctl_ctl->dramtmg[1]);
	writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
	       DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
	       &mctl_ctl->dramtmg[2]);
	writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
	       &mctl_ctl->dramtmg[3]);
	writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
	       DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
	writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
	       DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
	       &mctl_ctl->dramtmg[5]);

	/* set two rank timing */
	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
			(0x66 << 8) | (0x10 << 0));

	/* set PHY interface timing, write latency and read latency configure */
	writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
	       (wr_latency << 0), &mctl_ctl->pitmg[0]);

	/* set PHY timing, PTR0-2 use default */
	writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
	writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);

	/* set refresh timing */
	writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
}

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#3 2021-08-08 17:39:38

shawn.d
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注册时间： 2020-09-12
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Re: [V3x] u-boot 支持

v3x是啥？

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#4 2021-08-10 20:46:15

mysteryli
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个人网站

Re: [V3x] u-boot 支持

楼主也在搞V3X？做到哪步了？

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#5 2023-10-18 17:23:56

15615756201
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Re: [V3x] u-boot 支持

我的为啥一直重启啊

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#6 2023-10-18 17:59:50

wcq6699
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注册时间： 2023-10-17
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Re: [V3x] u-boot 支持

怎么引导到FLASH  期待系统呀

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