WhyCan Forum(哇酷开发者社区)

 Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13
 2019:
 
     + Added ARM Cortex-M23 port layer to complement the pre-existing ARM
       Cortex-M33 port layer.     + The RISC-V port now automatically
 switches between 32-bit and 64-bit       cores.

...
 Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13
 2019:
 
     ...
 + The RISC-V port now automatically switches between 32-bit and 64-bit       cores.     
 ...
 

  Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released
 February 25 2019:
  
   + Added GCC RISC-V MCU port with three separate demo applications. 
   ...    

__freertos_irq_stack_top

	#define configMTIME_BASE_ADDRESS 	( pdev_mtime_mtime_addr )
	#define configMTIMECMP_BASE_ADDRESS( pdev_mtime_mtimecmp_addr )
	

	#define configUSE_IDLE_HOOK				0
	#define configUSE_TICK_HOOK				1
	

	#define configCPU_CLOCK_HZ				( 1000 )
	#define configTICK_RATE_HZ				( ( TickType_t ) 1 )
	

	#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 105 )
	#define configTOTAL_HEAP_SIZE			( ( size_t ) 14500 )
	

	#define configMAX_TASK_NAME_LEN			( 16 )
	

	CFLAGS      += -D__riscv_xlen=64 -D__riscv64
	

	CFLAGS      += -D__riscv_xlen=32
	

	#ifdef __riscv64
		#define portBYTE_ALIGNMENT			8
	#else
		#define portBYTE_ALIGNMENT			16
	#endif
	

    #include "rv_mtvec_map.h"
    .macro init;
    .endm
    .section .init;
    .option norvc
    .option nopic
    .align  6;
    .weak reset_vector;
    .globl _start;
    .type _start,@function
    
_start:
    la sp, __stack_end                                    
    /* reset vector */
    addi s2, x0, 'a';
    li  t1, pdev_uart0_write_addr;
    sb s2,0(t1);

    addi s2, x0, 'b';
    li  t1, pdev_uart0_write_addr;
    sb s2,0(t1);

    addi s2, x0, '\n';
    li  t1, pdev_uart0_write_addr;
    sb s2,0(t1);
    
    j reset_vector
    .align  4;                                             
reset_vector:
    addi s2, x0, 'r';
    li  t1, pdev_uart0_write_addr;
    sb s2,0(t1);

    addi s2, x0, '\n';
    li  t1, pdev_uart0_write_addr;
    sb s2,0(t1);
    
    la a0,e_vertor;

2:
	/* Clear bss section */
	la a0, __bss_start;
	la a1, __bss_end;
	bgeu a0, a1, 2f;
1:
	# sw zero, (a0);
	addi a0, a0, 4;
	bltu a0, a1, 1b;
2:

    call main;
    unimp

void main(void){
    // *(uint64_t *)(pdev_mtime_mtimecmp_addr+1) = 300;
    uint64_t i;
    puts("main\n");
    extern void main_blinky( void );
    main_blinky();
    puts("main_blinky\n");
    while(1){
        i = 1000;
        while(i--);
        puts("wait for cb\n");
    }
}