void InitSPI1(){
GPIOA->CFG[0]&=0xffff0000;
GPIOA->CFG[0]|=0x00001661;
SETBIT(CCU->BUS_SOFT_RST0,1<<CCU_BUS_CLK_GATING_SPI1_GATING);
ENABLE_BUSCLK(CCU_BUS_CLK_GATING_SPI1_GATING);
SPI1->CCR=0x00001000+2;
SPI1->GCR=SPI_GCR_SRST|SPI_GCR_MODE|SPI_GCR_TP_EN|SPI_GCR_EN;
while(SPI1->GCR&SPI_GCR_SRST);
SETBIT(SPI1->TCR,SPI_TCR_CPOL|SPI_TCR_CPHA|SPI_TCR_SS_OWNER);//SPI_TCR_CPOL|SPI_TCR_CPHA|
SETBIT(SPI1->FCR,SPI_FCR_RF_RST|SPI_FCR_TX_FIFO_RST|SPI_FCR_TF_DRQ_EN);
}
void InitDMA(){
ENABLE_BUSCLK(CCU_BUS_CLK_GATING_DMA_GATING);
SETBIT(CCU->BUS_SOFT_RST0,1<<CCU_BUS_CLK_GATING_DMA_GATING);
DMA->NDMA[0].CFG=NDMA_CFG_DESTINATION_DRQ_TYPE_CONFIDENTIAL_SET(NDMA_CFG_DRQ_SPI1_TX)|NDMA_CFG_SOURCE_DRQ_TYPE_SET(NDMA_CFG_DRQ_SDRAM_MEMORY)|NDMA_CFG_SOURCE_ADDRESS_TYPE_SET(NDMA_CFG_ADDRESS_LINEAR_MODE)|NDMA_CFG_DESTINATION_ADDRESS_TYPE_SET(NDMA_CFG_ADDRESS_IO_MODE)|NDMA_CFG_REMAIN_BYTE_COUNTER_READ_ENABLE|NDMA_CFG_WAIT_STATE_SET(NDMA_CFG_WAIT_STATE2);
DMA->NDMA[0].SRC_ADR=(u32)&lcdbuff;
DMA->NDMA[0].DES_ADR=(u32)&SPI1->TXD;
}
void flushDMA(){
SPI1->MBC=SPI1->MTC=SPI1->BCC=DMA->NDMA[0].BYTE_CNT=240*320*2;
SETBIT(DMA->NDMA[0].CFG,NDMA_CFG_LOADING);
SETBIT(SPI1->TCR,SPI_TCR_XCH);
while(DMA->NDMA[0].CFG&NDMA_CFG_BUSY_STATUS)SPI1->RXD;
SETBIT(SPI1->ISR,SPI_ISR_TC);
while(!(SPI1->ISR&SPI_ISR_TC))SPI1->RXD;
}
u8 lcdbuff[240*320*2] __attribute__((at(0x80000000)));
for(cnt=0;cnt<240*320;cnt++)lcdbuff[cnt]=0xff;
for(cnt=0;cnt<240*320;cnt++)lcdbuff[cnt+240*320]=0x0;
InitDMA();
ST7789_CS_CLR();
flushDMA();
ST7789_CS_SET();
我试了一下效果
https://whycan.cn/files/members/2421/shua.mp4
测试的过程中发现SPI的RXD如果不读也会卡住SPI,不知道有没有忽略RXD的方法。
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SPI1的IO驱动能力不足
CLK只能到34M了
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厉害了,是dma驱动么。加一个强上拉看看
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想问一下,这个程序模板在哪?
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@KeyMove
是不是不清RX的FIFO传输会停止,是不是清了TP_EN就可以了。
TP_EN
Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop smart
burst sending when RX FIFO is full.
1 – stop transmit data when RXFIFO full
0 – normal operation, ignore RXFIFO status
Note: Can’t be written when XCH=1
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