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src/api/tcpip.c:485:  err_t err = sys_sem_new(&call->sem, 0);
src/api/sockets.c:2026:      if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) {
src/api/sockets.c:2371:    if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) {
src/api/api_lib.c:1318:  err = sys_sem_new(API_EXPR_REF(API_VAR_REF(msg).sem), 0);
src/api/api_msg.c:752:  if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) {
src/core/sys.c:139:    err_t err = sys_sem_new(&delaysem, 0);

 /> list_sem
semaphore        v   suspend thread
---------------- --- --------------
sem126           000 1:lwip_test_exampl
sem53            000 0
sem6             000 0
sem3             000 0
can data sem     000 1:udp and tcp thre
rxSem            000 1:canRxThread
can0tl           001 0
shrx             000 0
sem0             000 1:ping_thread
qspi0_s          000 0
heap_cma         001 0
heap_sys         001 0

static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
    aicmac_netif_t *aic_netif = (aicmac_netif_t *)netif;
    struct pbuf *q;
    aicmac_dma_desc_t *pdesc;
    int ret = ERR_OK;
#ifndef CONFIG_MAC_ZERO_COPY_TXBUF
    u8 *buffer;
    uint16_t framelength = 0;
    uint32_t bufferoffset = 0;
    uint32_t byteslefttocopy = 0;
    uint32_t payloadoffset = 0;
#else
    uint32_t p_cnt = 0;
    uint32_t p_type = 0;
    uint32_t empty_desc_cnt = 0;
    uint32_t index;
    uint32_t tmpreg = 0;
    uint32_t i = 0;
#endif

    pr_debug("%s\n", __func__);

    if ((netif == NULL) || (p == NULL)){
        pr_err("%s invalid parameter.\n", __func__);
        return ERR_MEM;
    }

    aicos_mutex_take(eth_tx_mutex, AICOS_WAIT_FOREVER);

    pdesc = dctl[aic_netif->port].tx_desc_p;
    /* before read: invalid cache */
    aicmac_dcache_invalid((uintptr_t)pdesc, sizeof(aicmac_dma_desc_t));

#ifndef CONFIG_MAC_ZERO_COPY_TXBUF
    buffer = (u8 *)(unsigned long)(pdesc->buff1_addr);
    bufferoffset = 0;

    for (q = p; q != NULL; q = q->next) {
        if ((pdesc->control & ETH_DMATxDesc_OWN) != (u32)RESET) {
            pr_err("%s no enough desc for transmit.(len = %u)\n", __func__, q->len);
            ret = ERR_MEM;
            goto error;
        }

        /* Get bytes in current lwIP buffer  */
        byteslefttocopy = q->len;
        payloadoffset = 0;

        /* Check if the length of data to copy is bigger than Tx buffer size*/
        while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE) {
            /* Copy data to Tx buffer*/
            memcpy((u8_t *)((u8_t *)buffer + bufferoffset),
                   (u8_t *)((u8_t *)q->payload + payloadoffset),
                   (ETH_TX_BUF_SIZE - bufferoffset));
            /* after write: flush cache */
            aicmac_dcache_clean((uintptr_t)((u8_t *)buffer + bufferoffset),
                                (ETH_TX_BUF_SIZE - bufferoffset));

            /* Point to next descriptor */
            pdesc = (aicmac_dma_desc_t *)(unsigned long)(pdesc->buff2_addr);
            /* before read: invalid cache */
            aicmac_dcache_invalid((uintptr_t)pdesc, sizeof(aicmac_dma_desc_t));

            /* Check if the buffer is available */
            if ((pdesc->control & ETH_DMATxDesc_OWN) != (u32)RESET) {
                pr_err("%s no enough desc for transmit.(len = %u)\n", __func__, q->len);
                ret = ERR_MEM;
                goto error;
            }

            buffer = (u8 *)(unsigned long)(pdesc->buff1_addr);

            byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
            payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
            framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
            bufferoffset = 0;
        }

        /* Copy the remaining bytes */
        memcpy((u8_t *)((u8_t *)buffer + bufferoffset),
               (u8_t *)((u8_t *)q->payload + payloadoffset), byteslefttocopy);
        /* after write: flush cache */
        aicmac_dcache_clean((uintptr_t)((u8_t *)buffer + bufferoffset),
                            byteslefttocopy);
        bufferoffset = bufferoffset + byteslefttocopy;
        framelength = framelength + byteslefttocopy;
    }

    /* Prepare transmit descriptors to give to DMA*/
    aicmac_submit_tx_frame(aic_netif->port, framelength);
#else
    /* Count number of pbufs in a chain */
    q = p;
    while (q != NULL) {
        if (q->len > ETH_DMATxDesc_TBS1){
            pr_err("%s too large pbuf.(len = %d)\n", __func__, q->len);
            ret = ERR_MEM;
            goto error;
        }
        p_cnt++;
        q = q->next;
    }

    /* Scan empty descriptor for DMA tx */
    while (((pdesc->control & ETH_DMATxDesc_OWN) == (uint32_t)RESET) &&
           (empty_desc_cnt < ETH_RXBUFNB)) {

        empty_desc_cnt++;
        if (empty_desc_cnt >= p_cnt)
            break;

        /* Point to next descriptor */
        pdesc = (aicmac_dma_desc_t *)(unsigned long)(pdesc->buff2_addr);
        if (pdesc == dctl[aic_netif->port].tx_desc_unconfirm_p){
            pr_info("%s don't overwrite unconfirm area.\n", __func__);
            break;
        }

        /* before read: invalid cache */
        aicmac_dcache_invalid((uintptr_t)pdesc, sizeof(aicmac_dma_desc_t));
    }

    if (p_cnt > empty_desc_cnt){
        pr_err("%s no enough desc for transmit pbuf.(pbuf_cnt = %d, empty_desc = %d)\n",
                __func__, p_cnt, empty_desc_cnt);
        ret = ERR_MEM;
        goto error;
    }

    pbuf_ref(p);
    q = p;
    p_type = p->type_internal;
    for(i=0; i<p_cnt; i++){
        index = pdesc->reserved1;
        if (index >= ETH_RXBUFNB){
            pr_err("%s get dma desc index err.\n", __func__);
            pbuf_free(p);
            ret = ERR_MEM;
            goto error;
        }

        if (i == (p_cnt-1)){
            dctl[aic_netif->port].tx_buff[index] = p;
        }else{
            dctl[aic_netif->port].tx_buff[index] = NULL;
        }

        /* flush data cache */
        if (p_type == PBUF_POOL){
            aicmac_dcache_clean((uintptr_t)q->payload, q->len);
        }else{
            aicos_dcache_clean_range((unsigned long *)q->payload, q->len);
        }

        /* Set Buffer1 address pointer */
        pdesc->buff1_addr =
            (uint32_t)(unsigned long)(q->payload);
        /* Set frame size */
        pdesc->buff_size = (q->len & ETH_DMATxDesc_TBS1);
        /* after write: flush cache */
        aicmac_dcache_clean((uintptr_t)&pdesc->buff_size, 2*sizeof(uint32_t));

        /*set LAST and FIRST segment */
        tmpreg =  ETH_DMATxDesc_TCH;
        if (i == 0)
            tmpreg |= ETH_DMATxDesc_FS;
        if (i == (p_cnt-1))
            tmpreg |= ETH_DMATxDesc_LS | ETH_DMATxDesc_IC;
        /* TCP/IP Tx Checksum Insertion */
        if (mac_config[aic_netif->port].coe_tx)
            tmpreg |= ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
        /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
        tmpreg |= ETH_DMATxDesc_OWN;
        pdesc->control = tmpreg;
        /* after write: flush cache */
        aicmac_dcache_clean((uintptr_t)&pdesc->control, sizeof(uint32_t));

        /* Point to next descriptor */
        pdesc = (aicmac_dma_desc_t *)(unsigned long)(pdesc->buff2_addr);
        q = q->next;
    }

    dctl[aic_netif->port].tx_desc_p = pdesc;

    /* Resume DMA transmission */
    aicmac_resume_dma_tx(aic_netif->port);
#endif

error:
    /* Give semaphore and exit */
    aicos_mutex_give(eth_tx_mutex);

    return ret;
}