WhyCan Forum(哇酷开发者社区)

@liefyuan
你的问题解决了么？ 我也遇到一样的问题，
HELLO! BOOT0 is starting!
BOOT0 commit : #.###
set pll start
periph0 has been enabled
set pll end
board init ok
ZQ value = 0x2e
get_pmu_exist() = -1
ddr_efuse_type: 0xb
mark_id: 0x70
trefi:7.8ms
[AUTO DEBUG] single rank and full DQ!
ddr_efuse_type: 0xb
mark_id: 0x70
trefi:7.8ms
[AUTO DEBUG] rank 0 row = 13
[AUTO DEBUG] rank 0 bank = 8
[AUTO DEBUG] rank 0 page size = 2 KB
DRAM BOOT DRIVE INFO: V0.32
DRAM CLK = 792 MHz
DRAM Type = 3 (2:DDR2,3:DDR3)
DRAMC read ODT  off.
DRAM ODT value: 0x42.
ddr_efuse_type: 0xb
mark_id: 0x70
DRAM SIZE =128 M
PLL_DDR_CTRL_REG:0xf8004100
DRAM_CLK_REG:0xc0000000
[TIMING DEBUG] MR2= 0x18
DRAM simple test OK.
rtc standby flag is 0x0, super standby flag is 0x0
spinand UBOOT_START_BLK_NUM 8 UBOOT_LAST_BLK_NUM 16
Jump to second Boot.

然后就没有显示了。uboot的串口也对应修改了串口的io口配置，和boot0里面一样的管脚，一样的配置