页次： 1
https://whycan.com/files/members/12176/20240122_165941_20240122-1805.jpg
some pair of these, I don’t remember exactly
check with a multimeter
I decompiled the driver from the original kernel of this device, the initialization array is very different from the manual for the camera given here, with this array the camera switched to DVP mode and a data stream appeared, and the pclk, hsync, vsync outputs were also switched on. Tomorrow I will post the changes on Github. By the way, MIPI mode appears to be initialized in the rockchip driver.
https://whycan.cn/files/members/3/QQ20180315142018.png
按这个修改， 可以通过编译。
Why don't you commit to the main repository?
[ 0.854870][ T1] gc0403 0-003c: Detected GC0403 sensor SUCCEFULL, update on github coming soon..
As it was already mentioned here, the camera requires MCLK to work, I corrected the device tree for this, but as it turned out I had bad soldering in the connector of my debug board. After eliminating the missing connection, the camera was located at 3c, wtf?? The manual indicates address 78, it turned out everything is simple, 78 is together with the direction bit, and Linux does not take this bit into account either in the device tree or i2c-tools, that is, the address actually needs to be shifted to the right by one bit, that is, divided by two 78/ 2 = 3c, bingo.
buildroot for booting from spi nor, the driver for gc0403 is built in, but does not work, the device tree does not enable mclk clock
https://github.com/DowJhob/Buildroot-YuzukiSBC
for build:
make DowJhob_defconfig
make
to makefile add
obj-$(CONFIG_VIDEO_GC0403) += gc0403.oto Kconfig
config VIDEO_GC0403
tristate "GalaxyCore GC0403 sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
depends on MEDIA_CAMERA_SUPPORT
select V4L2_FWNODE
help
Support for the GalaxyCore GC0403 sensor.
To compile this driver as a module, choose M here: the
module will be called gc0403.and enable cam support in linux-menuconfig
after these changes apper gc0403.o file
i dont test, wait board from tao
You expected to see your camera at address 0x3C, although your fex file shows address 0x78
vip_dev0_twi_addr = 120But again, if it is not added to the device tree, then the kernel will not load a driver for it, which must be pre-built
I will be doing a lichee pi zero test, if you want to run your kernel with camera support on this board you will also need to set the pmu to the appropriate voltages
https://docs.google.com/spreadsheets/d/1cpCm4w2osl_qq0VbIGKfyeqJWF3uEJNOU9e1Cx9IoMg/edit#gid=0
If you want a shell on the device, use ADB
adb -d shellvia usb pins near the connector, camdroid is used on the device
In function
gc0403_probechange function
media_entity_init
to
media_entity_pads_initdts file:
&csi1 {
pinctrl-names = "default";
pinctrl-0 = <&csi1_8bit_pins>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
csi1_ep: endpoint {
remote-endpoint = <&gc0403_ep>;
bus-width = <8>; // number of data lines actively used, valid for the parallel busses.
hsync-active = <1>; // active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
vsync-active = <0>; // active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
data-active = <1>; // similar to HSYNC and VSYNC, specifies data line polarity.
pclk-sample = <1>; // sample data on rising (1) or falling (0) edge of the pixel clock signal.
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pe_pins>;
status = "okay";
gc0403: camera@78 {
compatible = "galaxycore,gc0403";
reg = <0x78>;
pinctrl-names = "default";
pinctrl-0 = <&csi1_mclk_pin>;
clocks = <&ccu CLK_CSI1_MCLK>;
clock-names = "xvclk";
pwdn-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */
port {mm
gc0403_ep: endpoint {
remote-endpoint = <&csi1_ep>;
bus-width = <8>; // number of data lines actively used, valid for the parallel busses.
hsync-active = <1>; // active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
vsync-active = <0>; // active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
data-active = <1>; // similar to HSYNC and VSYNC, specifies data line polarity.
pclk-sample = <1>; // sample data on rising (1) or falling (0) edge of the pixel clock signal.
};
};
};dtsi file
csi1_8bit_pins: csi1-8bit-pins {
pins = "PE0", "PE2", "PE3", "PE8", "PE9", // PCLK, HSYNK, VSYNK, D4, D5,
"PE10", "PE11", "PE12", "PE13", "PE14", // D6, D7, D8, D9, D10
"PE15"; // D11
function = "csi";
};
csi1_mclk_pin: csi1-mclk-pin {
pins = "PE20"; // MCLK
function = "csi";
};页次： 1