GenaSPB 发表的帖子

GenaSPB · 全志 SOC

Hello.
Who can help with hdmi phy initialization code for subject?
H3/a64 not work on this processor.
Bare metal.

Current state here:
https://github.com/ua1arn/hftrx/blob/e3313fc35a93618cb72a7354153a22266f47b0b4/src/display/ltdc.c#L7491

T507 not set status bit after calibration.

GenaSPB · 全志 SOC

Headers for use with CMSIS_5 may be found here:
https://github.com/ua1arn/hftrx/tree/develop/arch/aw_t113x

Audio and other in same place. Two (and risc-v core for t113-s4) code also.

GenaSPB · 全志 SOC

Xfel support norflash operations

GenaSPB · 全志 SOC

zyfl88 说：

我打了T113的板子现在不知道怎么玩了，按搜到的方法编译固件烧到SD卡，板子没有任何反应

Tray mango-pi binaries tflush_uac2.zip from this directory
https://github.com/ua1arn/hftrx/tree/develop/build/allwinner_t113-s3

Build environment and utilities also can be found here.

GenaSPB · 全志 SOC

Why you remove 'volatile' from g2d registers?

GenaSPB · 全志 SOC

https://github.com/ua1arn/hftrx/tree/develop/src/sdram/aw_t113s3_f133

GenaSPB · 全志 SOC

I confirm. Sunny days not good for hacking

GenaSPB · 全志 SOC

Run unmodified tina_d1s_mipi_rpi_uart0.img - uart shown this:

[00.395]line:714 init_clocks
__clk_init: clk pll_periph0x2 already initialized
register fix_factor clk error
[00.406]drv_disp_init
request pwm success, pwm2:pwm2:0x2000c00.
[00.422]drv_disp_init finish
[00.425]boot_gui_init:start
[00.428]set disp.dev2_output_type fail. using defval=0
[00.620]boot_gui_init:finish
partno erro : can't find partition bootloader
54 bytes read in 1 ms (52.7 KiB/s)
[00.989]bmp_name=bootlogo.bmp size 307254
307254 bytes read in 28 ms (10.5 MiB/s)
[01.031]LCD open finish

Why disp.dev2_output_type fail ?
Display not shown anything. Backlight turned on by hardware.

GenaSPB · 全志 SOC

Check t113m4

GenaSPB · 全志 SOC

Some usb wifi dongles are closed sources. No specifications avaliable

GenaSPB · 全志 SOC

Start second core on T113-s3:

//	3.4.2.4 CPU0 Hotplug Process
//
//	The Hotplug Flag Register is 0x070005C0.
//	The Soft Entry Address Register is 0x070005C4.

//	3.4.2.3 NON_CPU0 Boot Process
//
//	The Soft Entry Address Register of CPU0 is 0x070005C4
//	The Soft Entry Address Register of CPU1 is 0x070005C8

#define HARDWARE_HOTPLUG_FLAG 0xFA50392F	// CPU Hotplug Flag value

// In Allwinner h133 this i/o block named R_CPUCFG

//#define HARDWARE_NCORES 2

static void aarch32_mp_cpuN_start(uintptr_t startfunc, unsigned targetcore)
{
	const uint32_t CORE_RESET_MASK = UINT32_C(1) << targetcore;	// CPUx_CORE_RESET
	volatile uint32_t * const rvaddr = ((volatile uint32_t *) (R_CPUCFG_BASE + 0x1c4 + targetcore * 4));
	ASSERT(startfunc != 0);
	ASSERT(targetcore != 0);

	C0_CPUX_CFG->C0_RST_CTRL &= ~ CORE_RESET_MASK;
	* rvaddr = startfunc;
	ASSERT(* rvaddr == startfunc);
	dcache_clean_all();	// startup code should be copied in to sysram for example.
	C0_CPUX_CFG->C0_RST_CTRL |= CORE_RESET_MASK;
}

Each core has own cache, MMU, part of GIC

Registers definitions: https://whycan.com/files/members/12476/t113s3.zip

GenaSPB · 全志 SOC

I can not putting anything in BROM. It is a read only memory

GenaSPB · 全志 SOC

In mentioned theme, hifi4 gcc with call0 abi (non-wimndowed abi) shown. Significantly less support at runtime need.

GenaSPB · 全志 SOC

Dual-core baremetal t113-s3 project here
https://github.com/ua1arn/hftrx/tree/develop

GenaSPB · 全志 SOC

Message:
https://electronix.ru/forum/index.php?/topic/166772-allwinner-t113-s3/&do=findComment&comment=1864963

gcc:
https://drive.google.com/file/d/1yIyvjHthyEdjYTlcjSFJK-uZaCRBITG4/view?usp=sharing

Theme:
https://electronix.ru/forum/index.php?/ … nt=1876159

GenaSPB · 全志 SOC

Each power-up of T113-s3 slightly change bits, visible in RETITE_PC0_REG and RETITE_PC1_REG

GenaSPB · 全志 SOC

RISC_CFG dumps on two boards:
F133-A:

06010000  00010000 4006E910 00000000 00000000 00000013 00000021 00000003 00000002
06010020  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010040  00000000 00000000 00000000 00000000 400010D8 00000000 00000000 00000000
06010060  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010080  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100A0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100C0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100E0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010100  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010120  00000000

T113-s3:

06010000  00010000 400F95E0 00000000 00000000 00000013 00000021 00000003 00000002
06010020  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010040  00000000 00000000 00000000 00000000 BFFBBFF2 000000F7 00000000 00000000
06010060  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010080  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100A0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100C0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100E0  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010100  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010120  00000000

On T113-s3 RETITE_PC0_REG and RETITE_PC1_REG looks like meaningful

GenaSPB · 全志 SOC

audiomonster 说：

你们有HIFI4-DSP User Manual 和 Compiler ? 看来这个DSP好厉害 !

Local hobbyists make windows - hosted xtensa gcc. Under tests with t113-s3.

xtensa-hifi4-elf-gcc.exe (crosstool-NG 1.25.0) 10.3.0
Copyright (C) 2020 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

GenaSPB · 全志 SOC

I am an author of this test code.
Unfortunately, risc-v core (may be exising) of t113-s3 still under reset...

I am play with other toys (lvds, mipi-dsi outputs).

WhyCan Forum(哇酷开发者社区)

#1 全志 SOC » T507/H616 hdmi » 2024-10-26 04:30:23

#2 Re: 全志 SOC » 分享一个自己做的T113-S3裸机IAR工程，有bootloader和led闪烁demo » 2024-10-09 16:07:25

#3 Re: 全志 SOC » 全志A20 / A64 / A133 / D1 / T113-I/V83x /V85x Tina / Android 文档合集/集合，很全! » 2024-09-17 03:54:19

#4 Re: 全志 SOC » T113-S3 RT-Thread SMP适配笔记 » 2024-08-18 17:43:16

#5 Re: 全志 SOC » 全志T113-S3 G2D加速裸机驱动 » 2024-06-28 12:35:48

#6 Re: 全志 SOC » F133B DDR初始化 » 2024-06-23 04:46:11

#7 Re: 全志 SOC » musb编程指南中文版 » 2024-06-01 20:37:13

#8 Re: 全志 SOC » 使用小麻雀直接驱动树莓派的DSI屏 » 2024-04-28 15:04:35

#9 Re: 全志 SOC » T113-S4 在售没有 » 2024-03-25 12:48:42

#10 Re: 全志 SOC » 分享一个自己做的T113-S3裸机IAR工程，有bootloader和led闪烁demo » 2023-11-13 03:10:33

#11 Re: 全志 SOC » 分享一个自己做的T113-S3裸机IAR工程，有bootloader和led闪烁demo » 2023-10-21 00:45:41

#12 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-10-10 14:24:14

#13 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-10-01 01:56:58

#14 Re: 全志 SOC » 分享一个自己做的T113-S3裸机IAR工程，有bootloader和led闪烁demo » 2023-09-22 01:12:31

#15 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-09-18 17:16:23

#16 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-07-16 10:05:17

#17 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-07-16 09:28:18

#18 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-07-15 02:37:03

#19 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-07-15 02:31:12

页脚