页次： 1
Run unmodified tina_d1s_mipi_rpi_uart0.img - uart shown this:
[00.395]line:714 init_clocks
__clk_init: clk pll_periph0x2 already initialized
register fix_factor clk error
[00.406]drv_disp_init
request pwm success, pwm2:pwm2:0x2000c00.
[00.422]drv_disp_init finish
[00.425]boot_gui_init:start
[00.428]set disp.dev2_output_type fail. using defval=0
[00.620]boot_gui_init:finish
partno erro : can't find partition bootloader
54 bytes read in 1 ms (52.7 KiB/s)
[00.989]bmp_name=bootlogo.bmp size 307254
307254 bytes read in 28 ms (10.5 MiB/s)
[01.031]LCD open finishWhy disp.dev2_output_type fail ?
Display not shown anything. Backlight turned on by hardware.
Start second core on T113-s3:
// 3.4.2.4 CPU0 Hotplug Process
//
// The Hotplug Flag Register is 0x070005C0.
// The Soft Entry Address Register is 0x070005C4.
// 3.4.2.3 NON_CPU0 Boot Process
//
// The Soft Entry Address Register of CPU0 is 0x070005C4
// The Soft Entry Address Register of CPU1 is 0x070005C8
#define HARDWARE_HOTPLUG_FLAG 0xFA50392F // CPU Hotplug Flag value
// In Allwinner h133 this i/o block named R_CPUCFG
//#define HARDWARE_NCORES 2
static void aarch32_mp_cpuN_start(uintptr_t startfunc, unsigned targetcore)
{
const uint32_t CORE_RESET_MASK = UINT32_C(1) << targetcore; // CPUx_CORE_RESET
volatile uint32_t * const rvaddr = ((volatile uint32_t *) (R_CPUCFG_BASE + 0x1c4 + targetcore * 4));
ASSERT(startfunc != 0);
ASSERT(targetcore != 0);
C0_CPUX_CFG->C0_RST_CTRL &= ~ CORE_RESET_MASK;
* rvaddr = startfunc;
ASSERT(* rvaddr == startfunc);
dcache_clean_all(); // startup code should be copied in to sysram for example.
C0_CPUX_CFG->C0_RST_CTRL |= CORE_RESET_MASK;
}Each core has own cache, MMU, part of GIC
Registers definitions: https://whycan.com/files/members/12476/t113s3.zip
Dual-core baremetal t113-s3 project here
https://github.com/ua1arn/hftrx/tree/develop
RISC_CFG dumps on two boards:
F133-A:
06010000 00010000 4006E910 00000000 00000000 00000013 00000021 00000003 00000002
06010020 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010040 00000000 00000000 00000000 00000000 400010D8 00000000 00000000 00000000
06010060 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100A0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100C0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100E0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010100 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010120 00000000T113-s3:
06010000 00010000 400F95E0 00000000 00000000 00000013 00000021 00000003 00000002
06010020 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010040 00000000 00000000 00000000 00000000 BFFBBFF2 000000F7 00000000 00000000
06010060 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100A0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100C0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
060100E0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010100 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
06010120 00000000On T113-s3 RETITE_PC0_REG and RETITE_PC1_REG looks like meaningful
你们有HIFI4-DSP User Manual 和 Compiler ? 看来这个DSP好厉害 !
Local hobbyists make windows - hosted xtensa gcc. Under tests with t113-s3.
xtensa-hifi4-elf-gcc.exe (crosstool-NG 1.25.0) 10.3.0
Copyright (C) 2020 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.页次： 1