C文件
/********************************************************************************/
/* @file ad7124.c */
/* @version V1.00 */
/* $author: yuanxihua@21cn.com */
/* $Date: 2019/03/04 02:54 $ */
/* @brief SWM320RBT6 Series AD7124 Driver Sample Code */
/* */
/* @note */
/* Copyright (C) 2010-2019 PM9GZY Technology Corp. All rights reserved. */
/* */
/********************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "ad7124.h"
/*
_________________________________________________
| SWM320RBT6 AD7124 |
| |
| PP1 MISO1 <---- MISO |
| PP2 MOSI1 ----> MOSI |
| PP3 SCLK1 ----> SCLK |
| PP4 NSS1 ----> ANCS |
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AD7124_CS_L() GPIO_ClrBit(GPIOP, PIN4)
#define AD7124_CS_H() GPIO_SetBit(GPIOP, PIN4)
/* Private macro -------------------------------------------------------------*/
#define INVALID_VAL -1 /* Invalid argument */
#define COMM_ERR -2 /* Communication error on receive */
#define TIMEOUT -3 /* A timeout has occured */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
void AD7124_Init(void);
void AD7124_Reset(void);
/* Private functions ---------------------------------------------------------*/
void SPI1Init(void)
{
SPI_InitStructure SPI_initStruct;
PORT_Init(PORTP, PIN1, FUNMUX1_SPI1_MISO, 1);
PORT_Init(PORTP, PIN2, FUNMUX0_SPI1_MOSI, 0);
PORT_Init(PORTP, PIN3, FUNMUX1_SPI1_SCLK, 0);
GPIO_Init(GPIOP, PIN4, 1, 0, 0);AD7124_CS_H();//PORT_Init(PORTP, PIN4, FUNMUX0_SPI1_SSEL, 0);
SPI_initStruct.clkDiv = SPI_CLKDIV_64;//0.52US
SPI_initStruct.FrameFormat = SPI_FORMAT_SPI;
SPI_initStruct.SampleEdge = SPI_FIRST_EDGE;
SPI_initStruct.IdleLevel = SPI_LOW_LEVEL;
SPI_initStruct.WordSize = 8;
SPI_initStruct.Master = 1;
SPI_initStruct.RXHFullIEn = 0;
SPI_initStruct.TXEmptyIEn = 0;
SPI_initStruct.TXCompleteIEn = 0;
SPI_Init(SPI1, &SPI_initStruct);
SPI_Open(SPI1);
AD7124_Reset();
AD7124_Init();
}
void AD7124_Read_Register(ad7124_reg_t *reg)
{
uint8_t cmd=reg->addr+0x40,width=reg->size,admit=reg->rw;uint32_t val=0;
if(!(admit&AD7124_RO)){return;}
AD7124_CS_L();
SPI_ReadWrite(SPI1,cmd);while(width--){val<<=8;val|=SPI_ReadWrite(SPI1,0x55)&0xff;}reg->value=val;
AD7124_CS_H();
}
void AD7124_Write_Register(ad7124_reg_t *reg)
{
uint8_t cmd=reg->addr+0x00,width=reg->size,admit=reg->rw;uint32_t val=reg->value;
if(!(admit&AD7124_WO)){return;}
AD7124_CS_L();
SPI_ReadWrite(SPI1,cmd);while(width--){SPI_ReadWrite(SPI1,(val>>(width*8))&0xff);}
AD7124_CS_H();
}
void AD7124_Reset(void){AD7124_CS_L();for(uint8_t i=0;i<8;i++){SPI_ReadWrite(SPI1,0xFF);}AD7124_CS_H();osDelay(10);}
void AD7124_Init(void){for(uint8_t i=AD7124_Status;i<AD7124_REG_END;i++){AD7124_Write_Register(&ad7124_regs[i]);}}
uint8_t AD7124_CRC8(uint8_t *buf, uint8_t len)
{
uint8_t i,crc=0,MULA=AD7124_CRC8_POLYNOMIAL_REPRESENTATION;
while(len--){for(i=0x80;i!=0;i>>=1){if(((crc&0x80)!=0)!=((*buf&i)!=0)){crc<<=1;crc^=MULA;}else{crc<<=1;}}buf++;}
return crc;
}
void AD7124_Gain(void){}
uint8_t AD7124_Read(uint32_t *data)
{
int32_t timeout=1000000;uint8_t total=0;
uint8_t lastch=20;uint8_t nowch=20;
while(1)
{
while(--timeout)
{
/* Read the value of the Status Register */
AD7124_Read_Register(&ad7124_regs[AD7124_Status]);
/* Check the RDY bit in the Status Register */
if((ad7124_regs[AD7124_Status].value & AD7124_STATUS_REG_RDY)==0)
{nowch = AD7124_STATUS_REG_CH_ACTIVE(ad7124_regs[AD7124_Status].value);break;}
}
if(timeout<=0){printf("AD Conv Timeout!!!\n\r");return total;}
if(lastch!=nowch)
{
/* Read the value of the Data Register */
AD7124_Read_Register(&ad7124_regs[AD7124_Data]);
/* Get the read result */
data[nowch] = ad7124_regs[AD7124_Data].value; data[nowch]&=0xFFFFFF;
lastch=nowch;total++;
// printf("AD7124_Read data[%d] = 0x%08x \n\r",nowch,data[nowch]);
}
if(total>=4){break;}
}
return total;
}
void AD7124_Test(void)
{
uint32_t adc[4]={0};float val[4];
// AD7124_CS_L(); SPI_ReadWrite(SPI1,0x55);AD7124_CS_H();
// AD7124_Read_Register(&ad7124_regs[AD7124_ID]);
// printf("AD7124_ID = 0x%02x \n\r",ad7124_regs[AD7124_ID].value);
// AD7124_Read_Register(&ad7124_regs[AD7124_CHANNEL_0]);
// printf("AD7124_CHANNEL_0 = 0x%08x \n\r",ad7124_regs[AD7124_CHANNEL_0].value);
// ad7124_regs[AD7124_FILTER_0].value=0x555555;
// AD7124_Write_Register(&ad7124_regs[AD7124_FILTER_0]);
// AD7124_Read_Register(&ad7124_regs[AD7124_FILTER_0]);
// printf("AD7124_FILTER_0 = 0x%08x \n\r",ad7124_regs[AD7124_FILTER_0].value);
// for(uint8_t i=AD7124_Status;i<AD7124_REG_END;i++)
// {
// AD7124_Read_Register(&ad7124_regs[i]);
// printf("ad7124_regs[0x%02x]=0x%08x \n\r",i,ad7124_regs[i].value);
// }
AD7124_Read(adc);
// printf("ADC[0]=0x%08x,ADC[1]=0x%08x,ADC[2]=0x%08x,ADC[3]=0x%08x\n\r",adc[0],adc[1],adc[2],adc[3]);
for(uint8_t i=0;i<4;i++)
{
val[i]=adc[i];val[i]*=2.500;val[i]/=0xffffff;
}
val[0]/=128;val[1]/=16;val[2]/=4;val[3]/=1;
// printf("VAL[0]=%3.10f V\n\r",val[0]);
// printf("VAL[1]=%3.10f V\n\r",val[1]);
// printf("VAL[2]=%3.10f V\n\r",val[2]);
// printf("VAL[3]=%3.10f V\n\r",val[3]);
// val[0]*=1000;val[1]*=1000;val[2]*=1000;val[3]*=1000;
printf("%3.10f,%3.10f,%3.10f,%3.10f\n\r",val[0],val[1],val[2],val[3]);
OLED_Volute(val);
osDelay(200);
}H文件
#ifndef __AD7124_H__
#define __AD7124_H__
#define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */
#define AD7124_WO 1 /* Write */
#define AD7124_RO 2 /* Read */
#define AD7124_RW 3 /* Read and Write */
/* AD7124 Register Map */
#define AD7124_COMM_REG 0x00
#define AD7124_STATUS_REG 0x00
#define AD7124_ADC_CTRL_REG 0x01
#define AD7124_DATA_REG 0x02
#define AD7124_IO_CTRL1_REG 0x03
#define AD7124_IO_CTRL2_REG 0x04
#define AD7124_ID_REG 0x05
#define AD7124_ERR_REG 0x06
#define AD7124_ERREN_REG 0x07
#define AD7124_CH0_MAP_REG 0x09
#define AD7124_CH1_MAP_REG 0x0A
#define AD7124_CH2_MAP_REG 0x0B
#define AD7124_CH3_MAP_REG 0x0C
#define AD7124_CH4_MAP_REG 0x0D
#define AD7124_CH5_MAP_REG 0x0E
#define AD7124_CH6_MAP_REG 0x0F
#define AD7124_CH7_MAP_REG 0x10
#define AD7124_CH8_MAP_REG 0x11
#define AD7124_CH9_MAP_REG 0x12
#define AD7124_CH10_MAP_REG 0x13
#define AD7124_CH11_MAP_REG 0x14
#define AD7124_CH12_MAP_REG 0x15
#define AD7124_CH13_MAP_REG 0x16
#define AD7124_CH14_MAP_REG 0x17
#define AD7124_CH15_MAP_REG 0x18
#define AD7124_CFG0_REG 0x19
#define AD7124_CFG1_REG 0x1A
#define AD7124_CFG2_REG 0x1B
#define AD7124_CFG3_REG 0x1C
#define AD7124_CFG4_REG 0x1D
#define AD7124_CFG5_REG 0x1E
#define AD7124_CFG6_REG 0x1F
#define AD7124_CFG7_REG 0x20
#define AD7124_FILT0_REG 0x21
#define AD7124_FILT1_REG 0x22
#define AD7124_FILT2_REG 0x23
#define AD7124_FILT3_REG 0x24
#define AD7124_FILT4_REG 0x25
#define AD7124_FILT5_REG 0x26
#define AD7124_FILT6_REG 0x27
#define AD7124_FILT7_REG 0x28
#define AD7124_OFFS0_REG 0x29
#define AD7124_OFFS1_REG 0x2A
#define AD7124_OFFS2_REG 0x2B
#define AD7124_OFFS3_REG 0x2C
#define AD7124_OFFS4_REG 0x2D
#define AD7124_OFFS5_REG 0x2E
#define AD7124_OFFS6_REG 0x2F
#define AD7124_OFFS7_REG 0x30
#define AD7124_GAIN0_REG 0x31
#define AD7124_GAIN1_REG 0x32
#define AD7124_GAIN2_REG 0x33
#define AD7124_GAIN3_REG 0x34
#define AD7124_GAIN4_REG 0x35
#define AD7124_GAIN5_REG 0x36
#define AD7124_GAIN6_REG 0x37
#define AD7124_GAIN7_REG 0x38
/* Communication Register bits */
#define AD7124_COMM_REG_WEN (0 << 7)
#define AD7124_COMM_REG_WR (0 << 6)
#define AD7124_COMM_REG_RD (1 << 6)
#define AD7124_COMM_REG_RA(x) ((x) & 0x3F)
/* Status Register bits */
#define AD7124_STATUS_REG_RDY (1 << 7)
#define AD7124_STATUS_REG_ERROR_FLAG (1 << 6)
#define AD7124_STATUS_REG_POR_FLAG (1 << 4)
#define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF)
/* ADC_Control Register bits */
#define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL (1 << 12)
#define AD7124_ADC_CTRL_REG_CONT_READ (1 << 11)
#define AD7124_ADC_CTRL_REG_DATA_STATUS (1 << 10)
#define AD7124_ADC_CTRL_REG_CS_EN (1 << 9)
#define AD7124_ADC_CTRL_REG_REF_EN (1 << 8)
#define AD7124_ADC_CTRL_REG_POWER_MODE(x) (((x) & 0x3) << 6)
#define AD7124_ADC_CTRL_REG_MODE(x) (((x) & 0xF) << 2)
#define AD7124_ADC_CTRL_REG_CLK_SEL(x)) (((x) & 0x3) << 0)
/* IO_Control_1 Register bits */
#define AD7124_IO_CTRL1_REG_GPIO_DAT2 (1 << 23)
#define AD7124_IO_CTRL1_REG_GPIO_DAT1 (1 << 22)
#define AD7124_IO_CTRL1_REG_GPIO_CTRL2 (1 << 19)
#define AD7124_IO_CTRL1_REG_GPIO_CTRL1 (1 << 18)
#define AD7124_IO_CTRL1_REG_PDSW (1 << 15)
#define AD7124_IO_CTRL1_REG_IOUT1(x) (((x) & 0x7) << 11)
#define AD7124_IO_CTRL1_REG_IOUT0(x) (((x) & 0x7) << 8)
#define AD7124_IO_CTRL1_REG_IOUT_CH1(x) (((x) & 0xF) << 4)
#define AD7124_IO_CTRL1_REG_IOUT_CH0(x) (((x) & 0xF) << 0)
/*IO_Control_1 AD7124-8 specific bits */
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 (1 << 23)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT3 (1 << 22)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT2 (1 << 21)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT1 (1 << 20)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4 (1 << 19)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3 (1 << 18)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2 (1 << 17)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1 (1 << 16)
/* IO_Control_2 Register bits */
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 15)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 14)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 11)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 10)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 5)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 4)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0)
/*IO_Control_2 AD7124-8 specific bits */
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15 (1 << 15)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14 (1 << 14)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13 (1 << 13)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12 (1 << 12)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11 (1 << 11)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10 (1 << 10)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9 (1 << 9)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8 (1 << 8)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 7)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 6)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 5)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 4)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 3)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 2)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0)
/* ID Register bits */
#define AD7124_ID_REG_DEVICE_ID(x) (((x) & 0xF) << 4)
#define AD7124_ID_REG_SILICON_REV(x) (((x) & 0xF) << 0)
/* Error Register bits */
#define AD7124_ERR_REG_LDO_CAP_ERR (1 << 19)
#define AD7124_ERR_REG_ADC_CAL_ERR (1 << 18)
#define AD7124_ERR_REG_ADC_CONV_ERR (1 << 17)
#define AD7124_ERR_REG_ADC_SAT_ERR (1 << 16)
#define AD7124_ERR_REG_AINP_OV_ERR (1 << 15)
#define AD7124_ERR_REG_AINP_UV_ERR (1 << 14)
#define AD7124_ERR_REG_AINM_OV_ERR (1 << 13)
#define AD7124_ERR_REG_AINM_UV_ERR (1 << 12)
#define AD7124_ERR_REG_REF_DET_ERR (1 << 11)
#define AD7124_ERR_REG_DLDO_PSM_ERR (1 << 9)
#define AD7124_ERR_REG_ALDO_PSM_ERR (1 << 7)
#define AD7124_ERR_REG_SPI_IGNORE_ERR (1 << 6)
#define AD7124_ERR_REG_SPI_SLCK_CNT_ERR (1 << 5)
#define AD7124_ERR_REG_SPI_READ_ERR (1 << 4)
#define AD7124_ERR_REG_SPI_WRITE_ERR (1 << 3)
#define AD7124_ERR_REG_SPI_CRC_ERR (1 << 2)
#define AD7124_ERR_REG_MM_CRC_ERR (1 << 1)
/* Error_En Register bits */
#define AD7124_ERREN_REG_MCLK_CNT_EN (1 << 22)
#define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN (1 << 21)
#define AD7124_ERREN_REG_LDO_CAP_CHK(x) (((x) & 0x3) << 19)
#define AD7124_ERREN_REG_ADC_CAL_ERR_EN (1 << 18)
#define AD7124_ERREN_REG_ADC_CONV_ERR_EN (1 << 17)
#define AD7124_ERREN_REG_ADC_SAT_ERR_EN (1 << 16)
#define AD7124_ERREN_REG_AINP_OV_ERR_EN (1 << 15)
#define AD7124_ERREN_REG_AINP_UV_ERR_EN (1 << 14)
#define AD7124_ERREN_REG_AINM_OV_ERR_EN (1 << 13)
#define AD7124_ERREN_REG_AINM_UV_ERR_EN (1 << 12)
#define AD7124_ERREN_REG_REF_DET_ERR_EN (1 << 11)
#define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN (1 << 10)
#define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR (1 << 9)
#define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN (1 << 8)
#define AD7124_ERREN_REG_ALDO_PSM_ERR_EN (1 << 7)
#define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN (1 << 6)
#define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN (1 << 5)
#define AD7124_ERREN_REG_SPI_READ_ERR_EN (1 << 4)
#define AD7124_ERREN_REG_SPI_WRITE_ERR_EN (1 << 3)
#define AD7124_ERREN_REG_SPI_CRC_ERR_EN (1 << 2)
#define AD7124_ERREN_REG_MM_CRC_ERR_EN (1 << 1)
/* Channel Registers 0-15 bits */
#define AD7124_CH_MAP_REG_CH_ENABLE (1 << 15)
#define AD7124_CH_MAP_REG_SETUP(x) (((x) & 0x7) << 12)
#define AD7124_CH_MAP_REG_AINP(x) (((x) & 0x1F) << 5)
#define AD7124_CH_MAP_REG_AINM(x) (((x) & 0x1F) << 0)
/* Configuration Registers 0-7 bits */
#define AD7124_CFG_REG_BIPOLAR (1 << 11)
#define AD7124_CFG_REG_BURNOUT(x) (((x) & 0x3) << 9)
#define AD7124_CFG_REG_REF_BUFP (1 << 8)
#define AD7124_CFG_REG_REF_BUFM (1 << 7)
#define AD7124_CFG_REG_AIN_BUFP (1 << 6)
#define AD7124_CFG_REG_AINN_BUFM (1 << 5)
#define AD7124_CFG_REG_REF_SEL(x) ((x) & 0x3) << 3
#define AD7124_CFG_REG_PGA(x) (((x) & 0x7) << 0)
/* Filter Register 0-7 bits */
#define AD7124_FILT_REG_FILTER(x) (((x) & 0x7) << 21)
#define AD7124_FILT_REG_REJ60 (1 << 20)
#define AD7124_FILT_REG_POST_FILTER(x) (((x) & 0x7) << 17)
#define AD7124_FILT_REG_SINGLE_CYCLE (1 << 16)
#define AD7124_FILT_REG_FS(x) (((x) & 0x7FF) << 0)
/*! Device register info */
typedef struct
{
uint8_t addr;
int32_t value;
uint8_t size;
uint8_t rw;
}ad7124_reg_t;
/*! Array holding the info for the ad7124 registers - address, initial value,
size and access type. */
ad7124_reg_t ad7124_regs[] =
{
{0x00, 0x00, 1, AD7124_RO}, /* AD7124_Status */
//使能DATA_STATUS、REF_EN 和 FULL POWER的连续采样模式，禁止用DOUT_RDY_DEL、CONT_READ和CS_EN，内时钟CLK无输出
{0x01, 0x0580, 2, AD7124_RW}, /* AD7124_ADC_Control */
{0x02, 0x000000, 3, AD7124_RO}, /* AD7124_Data */
//禁用IOUT0、IOUT1、不用PDSW低边桥开关
{0x03, 0x000000, 3, AD7124_RW}, /* AD7124_IOCon1 */
//禁用VBIAS0-VBIAS7
{0x04, 0x0000, 2, AD7124_RW}, /* AD7124_IOCon2 */
{0x05, 0x04, 1, AD7124_RO}, /* AD7124_ID */
{0x06, 0x000000, 3, AD7124_RO}, /* AD7124_Error */
//不用ERROR功能
{0x07, 0x000000, 3, AD7124_RW}, /* AD7124_Error_En */
{0x08, 0x00, 1, AD7124_RO}, /* AD7124_Mclk_Count */
//使能通道0、选择Setup0配置组、输入脚分配AIN0->AINP,AIN1->AINM
{0x09, 0x8001, 2, AD7124_RW}, /* AD7124_Channel_0 */
//使能通道1、选择Setup1配置组、输入脚分配AIN2->AINP,AIN3->AINM
{0x0A, 0x9043, 2, AD7124_RW}, /* AD7124_Channel_1 */
//使能通道2、选择Setup2配置组、输入脚分配AIN4->AINP,AIN5->AINM
{0x0B, 0xA085, 2, AD7124_RW}, /* AD7124_Channel_2 */
//使能通道3、选择Setup3配置组、输入脚分配AIN6->AINP,AIN7->AINM
{0x0C, 0xB0C7, 2, AD7124_RW}, /* AD7124_Channel_3 */
{0x0D, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_4 */
{0x0E, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_5 */
{0x0F, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_6 */
{0x10, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_7 */
{0x11, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_8 */
{0x12, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_9 */
{0x13, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_10 */
{0x14, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_11 */
{0x15, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_12 */
{0x16, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_13 */
{0x17, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_14 */
{0x18, 0x0000, 2, AD7124_RW}, /* AD7124_Channel_15 */
//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=128
{0x19, 0x01F7, 2, AD7124_RW}, /* AD7124_Config_0 */
//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=16
{0x1A, 0x01F4, 2, AD7124_RW}, /* AD7124_Config_1 */
//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=4
{0x1B, 0x01F2, 2, AD7124_RW}, /* AD7124_Config_2 */
//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=1
{0x1C, 0x01F0, 2, AD7124_RW}, /* AD7124_Config_3 */
{0x1D, 0x09F0, 2, AD7124_RW}, /* AD7124_Config_4 */
{0x1E, 0x09F0, 2, AD7124_RW}, /* AD7124_Config_5 */
{0x1F, 0x09F0, 2, AD7124_RW}, /* AD7124_Config_6 */
{0x20, 0x09F0, 2, AD7124_RW}, /* AD7124_Config_7 */
{0x21, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_0 */
{0x22, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_1 */
{0x23, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_2 */
{0x24, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_3 */
{0x25, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_4 */
{0x26, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_5 */
{0x27, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_6 */
{0x28, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_7 */
{0x29, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_0 */
{0x2A, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_1 */
{0x2B, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_2 */
{0x2C, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_3 */
{0x2D, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_4 */
{0x2E, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_5 */
{0x2F, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_6 */
{0x30, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_7 */
//增益寄存器
{0x31, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_0 */
//增益寄存器
{0x32, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_1 */
//增益寄存器
{0x33, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_2 */
//增益寄存器
{0x34, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_3 */
{0x35, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_4 */
{0x36, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_5 */
{0x37, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_6 */
{0x38, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_7 */
};
/*! AD7124 registers list*/
enum ad7124_registers
{
AD7124_Status = 0x00,
AD7124_ADC_CONTROL,
AD7124_Data,
AD7124_IOCONTROL_1,
AD7124_IOCONTROL_2,
AD7124_ID,
AD7124_Error,
AD7124_ERROR_EN,
AD7124_MCLK_COUNT,
AD7124_CHANNEL_0,
AD7124_CHANNEL_1,
AD7124_CHANNEL_2,
AD7124_CHANNEL_3,
AD7124_CHANNEL_4,
AD7124_CHANNEL_5,
AD7124_CHANNEL_6,
AD7124_CHANNEL_7,
AD7124_CHANNEL_8,
AD7124_CHANNEL_9,
AD7124_CHANNEL_10,
AD7124_CHANNEL_11,
AD7124_CHANNEL_12,
AD7124_CHANNEL_13,
AD7124_CHANNEL_14,
AD7124_CHANNEL_15,
AD7124_CONFIG_0,
AD7124_CONFIG_1,
AD7124_CONFIG_2,
AD7124_CONFIG_3,
AD7124_CONFIG_4,
AD7124_CONFIG_5,
AD7124_CONFIG_6,
AD7124_CONFIG_7,
AD7124_FILTER_0,
AD7124_FILTER_1,
AD7124_FILTER_2,
AD7124_FILTER_3,
AD7124_FILTER_4,
AD7124_FILTER_5,
AD7124_FILTER_6,
AD7124_FILTER_7,
AD7124_OFFSET_0,
AD7124_OFFSET_1,
AD7124_OFFSET_2,
AD7124_OFFSET_3,
AD7124_OFFSET_4,
AD7124_OFFSET_5,
AD7124_OFFSET_6,
AD7124_OFFSET_7,
AD7124_GAIN_0,
AD7124_GAIN_1,
AD7124_GAIN_2,
AD7124_GAIN_3,
AD7124_GAIN_4,
AD7124_GAIN_5,
AD7124_GAIN_6,
AD7124_GAIN_7,
AD7124_REG_END
};
#endif /* __AD7124_H__ */最近编辑记录 缥缈九哥 (2020-05-09 23:20:39)
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