struct dram_para suniv_dram_para = {
.size = 32,
/*.clk = 156,*/
.clk = CONFIG_DRAM_CLK,
.access_mode = 1,
.cs_num = 1,
.ddr8_remap = 0,
.sdr_ddr = DRAM_TYPE_DDR,
.bwidth = 16,
.col_width = 10,
.row_width = 13,
.bank_size = 4,
.cas = 0x3,
};# CONFIG_MACH_SUN50I_H5 is not set
# CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER is not set
CONFIG_DRAM_CLK=156
CONFIG_DRAM_ZQ=0
# CONFIG_DRAM_ODT_EN is not set
CONFIG_SYS_CLK_FREQ=608000000
# CONFIG_UART0_PORT_F is not set
# CONFIG_OLD_SUNXI_KERNEL_COMPAT is not set
CONFIG_MACPWR=""Uboot 版本 u-boot-nano-v2018.01 修改ddr 修改是成功了，但是没运行多久就会报错，不稳定，目前不知道CPU 主频这样改是不是可以的，担心这个宏 没有生效。。源文件全局搜索貌似没有用到这个宏CONFIG_SYS_CLK_FREQ，
root@virtual-machine:/home/f1c100s/uboot/nano-uboot-2018.1/u-boot# find . -name "*.c" | xargs grep "CONFIG_SYS_CLK_FREQ"
./drivers/mmc/ftsdc010_mci.c:#ifdef CONFIG_SYS_CLK_FREQ
./drivers/mmc/ftsdc010_mci.c: chip->sclk = CONFIG_SYS_CLK_FREQ;
./drivers/serial/serial_lpuart.c:#ifndef CONFIG_SYS_CLK_FREQ
./drivers/serial/serial_lpuart.c:#define CONFIG_SYS_CLK_FREQ 0
./drivers/serial/serial_lpuart.c: return CONFIG_SYS_CLK_FREQ;
./board/sbc8641d/sbc8641d.c: * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
./board/sbc8548/sbc8548.c: uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
./board/renesas/gose/gose.c: stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
./board/renesas/porter/porter.c: stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
./board/renesas/eagle/eagle.c: stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
./board/renesas/koelsch/koelsch.c: stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
./board/renesas/stout/stout.c: u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
./board/renesas/lager/lager.c: u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
./board/xes/common/fsl_8xxx_pci.c: uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
./board/freescale/p1_p2_rdb_pc/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/p1_p2_rdb_pc/spl.c: bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/mpc8610hpcd/mpc8610hpcd.c: * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
./board/freescale/t208xrdb/t208xrdb.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/t208xrdb/spl.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/c29xpcie/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/c29xpcie/spl.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/t4rdb/spl.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/bsc9131rdb/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/mpc8641hpcn/mpc8641hpcn.c: * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
./board/freescale/mpc8548cds/mpc8548cds.c: if (CONFIG_SYS_CLK_FREQ < 66000000)
./board/freescale/bsc9132qds/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/t102xrdb/t102xrdb.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/t102xrdb/spl.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/t104xrdb/spl.c: return CONFIG_SYS_CLK_FREQ;
./board/freescale/p1010rdb/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/freescale/p1010rdb/spl.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/socrates/socrates.c: f = CONFIG_SYS_CLK_FREQ;
./board/Arcturus/ucp1020/spl_minimal.c: gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/Arcturus/ucp1020/spl.c: bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
./board/sunxi/board.c: clock_set_pll1(CONFIG_SYS_CLK_FREQ);
./arch/powerpc/cpu/mpc85xx/fdt.c: "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
./arch/powerpc/cpu/mpc85xx/fdt.c: "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
./arch/powerpc/cpu/mpc85xx/speed.c: unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
./arch/powerpc/cpu/mpc85xx/speed.c: sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
./arch/powerpc/cpu/mpc85xx/speed.c: sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
./arch/powerpc/cpu/mpc85xx/speed.c: sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
./arch/powerpc/cpu/mpc85xx/pci.c: if (CONFIG_SYS_CLK_FREQ < 66000000)
./arch/powerpc/cpu/mpc86xx/speed.c:/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
./arch/powerpc/cpu/mpc86xx/speed.c: sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
./arch/powerpc/cpu/mpc86xx/speed.c: sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
./arch/arm/mach-stm32/stm32f7/timer.c: writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1,
./arch/arm/mach-stm32/stm32f4/clock.c:#if (CONFIG_SYS_CLK_FREQ == 180000000)
./arch/arm/mach-s5pc1xx/clock.c:#ifndef CONFIG_SYS_CLK_FREQ_C100
./arch/arm/mach-s5pc1xx/clock.c:#define CONFIG_SYS_CLK_FREQ_C100 12000000
./arch/arm/mach-s5pc1xx/clock.c:#ifndef CONFIG_SYS_CLK_FREQ_C110
./arch/arm/mach-s5pc1xx/clock.c:#define CONFIG_SYS_CLK_FREQ_C110 24000000
./arch/arm/mach-s5pc1xx/clock.c: freq = CONFIG_SYS_CLK_FREQ_C100;
./arch/arm/mach-s5pc1xx/clock.c: freq = CONFIG_SYS_CLK_FREQ_C110;
./arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
./arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
./arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c: unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
./arch/arm/cpu/armv8/fsl-layerscape/fdt.c: if (CONFIG_SYS_CLK_FREQ != 100000000) {
./arch/arm/cpu/armv8/fsl-layerscape/fdt.c: CONFIG_SYS_CLK_FREQ, 1);
./arch/arm/cpu/arm920t/ep93xx/speed.c: * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
./arch/arm/cpu/arm920t/ep93xx/speed.c: * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
./arch/arm/cpu/arm920t/ep93xx/speed.c: uint64_t rate = CONFIG_SYS_CLK_FREQ;
./arch/arm/cpu/arm920t/ep93xx/speed.c: uclk_rate = CONFIG_SYS_CLK_FREQ;
./arch/arm/cpu/arm920t/ep93xx/speed.c: uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
./arch/arm/cpu/arm920t/imx/speed.c: * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
./arch/arm/cpu/arm920t/imx/speed.c: return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
./arch/arm/cpu/armv7/ls102xa/fdt.c: CONFIG_SYS_CLK_FREQ, 1);
./arch/arm/cpu/armv7/ls102xa/fdt.c: "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
./arch/arm/cpu/armv7/ls102xa/clock.c: unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
./arch/arm/mach-exynos/clock.c: freq = CONFIG_SYS_CLK_FREQ;
./arch/arm/mach-exynos/clock.c: sclk = CONFIG_SYS_CLK_FREQ;
./arch/xtensa/lib/time.c: ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
./arch/xtensa/lib/time.c: return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
./arch/xtensa/lib/time.c: return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
./arch/xtensa/lib/time.c: return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
./arch/arc/lib/cpu.c: gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
./arch/nds32/cpu/n1213/ag101/timer.c: (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
./arch/nds32/cpu/n1213/ag101/timer.c: (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
./arch/nds32/cpu/n1213/ag101/timer.c: long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
./arch/nds32/cpu/n1213/ag101/timer.c: return CONFIG_SYS_CLK_FREQ;
root@ll-virtual-machine:/home/ll/f1c100s/uboot/nano-uboot-2018.1/u-boot#
root@ll-virtual-machine:/home/ll/f1c100s/uboot/nano-uboot-2018.1/u-boot#
root@ll-virtual-machine:/home/ll/f1c100s/uboot/nano-uboot-2018.1/u-boot# find . -name "*.c" | xargs grep "408"
./drivers/net/xilinx_axi_emac.c: u32 tc; /* 0x408: Tx Configuration */
./drivers/usb/eth/r8152_fw.c: 0x6408, 0x0000, 0x0000, 0x7d00, 0x6800, 0xb603, 0x7c10, 0x6010,
./drivers/usb/gadget/storage_common.c:#define SS_COMMUNICATION_FAILURE 0x040800
./drivers/usb/common/fsl-errata.c: case SVR_T4080:
./drivers/usb/common/fsl-errata.c: case SVR_P4080:
./drivers/usb/common/fsl-errata.c: case SVR_T4080:
./drivers/usb/common/fsl-errata.c: case SVR_P4080:
./drivers/usb/musb-new/sunxi.c:#define USBC_REG_o_PHYBIST 0x0408
./drivers/ddr/marvell/axp/ddr3_spd.c: /* {0x00001408} - DDR SDRAM Timing (Low) Register */
./drivers/mtd/nand/zynq_nand.c: u32 emcmd1r; /* 0x408 */
./drivers/gpio/pca953x_gpio.c: { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
./drivers/pci/fsl_pci_init.c:#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
./drivers/fpga/zynqpl.c:#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
./drivers/clk/renesas/clk-rcar-gen3.c: DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
./drivers/clk/renesas/clk-rcar-gen3.c: DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
./drivers/clk/renesas/clk-rcar-gen3.c: DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
./drivers/clk/renesas/clk-rcar-gen3.c: DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
./drivers/clk/renesas/clk-rcar-gen3.c: { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
./drivers/mmc/mv_sdhci.c:#define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
./drivers/mmc/mv_sdhci.c:#define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
./drivers/video/broadwell_igd.c: writel(0x00000000, regs + 0x9408);
./drivers/video/broadwell_igd.c: writel(0x00000000, regs + 0x9408);
./drivers/video/tegra124/display.c: clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
./drivers/video/formike.c: spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00);
./drivers/sound/wm8994.c: 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
./board/maxbcm/maxbcm.c: {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
./board/ti/ti814x/evm.c: .sdram_config = 0x40801ab2,
./board/ti/ti814x/evm.c: .sdram_config = 0x40801ab2,
./board/davinci/da8xxevm/da850evm.c: * 0010b - 408 MHz
./board/davinci/da8xxevm/da850evm.c: else if (maxcpuclk >= 408000000)
./board/davinci/da8xxevm/omapl138_lcdk.c: * 0010b - 408 MHz
./board/compulab/cl-som-imx7/spl.c: .init4 = 0x04080000,
./board/theadorable/theadorable.c: {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
./board/Barix/ipam390/ipam390.c: * 0010b - 408 MHz
./board/Barix/ipam390/ipam390.c: else if (maxcpuclk >= 408000000)
./board/Synology/ds414/ds414.c: {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x021b001c, 0x04088032,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x021b001c, 0x09408030,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x020c4080, 0x00000FFF,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x021b001c, 0x04088032,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x021b001c, 0x09408030,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x020c4080, 0x00000FFF,
./board/freescale/mx6sabreauto/mx6sabreauto.c: 0x020c4080, 0x00000FFF,
./board/freescale/mx6sabresd/mx6sabresd.c: 0x021b001c, 0x04088032,
./board/freescale/mx6sabresd/mx6sabresd.c: 0x021b001c, 0x09408030,
./board/freescale/mx6sabresd/mx6sabresd.c: 0x021b001c, 0x04088032,
./board/freescale/mx6sabresd/mx6sabresd.c: 0x021b001c, 0x09408030,
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO0",
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO1",
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO3",
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO4",
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO8",
./board/freescale/corenet_ds/eth_p4080.c: "P4080DS_MDIO12",
./board/freescale/corenet_ds/eth_p4080.c:static char *p4080ds_mdio_name_for_muxval(u32 muxval)
./board/freescale/corenet_ds/eth_p4080.c: char *name = p4080ds_mdio_name_for_muxval(muxval);
./board/freescale/corenet_ds/eth_p4080.c:#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
./board/freescale/corenet_ds/eth_p4080.c:struct p4080ds_mdio {
./board/freescale/corenet_ds/eth_p4080.c:static void p4080ds_mux_mdio(u32 muxval)
./board/freescale/corenet_ds/eth_p4080.c:static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
./board/freescale/corenet_ds/eth_p4080.c: struct p4080ds_mdio *priv = bus->priv;
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mux_mdio(priv->muxval);
./board/freescale/corenet_ds/eth_p4080.c:static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
./board/freescale/corenet_ds/eth_p4080.c: struct p4080ds_mdio *priv = bus->priv;
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mux_mdio(priv->muxval);
./board/freescale/corenet_ds/eth_p4080.c:static int p4080ds_mdio_reset(struct mii_dev *bus)
./board/freescale/corenet_ds/eth_p4080.c: struct p4080ds_mdio *priv = bus->priv;
./board/freescale/corenet_ds/eth_p4080.c:static int p4080ds_mdio_init(char *realbusname, u32 muxval)
./board/freescale/corenet_ds/eth_p4080.c: struct p4080ds_mdio *pmdio;
./board/freescale/corenet_ds/eth_p4080.c: printf("Failed to allocate P4080DS MDIO bus\n");
./board/freescale/corenet_ds/eth_p4080.c: printf("Failed to allocate P4080DS private data\n");
./board/freescale/corenet_ds/eth_p4080.c: bus->read = p4080ds_mdio_read;
./board/freescale/corenet_ds/eth_p4080.c: bus->write = p4080ds_mdio_write;
./board/freescale/corenet_ds/eth_p4080.c: bus->reset = p4080ds_mdio_reset;
./board/freescale/corenet_ds/eth_p4080.c: sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
./board/freescale/corenet_ds/eth_p4080.c: * P4080DS can be configured in many different ways, supporting a number
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
./board/freescale/corenet_ds/eth_p4080.c: p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
./board/freescale/corenet_ds/eth_hydra.c: * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
./board/freescale/corenet_ds/eth_hydra.c: * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
./board/freescale/corenet_ds/corenet_ds.c: * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
./board/freescale/corenet_ds/corenet_ds.c: * p4080_erratum_serdes8(), since that function may modify the clocks.
./board/freescale/corenet_ds/eth_superhydra.c: * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
./board/freescale/corenet_ds/eth_superhydra.c: * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
./board/freescale/corenet_ds/eth_superhydra.c: * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
./board/freescale/m54455evb/m54455evb.c: out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
./board/freescale/t102xrdb/t102xrdb.c: i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
./board/freescale/t102xrdb/t102xrdb.c: i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
./board/freescale/t102xrdb/t102xrdb.c: i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
./board/freescale/t102xrdb/t102xrdb.c: i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
./board/freescale/t102xrdb/t102xrdb.c: i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
./board/freescale/t102xrdb/t102xrdb.c: i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
./board/freescale/t102xrdb/t102xrdb.c: i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
./board/freescale/t102xrdb/t102xrdb.c: i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
./board/toradex/colibri_imx6/colibri_imx6.c:/* MX6_MMDC_P0_MDSCR, 0x04408032, */
./board/toradex/colibri_imx6/colibri_imx6.c:/* MX6_MMDC_P0_MDSCR, 0x04408032, */
./board/toradex/apalis_imx6/apalis_imx6.c:MX6_MMDC_P0_MDSCR, 0x04088032,
./board/toradex/apalis_imx6/apalis_imx6.c:MX6_MMDC_P0_MDSCR, 0x19408030,
./board/intel/cherryhill/cherryhill.c: NA, 1, NA, 0x4408, NORTH),
./board/intel/cherryhill/cherryhill.c: NA, 47, NA, 0x5408, NORTH),
./board/intel/cherryhill/cherryhill.c: NA, 1, NA, 0x4408, EAST),
./board/intel/cherryhill/cherryhill.c: NA, 1, NA, 0x4408, SOUTHEAST),
./board/intel/cherryhill/cherryhill.c: NA, 35, NA, 0x5408, SOUTHEAST),
./board/intel/cherryhill/cherryhill.c: NA, 1, NA, 0x4408, SOUTHWEST),
./lib/md5.c: MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
./lib/bzip2/bzlib_crctable.c: 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
./lib/crc16.c: 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
./arch/powerpc/cpu/mpc8xxx/cpu.c: CPU_TYPE_ENTRY(P4080, P4080, 8),
./arch/powerpc/cpu/mpc8xxx/cpu.c: CPU_TYPE_ENTRY(T4080, T4080, 4),
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_ARCH_P4080
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: * To avoid the situation that resulted in the P4080 erratum
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: p4080_erratum_serdes_a005(srds_regs, cfg);
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
./arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
./arch/powerpc/cpu/mpc85xx/fdt.c:#if defined(CONFIG_ARCH_P4080)
./arch/powerpc/cpu/mpc85xx/speed.c: case SVR_T4080:
./arch/powerpc/cpu/mpc85xx/cpu_init.c: /* only the L2 of first cluster should be enabled as expected on T4080,
./arch/powerpc/cpu/mpc85xx/cpu_init.c: if (SVR_SOC_VER(svr) == SVR_T4080)
./arch/powerpc/cpu/mpc85xx/cpu_init.c:#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
./arch/powerpc/cpu/mpc85xx/cpu_init.c: * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
./arch/powerpc/cpu/mpc85xx/cpu_init.c: * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
./arch/powerpc/cpu/mpc85xx/cpu_init.c:#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
./arch/powerpc/cpu/mpc85xx/cpu_init.c: (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
./arch/powerpc/cpu/mpc85xx/cpu_init.c: (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#ifdef CONFIG_ARCH_P4080
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#ifdef CONFIG_ARCH_P4080
./arch/powerpc/cpu/mpc85xx/cmd_errata.c: * For P4080, the erratum document says that the value at offset 0x108
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
./arch/powerpc/cpu/mpc85xx/cmd_errata.c: * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
./arch/powerpc/cpu/mpc85xx/cmd_errata.c:#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
./arch/powerpc/cpu/mpc85xx/cpu.c: if (SVR_SOC_VER(svr) == SVR_T4080) {
./arch/powerpc/cpu/mpc85xx/cpu.c: /* It needs SW to disable core4~7 as HW design sake on T4080 */
./arch/powerpc/cpu/mpc85xx/p4080_ids.c: * a 4080 rev.2 h/w requirement that DECOs sharing from themselves
./arch/powerpc/cpu/mpc85xx/p4080_serdes.c:#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
./arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c: 0x00000000, 0x00000000, 0x01000000, 0x01020408,
./arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c: 0x00040800,
./arch/arm/mach-imx/cache.c: val |= 0x40800000;
./arch/arm/mach-sunxi/clock_sun6i.c: clock_set_pll1(408000000);
./arch/arm/mach-sunxi/clock_sun8i_a83t.c: clock_set_pll1(408000000);
./arch/arm/mach-sunxi/clock_sun9i.c: clock_set_pll1(408000000);
./arch/arm/mach-sunxi/clock_sun9i.c: clock_set_pll2(408000000);
./arch/arm/mach-sunxi/dram_sun4i.c: } else if (clk >= 396 && clk < 408) {
./arch/arm/mach-rmobile/pfc-r8a7793.c: { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
./arch/arm/mach-rmobile/pfc-r8a7791.c: { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
./arch/arm/mach-rmobile/pfc-r8a7792.c: { PINMUX_DATA_REG("INDT9", 0xE6055408, 32) {
./arch/arm/mach-rmobile/pfc-r8a7794.c: { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
./arch/arm/mach-omap2/omap5/prcm-regs.c: .cm_l4per_dynamicdep = 0x4a009408,
./arch/arm/mach-omap2/omap4/prcm-regs.c: .cm_l4per_dynamicdep = 0x4a009408,
./arch/arm/mach-tegra/tegra124/cpu.c: * PLLP base of 408MHz.
./arch/arm/mach-tegra/clock.c: * 408MHz which is beyond system clock's upper limit.
./arch/arm/mach-tegra/clock.c: * PLLP output frequency set to 408Mhz
./arch/arm/mach-tegra/clock.c: clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
./arch/arm/mach-tegra/clock.c: clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
./arch/arm/mach-tegra/clock.c: clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
./arch/arm/mach-tegra/clock.c: reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
./arch/arm/mach-tegra/clock.c: | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
./arch/arm/mach-tegra/clock.c: reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
./arch/arm/mach-tegra/clock.c: | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
./arch/arm/mach-tegra/tegra210/clock.c: * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
./arch/arm/mach-tegra/tegra210/clock.c: reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
./arch/arm/mach-tegra/tegra210/clock.c: reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
./arch/arm/mach-tegra/tegra210/clock.c: | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
./arch/arm/mach-tegra/tegra114/cpu.c: * to 408 to satisfy the requirement of having at least 16 CPU clock
./arch/arm/mach-tegra/tegra114/cpu.c: setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
./arch/arm/mach-tegra/tegra114/cpu.c: * PLLP base of 408MHz.
./arch/arm/mach-tegra/cpu.c: * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
./arch/x86/cpu/ivybridge/sata.c: pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
./arch/x86/cpu/ivybridge/sdram.c: * ff800000 4088MB MEBASE
./arch/x86/cpu/ivybridge/sdram.c: * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
./scripts/kconfig/zconf.tab.c: 383, 386, 388, 389, 390, 393, 401, 408, 415, 421,CONFIG_SYS_CLK_FREQ 宏的默认值是 408000000
./arch/arm/mach-sunxi/clock_sun6i.c: clock_set_pll1(408000000);
./arch/arm/mach-sunxi/clock_sun8i_a83t.c: clock_set_pll1(408000000);最近编辑记录 小熊猫 (2020-09-23 11:15:25)
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devem 修改的，不知道地址，也没datasheet ，这个帖子看了
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自己 up up
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