目前遇到的问题如下：
按照linux4.14版本内核的设备树配置了6.1的LCD部分。但是使用的是drm方式，但是会提示如下错误：
[ 0.814794] panel-simple panel: supply power not found, using dummy regulator
[ 0.815406] ------------[ cut here ]------------
[ 0.815435] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/panel/panel-simple.c:623 panel_simple_probe+0x578/0x6dc
[ 0.815539] Modules linked in:
[ 0.815566] CPU: 0 PID: 1 Comm: swapper Not tainted 6.1.0-rc6-licheepi-nano #6
[ 0.815598] Hardware name: Allwinner suniv Family
[ 0.815632] unwind_backtrace from show_stack+0x10/0x14
[ 0.815722] show_stack from dump_stack_lvl+0x28/0x30
[ 0.815785] dump_stack_lvl from __warn+0xdc/0xf4
[ 0.815823] __warn from warn_slowpath_fmt+0xa8/0xb8
[ 0.815860] warn_slowpath_fmt from panel_simple_probe+0x578/0x6dc
[ 0.815918] panel_simple_probe from platform_probe+0x58/0xb8
[ 0.815974] platform_probe from really_probe+0xc4/0x2ac
[ 0.816042] really_probe from __driver_probe_device+0x80/0xe4
[ 0.816106] __driver_probe_device from driver_probe_device+0x30/0xdc
[ 0.816172] driver_probe_device from __driver_attach+0x8c/0x110
[ 0.816238] __driver_attach from bus_for_each_dev+0x70/0xb4
[ 0.816303] bus_for_each_dev from bus_add_driver+0x158/0x1ec
[ 0.816362] bus_add_driver from driver_register+0x74/0x10c
[ 0.816429] driver_register from panel_simple_init+0x10/0x48
[ 0.816505] panel_simple_init from do_one_initcall+0x48/0x240
[ 0.816562] do_one_initcall from kernel_init_freeable+0x180/0x1fc
[ 0.816638] kernel_init_freeable from kernel_init+0x10/0x130
[ 0.816690] kernel_init from ret_from_fork+0x14/0x2c
[ 0.816726] Exception stack(0xc480dfb0 to 0xc480dff8)
[ 0.816761] dfa0: 00000000 00000000 00000000 00000000
[ 0.816796] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.816826] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 0.816844] ---[ end trace 0000000000000000 ]---
设备树如下:
<suniv-f1c100s.dtsi>：
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
* Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
*/
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
clocks {
osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
};
cpus {
// #address-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
// reg = <0x0>;
};
};
de: display-engine {
compatible = "allwinner,suniv-f1c100s-display-engine";
allwinner,pipelines = <&fe0>;
status = "disabled";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,suniv-f1c100s-system-control",
"allwinner,sun4i-a10-system-control",
"allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_d: sram@10000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
compatible = "allwinner,suniv-f1c100s-sram-d",
"allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
};
spi0: spi@1c05000 {
compatible = "allwinner,suniv-f1c100s-spi",
"allwinner,sun8i-h3-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@1c06000 {
compatible = "allwinner,suniv-f1c100s-spi",
"allwinner,sun8i-h3-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_SPI1>;
status = "disabled";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,suniv-f1c100s-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <29>;
clocks = <&ccu CLK_BUS_LCD>,
<&ccu CLK_TCON>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_LCD>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,suniv-f1c100s-mmc",
"allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <23>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,suniv-f1c100s-mmc",
"allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <24>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
intc: interrupt-controller@1c20400 {
compatible = "allwinner,suniv-f1c100s-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
pio: pinctrl@1c20800 {
compatible = "allwinner,suniv-f1c100s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <38>, <39>, <40>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
};
spi0_pc_pins: spi0-pc-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
uart0_pe_pins: uart0-pe-pins {
pins = "PE0", "PE1";
function = "uart0";
};
uart1_pa_pins: uart1-pa-pins {
pins = "PA2", "PA3";
function = "uart1";
};
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD6", "PD7", "PD8", "PD9",
"PD10", "PD11", "PD12", "PD13", "PD14",
"PD15", "PD16", "PD17", "PD18", "PD19",
"PD20", "PD21";
function = "lcd";
};
};
timer@1c20c00 {
compatible = "allwinner,suniv-f1c100s-timer";
reg = <0x01c20c00 0x90>;
interrupts = <13>, <14>, <15>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20ca0 {
compatible = "allwinner,suniv-f1c100s-wdt",
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <16>;
clocks = <&osc32k>;
};
uart0: serial@1c25000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c25000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@1c25400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c25400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@1c25800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c25800 0x400>;
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
usb_otg: usb@1c13000 {
compatible = "allwinner,suniv-musb";
reg = <0x01c13000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <26>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
status = "disabled";
};
usbphy: phy@1c13400 {
compatible = "allwinner,suniv-usb-phy";
reg = <0x01c13400 0x10>;
reg-names = "phy_ctrl";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
#phy-cells = <1>;
status = "disabled";
};
fe0: display-frontend@1e00000 {
compatible = "allwinner,suniv-f1c100s-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <30>;
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
<&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
be0: display-backend@1e60000 {
compatible = "allwinner,suniv-f1c100s-display-backend";
reg = <0x01e60000 0x10000>;
reg-names = "be";
interrupts = <31>;
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_BE>;
reset-names = "be";
assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_be0>;
};
};
};
};
};
};
<suniv-f1c100s-licheepip-nano.dts>：
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
*/
/dts-v1/;
#include "suniv-f1c100s.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
aliases {
mmc0 = &mmc0;
serial1 = &uart1;
spi0 = &spi0;
};
chosen {
stdout-path = "serial1:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
status = "okay";
vmmc-supply = <®_vcc3v3>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pc_pins>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pa_pins>;
status = "okay";
};
&otg_sram {
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
status = "okay";
};
<suniv-f1c100s-licheepi-nano-with-lcd.dts>:
/*
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR X11)
*/
#include "suniv-f1c100s-licheepi-nano.dts"
/ {
panel: panel {
compatible = "ampire,am-480272h3tmqw-t01h", "simple-panel";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_lcd>;
};
};
};
};
&be0 {
status = "okay";
};
&de {
status = "okay";
};
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
status = "okay";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
技术狂，追求技术更高层，哈哈哈
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