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F1c100s， RTT工程，AHB APB总线频率的值不同导致USB数据传输出现问题。求助各位大佬！

AHB/APB/HCLKC Configuration Register，我的公司之前程序的nandboot是赋值的12110，我新的RTT工程使用这个值发现程序起来后，USB下载不进去，并且很有意思的是，如果uart2口连接的485模块有120欧终端电阻，或者uart2连接一个485打印口USB也可以识别下载。

我的程序是有两个boot的，大概流程是nandboot 跳到boot1，boot1启动我的app。boot1也是RTT系统。boot1的目的是做一个强制更新app的功能避免卡死只能刷机。
下面是nandboot的sysclock初始化：
void sys_clock_init(int HZ)
{
    u32_t val;

    write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME0, 0x1ff);
    write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME1, 0x1ff);

    val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
    val &= ~(0x3 << 16);
    val |= (0x1 << 16);
    write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
    sdelay(100);

    write32(F1C100S_CCU_BASE + CCU_PLL_VIDEO_CTRL, 0x81004107);
    sdelay(100);
    write32(F1C100S_CCU_BASE + CCU_PLL_PERIPH_CTRL, 0x80041800);
    sdelay(100);
    // write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00003180);//采用原厂MDK提供的分频
    write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00012110);
    sdelay(100);

    val = read32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE);
    val |= (0x1 << 26) | (0x1 << 24);
    write32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE, val);
    sdelay(100);

    clock_set_pll_cpu(HZ);
    val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
    val &= ~(0x3 << 16);
    val |= (0x2 << 16);
    write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
    sdelay(100);//100->200
}
下面是boot1：
void sys_clock_init(void)
{
    uint32_t val;

    write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME0, 0x1ff);
    write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME1, 0x1ff);

    val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
    val &= ~(0x3 << 16);
    val |= (0x1 << 16);
    write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
    sdelay(100);

    // uint32_t boot1ahpval = 0;
    // boot1ahpval = read32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG);
    // rt_kprintf("111CCU_AHB_APB_CFG:%d Hz\r\n",boot1ahpval);

    write32(F1C100S_CCU_BASE + CCU_PLL_VIDEO_CTRL, 0x81004107);
    sdelay(100);
    write32(F1C100S_CCU_BASE + CCU_PLL_PERIPH_CTRL, 0x80041800);
    sdelay(100);
    write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00003180);
    sdelay(100);
    // boot1ahpval = read32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG);
    // rt_kprintf("222CCU_AHB_APB_CFG:%d Hz\r\n",boot1ahpval);
    val = read32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE);
    val |= (0x1 << 26) | (0x1 << 24);
    write32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE, val);
    sdelay(100);

    clock_set_pll_cpu(600000000);
    val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
    val &= ~(0x3 << 16);
    val |= (0x2 << 16);
    write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
    sdelay(100);
}
主要差别就是CCU_AHB_APB_CFG寄存器一个是0x00012110，boot1是0x00003180。如果nandboot也使用3180是能正常下载的。nandboot使用12110需要485模块有终端电阻。是否是更改这些寄存器是需要有一些前提步骤，不能在一次上电中途访问修改？