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楼主 #1 2019-05-24 00:12:19

wuxx
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注册时间： 2018-01-03
已发帖子： 30
积分： 30

写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

之前大概花半个下午写的小工具，类似树莓派的gpio命令。
源码和二进制都在 https://github.com/wuxx/f1c100s-gpio-tools
具体用法和树莓派的gpio命令类似，如下

root@f1c100s:~#gpio
usage: gpio help
       gpio read  [PA0|PA1...]
       gpio write [PA0|PA1...]
       gpio mode  [PA0|PA1...] [in|out|...]
       gpio readall
       gpio dumpall
       gpio info
-- github.com/wuxx/f1c100s-gpio-tools --

root@f1c100s:~#gpio read PA0
PA0: 1

root@f1c100s:~#gpio write PA0 0
root@f1c100s:~#gpio read PA0
PA0: 0
root@f1c100s:~#gpio mode PA0 in

root@f1c100s:~#gpio readall
        value   mode
PA:
PA0:    0       [in]
PA1:    0       [disabled]
PA2:    0       [out]
PA3:    1       [out]
PB:
PB3:    0       [disabled]
PC:
PC0:    0       [spi0_clk]
PC1:    0       [spi0_cs]
PC2:    0       [spi0_miso]
PC3:    0       [spi0_mosi]
PD:
PD0:    0       [lcd_d2]
PD1:    0       [lcd_d3]
PD2:    0       [lcd_d4]
PD3:    0       [lcd_d5]
PD4:    0       [lcd_d6]
PD5:    0       [lcd_d7]
PD6:    0       [lcd_d10]
PD7:    0       [lcd_d11]
PD8:    0       [lcd_d12]
PD9:    0       [lcd_d13]
PD10:   0       [lcd_d14]
PD11:   0       [lcd_d15]
PD12:   0       [lcd_d18]
PD13:   0       [lcd_d19]
PD14:   0       [lcd_d20]
PD15:   0       [lcd_d21]
PD16:   0       [lcd_d22]
PD17:   0       [lcd_d23]
PD18:   0       [lcd_clk]
PD19:   0       [lcd_de]
PD20:   0       [lcd_hsync]
PD21:   0       [lcd_vsync]
PE:
PE0:    0       [uart0_rx]
PE1:    0       [uart0_tx]
PE2:    0       [out]
PE3:    1       [out]
PE4:    1       [out]
PE5:    1       [in]
PE6:    1       [out]
PE7:    0       [disabled]
PE8:    0       [disabled]
PE9:    0       [disabled]
PE10:   1       [out]
PE11:   0       [twi0_sck]
PE12:   0       [twi0_sda]
PF:
PF0:    0       [sdc0_d1]
PF1:    0       [sdc0_d0]
PF2:    0       [sdc0_clk]
PF3:    0       [sdc0_cmd]
PF4:    0       [sdc0_d3]
PF5:    0       [sdc0_d2]

root@f1c100s:~#gpio info
PA0:    (in out tp_x1 reserved da_bclk uart1_rts spi1_cs disabled )
PA1:    (in out tp_x2 reserved da_lrck uart1_cts spi1_miso disabled )
PA2:    (in out tp_y1 pwm0 da_in uart1_rx spi1_clk disabled )
PA3:    (in out tp_y2 ir_rx da_out uart1_tx spi1_miso disabled )
PB3:    (in out ddr_ref_d ir_rx reserved reserved reserved disabled )
PC0:    (reserved out spi0_clk sdc1_clk reserved reserved reserved disabled )
PC1:    (in out spi0_cs sdc1_cmd reserved reserved reserved disabled )
PC2:    (in out spi0_miso sdc1_d0 reserved reserved reserved disabled )
PC3:    (in out spi0_mosi uart0_tx reserved reserved reserved disabled )
PD0:    (in out lcd_d2 twi0_sda rsb_sda reserved eintd0 disabled )
PD1:    (in out lcd_d3 uart1_rts reserved reserved eintd1 disabled )
PD2:    (in out lcd_d4 uart1_cts reserved reserved eintd2 disabled )
PD3:    (in out lcd_d5 uart1_rx reserved reserved eintd3 disabled )
PD4:    (in out lcd_d6 uart1_tx reserved reserved eintd4 disabled )
PD5:    (in out lcd_d7 twi1_sck reserved reserved eintd5 disabled )
PD6:    (in out lcd_d10 twi1_sda reserved reserved eintd6 disabled )
PD7:    (in out lcd_d11 da_mclk reserved reserved eintd7 disabled )
PD8:    (in out lcd_d12 da_bclk reserved reserved eintd8 disabled )
PD9:    (in out lcd_d13 da_lrck reserved reserved eintd9 disabled )
PD10:   (in out lcd_d14 da_in reserved reserved eintd10 disabled )
PD11:   (in out lcd_d15 da_out reserved reserved eintd11 disabled )
PD12:   (in out lcd_d18 twi0_sck rsb_sck reserved eintd12 disabled )
PD13:   (in out lcd_d19 uart2_tx rsb_sck reserved eintd13 disabled )
PD14:   (in out lcd_d20 uart2_rx reserved reserved eintd14 disabled )
PD15:   (in out lcd_d21 uart2_rts twi2_sck reserved eintd15 disabled )
PD16:   (in out lcd_d22 uart2_cts twi2_sda reserved eintd16 disabled )
PD17:   (in out lcd_d23 owa_out reserved reserved eintd17 disabled )
PD18:   (in out lcd_clk spi0_cs reserved reserved eintd18 disabled )
PD19:   (in out lcd_de spi0_mosi reserved reserved eintd19 disabled )
PD20:   (in out lcd_hsync spi0_clk reserved reserved eintd20 disabled )
PD21:   (in out lcd_vsync spi0_miso reserved reserved eintd21 disabled )
PE0:    (in out csi_hsync lcd_d0 twi2_sck uart0_rx einte0 disabled )
PE1:    (in out csi_vsync lcd_d1 twi2_sda uart0_tx einte1 disabled )
PE2:    (in out csi_pclk lcd_d8 clk_out reserved einte2 disabled )
PE3:    (in out csi_d0 lcd_d9 da_bclk rsb_sck einte3 disabled )
PE4:    (in out csi_d1 lcd_d16 da_lrck rsb_sda einte4 disabled )
PE5:    (in out csi_d2 lcd_d17 da_in reserved einte5 disabled )
PE6:    (in out csi_d3 pwm1 da_out owa_out einte6 disabled )
PE7:    (in out csi_d4 uart2_tx spi1_cs reserved einte7 disabled )
PE8:    (in out csi_d5 uart2_rx spi1_mosi reserved einte8 disabled )
PE9:    (in out csi_d6 uart2_rts spi1_clk reserved einte9 disabled )
PE10:   (in out csi_d7 uart2_cts spi1_miso reserved einte10 disabled )
PE11:   (in out clk_out twi0_sck ir_rx reserved einte11 disabled )
PE12:   (in out da_mclk twi0_sda pwm0 reserved einte12 disabled )
PF0:    (in out sdc0_d1 dbg_ms ir_rx reserved eintf0 disabled )
PF1:    (in out sdc0_d0 dbg_di reserved reserved eintf1 disabled )
PF2:    (in out sdc0_clk uart0_tx reserved reserved eintf2 disabled )
PF3:    (in out sdc0_cmd dbg_do reserved reserved eintf3 disabled )
PF4:    (in out sdc0_d3 uart0_tx reserved reserved eintf4 disabled )
PF5:    (in out sdc0_d2 dbg_ck pwm1 reserved eintf5 disabled )

root@f1c100s:~#gpio dumpall
PA:
GPIO_CFG0: 0x00001170
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000008
GPIO_DRV0: 0x00000055
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PB:
GPIO_CFG0: 0x00007222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000055
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PC:
GPIO_CFG0: 0x00002222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000000
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PD:
GPIO_CFG0: 0x22222222
GPIO_CFG1: 0x22222222
GPIO_CFG2: 0x00222222
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x55555555
GPIO_DRV1: 0x00000555
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PE:
GPIO_CFG0: 0x71011155
GPIO_CFG1: 0x00033177
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000478
GPIO_DRV0: 0x01555555
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000004
GPIO_PUL1: 0x00000000
PF:
GPIO_CFG0: 0x00222222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000aaa
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000555
GPIO_PUL1: 0x00000000

最近编辑记录 wuxx (2019-05-24 00:15:56)

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#2 2019-05-24 06:28:14

Lvy
会员
注册时间： 2017-11-25
已发帖子： 107
积分： 96.5

Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

这个好。支持支持！！:)

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#3 2019-05-24 08:21:35

晕哥
管理员
注册时间： 2017-09-06
已发帖子： 9,342
积分： 9202

Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

相当不错， 感谢分享！


#include <stdio.h>
#include <stdlib.h>
#include <string.h>

/* author: wuxx */

enum GPIO_GROUP_E {
    PA = 0,
    PB = 1,
    PC = 2,
    PD = 3,
    PE = 4,
    PF = 5,
};

enum GPIO_MODE_E {
    IN = 0,
    OUT = 1,
};

#define GPIO_BASE   (0x01C20800)

#define GPIO_CFG0(n) (GPIO_BASE + ((n) * 0x24) + 0x0)
#define GPIO_CFG1(n) (GPIO_BASE + ((n) * 0x24) + 0x4)
#define GPIO_CFG2(n) (GPIO_BASE + ((n) * 0x24) + 0x8)
#define GPIO_CFG3(n) (GPIO_BASE + ((n) * 0x24) + 0xC)
#define GPIO_DATA(n) (GPIO_BASE + ((n) * 0x24) + 0x10)
#define GPIO_DRV0(n) (GPIO_BASE + ((n) * 0x24) + 0x14)
#define GPIO_DRV1(n) (GPIO_BASE + ((n) * 0x24) + 0x18)
#define GPIO_PUL0(n) (GPIO_BASE + ((n) * 0x24) + 0x1C)
#define GPIO_PUL1(n) (GPIO_BASE + ((n) * 0x24) + 0x20)

#define MAKE_PID(group, index) (#group#index), ((group) << 5 | index)

#define get_bit(x, index)       (((x) >> index) & 0x1)


typedef unsigned char u8;
typedef   signed char s8;
typedef unsigned short u16;
typedef   signed short s16;
typedef unsigned int u32;
typedef   signed int s32;

/* pio */
/* |     |         */
/* 7 6 5 4 3 2 1 0 */
struct gpio_info {
    char name[16];  /* PA, PB, PC, PD, PE, PF */
    u8 pio;
    u32 cfg_addr;
    u32 cfg_off;
    u32 mode; /* 3 bit */
    char mode_desc[32];
};

/* 6 * 32 * 8 (PA-PF = 6, io0-io32,  8 mode) */
u32 gindex = 0;
struct gpio_info gi[2048];

/* ADD(PA, offset, mode, mode_desc)*/

void set_bit(unsigned int *x, unsigned int bit_index, unsigned int b)
{
    unsigned int _x;
    unsigned int bit_mask;
    _x = *x;
    if (get_bit(_x, bit_index) != b) {
        if (b == 0) {
            bit_mask = ~(0x1 << bit_index);
            *x = (_x) & bit_mask;
        } else {    /* b == 1 */
            bit_mask = (0x1 << bit_index);
            *x = (_x) | bit_mask;
        }
    }
}


u32 writel(u32 addr, u32 data)
{
    FILE *fp;
    u32 value = 0;
    char cmd[1024];

    snprintf(cmd, sizeof(cmd), "devmem 0x%08x 32 0x%08x", addr, data);

    fp = popen(cmd, "r");

    if (fp == NULL) {
        fprintf(stderr, "%s: popen(%s) fail!\n", __func__, cmd);
        goto err;
    }

err:
    pclose(fp);
    return value;

}

u32 readl(u32 addr)
{
    FILE *fp;
    u32 value = 0;
    char cmd[1024];
    char buf[32];

    snprintf(cmd, sizeof(cmd), "devmem 0x%08x", addr);

    fp = popen(cmd, "r");
    if (fp == NULL) {
        fprintf(stderr, "%s: popen(%s) fail!\n", __func__, cmd);
    }

    fread(buf, sizeof(char), sizeof(buf), fp);
    sscanf(buf, "0x%x", &value);

err:
    pclose(fp);
    return value;
}

struct gpio_info * gi_get(char *name, char *mode)
{
    u32 i;
    for(i = 0; i < gindex; i++) {
        if ((strcmp(gi[i].name, name) == 0)) {
            if (mode == NULL) {
                return &(gi[i]);
            } else {
                if (strcmp(gi[i].mode_desc, mode) == 0) {
                    return &(gi[i]);
                }
            }
        }
    }
    return NULL;
}
char * gi_get_mode_desc(u8 pio, u32 mode)
{
    u32 i;
    for(i = 0; i < gindex; i++) {
        if (gi[i].pio == pio && gi[i].mode == mode) {
            return gi[i].mode_desc;
        }
    }

    fprintf(stdout, "%s(0x%x, 0x%x) fail\n", __func__, pio, mode);
    return NULL;
}

void gi_add(char *name, u8 pio, u32 cfg_addr, u32 offset, u32 mode, char *mode_desc)
{
    if (gindex >= (sizeof(gi) / sizeof(gi[0]))) {
        fprintf(stderr, "gindex overflow!\n");
        exit(-1);
    }

    strncpy(gi[gindex].name, name, sizeof(gi[gindex].name));
    gi[gindex].pio = pio;
    gi[gindex].cfg_addr = cfg_addr;
    gi[gindex].cfg_off  = offset;
    gi[gindex].mode = mode;
    strncpy(gi[gindex].mode_desc, mode_desc, sizeof(gi[gindex].mode_desc));

    gindex++;
}

void gi_init()
{
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 0, "in");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 1, "out");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 2, "tp_x1");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 3, "reserved");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 4, "da_bclk");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 5, "uart1_rts");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 6, "spi1_cs");
    gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 0, "in");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 1, "out");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 2, "tp_x2");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 3, "reserved");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 4, "da_lrck");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 5, "uart1_cts");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 6, "spi1_miso");
    gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 0, "in");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 1, "out");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 2, "tp_y1");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 3, "pwm0");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 4, "da_in");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 5, "uart1_rx");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 6, "spi1_clk");
    gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 0, "in");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 1, "out");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 2, "tp_y2");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 3, "ir_rx");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 4, "da_out");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 5, "uart1_tx");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 6, "spi1_miso");
    gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 7, "disabled");


    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 0, "in");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 1, "out");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 2, "ddr_ref_d");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 3, "ir_rx");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 6, "reserved");
    gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 0, "reserved");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 1, "out");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 2, "spi0_clk");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 3, "sdc1_clk");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 4, "reserved");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 6, "reserved");
    gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 0, "in");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 1, "out");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 2, "spi0_cs");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 3, "sdc1_cmd");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 4, "reserved");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 6, "reserved");
    gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 0, "in");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 1, "out");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 2, "spi0_miso");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 3, "sdc1_d0");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 4, "reserved");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 6, "reserved");
    gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 0, "in");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 1, "out");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 2, "spi0_mosi");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 3, "uart0_tx");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 6, "reserved");
    gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 0, "in");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 1, "out");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 2, "lcd_d2");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 3, "twi0_sda");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 4, "rsb_sda");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 6, "eintd0");
    gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 0, "in");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 1, "out");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 2, "lcd_d3");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 3, "uart1_rts");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 4, "reserved");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 6, "eintd1");
    gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 0, "in");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 1, "out");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 2, "lcd_d4");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 3, "uart1_cts");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 4, "reserved");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 6, "eintd2");
    gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 0, "in");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 1, "out");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 2, "lcd_d5");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 3, "uart1_rx");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 6, "eintd3");
    gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 0, "in");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 1, "out");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 2, "lcd_d6");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 3, "uart1_tx");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 4, "reserved");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 5, "reserved");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 6, "eintd4");
    gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 0, "in");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 1, "out");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 2, "lcd_d7");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 3, "twi1_sck");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 4, "reserved");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 5, "reserved");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 6, "eintd5");
    gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 7, "disabled");

    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 0, "in");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 1, "out");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 2, "lcd_d10");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 3, "twi1_sda");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 4, "reserved");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 5, "reserved");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 6, "eintd6");
    gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 7, "disabled");

    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 0, "in");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 1, "out");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 2, "lcd_d11");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 3, "da_mclk");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 4, "reserved");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 5, "reserved");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 6, "eintd7");
    gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 7, "disabled");

    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 0, "in");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 1, "out");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 2, "lcd_d12");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 3, "da_bclk");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 4, "reserved");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 6, "eintd8");
    gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 0, "in");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 1, "out");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 2, "lcd_d13");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 3, "da_lrck");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 4, "reserved");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 6, "eintd9");
    gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 0, "in");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 1, "out");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 2, "lcd_d14");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 3, "da_in");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 4, "reserved");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 6, "eintd10");
    gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 0, "in");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 1, "out");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 2, "lcd_d15");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 3, "da_out");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 6, "eintd11");
    gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 0, "in");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 1, "out");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 2, "lcd_d18");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 3, "twi0_sck");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 4, "rsb_sck");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 5, "reserved");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 6, "eintd12");
    gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 0, "in");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 1, "out");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 2, "lcd_d19");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 3, "uart2_tx");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 4, "rsb_sck");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 5, "reserved");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 6, "eintd13");
    gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 7, "disabled");

    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 0, "in");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 1, "out");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 2, "lcd_d20");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 3, "uart2_rx");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 4, "reserved");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 5, "reserved");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 6, "eintd14");
    gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 7, "disabled");

    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 0, "in");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 1, "out");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 2, "lcd_d21");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 3, "uart2_rts");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 4, "twi2_sck");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 5, "reserved");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 6, "eintd15");
    gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 7, "disabled");

    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 0, "in");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 1, "out");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 2, "lcd_d22");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 3, "uart2_cts");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 4, "twi2_sda");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 6, "eintd16");
    gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 0, "in");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 1, "out");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 2, "lcd_d23");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 3, "owa_out");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 4, "reserved");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 6, "eintd17");
    gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 0, "in");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 1, "out");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 2, "lcd_clk");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 3, "spi0_cs");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 4, "reserved");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 6, "eintd18");
    gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 0, "in");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 1, "out");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 2, "lcd_de");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 3, "spi0_mosi");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 6, "eintd19");
    gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 0, "in");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 1, "out");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 2, "lcd_hsync");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 3, "spi0_clk");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 4, "reserved");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 5, "reserved");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 6, "eintd20");
    gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 0, "in");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 1, "out");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 2, "lcd_vsync");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 3, "spi0_miso");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 4, "reserved");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 5, "reserved");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 6, "eintd21");
    gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 7, "disabled");

    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 0, "in");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 1, "out");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 2, "csi_hsync");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 3, "lcd_d0");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 4, "twi2_sck");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 5, "uart0_rx");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 6, "einte0");
    gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 0, "in");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 1, "out");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 2, "csi_vsync");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 3, "lcd_d1");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 4, "twi2_sda");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 5, "uart0_tx");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 6, "einte1");
    gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 0, "in");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 1, "out");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 2, "csi_pclk");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 3, "lcd_d8");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 4, "clk_out");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 6, "einte2");
    gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 0, "in");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 1, "out");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 2, "csi_d0");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 3, "lcd_d9");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 4, "da_bclk");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 5, "rsb_sck");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 6, "einte3");
    gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 0, "in");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 1, "out");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 2, "csi_d1");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 3, "lcd_d16");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 4, "da_lrck");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 5, "rsb_sda");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 6, "einte4");
    gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 0, "in");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 1, "out");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 2, "csi_d2");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 3, "lcd_d17");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 4, "da_in");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 5, "reserved");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 6, "einte5");
    gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 7, "disabled");

    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 0, "in");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 1, "out");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 2, "csi_d3");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 3, "pwm1");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 4, "da_out");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 5, "owa_out");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 6, "einte6");
    gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 7, "disabled");

    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 0, "in");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 1, "out");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 2, "csi_d4");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 3, "uart2_tx");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 4, "spi1_cs");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 5, "reserved");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 6, "einte7");
    gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 7, "disabled");

    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 0, "in");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 1, "out");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 2, "csi_d5");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 3, "uart2_rx");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 4, "spi1_mosi");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 6, "einte8");
    gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 0, "in");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 1, "out");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 2, "csi_d6");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 3, "uart2_rts");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 4, "spi1_clk");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 6, "einte9");
    gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 0, "in");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 1, "out");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 2, "csi_d7");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 3, "uart2_cts");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 4, "spi1_miso");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 6, "einte10");
    gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 0, "in");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 1, "out");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 2, "clk_out");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 3, "twi0_sck");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 4, "ir_rx");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 6, "einte11");
    gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 0, "in");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 1, "out");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 2, "da_mclk");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 3, "twi0_sda");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 4, "pwm0");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 5, "reserved");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 6, "einte12");
    gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 0, "in");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 1, "out");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 2, "sdc0_d1");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 3, "dbg_ms");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 4, "ir_rx");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 5, "reserved");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 6, "eintf0");
    gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 7, "disabled");

    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 0, "in");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 1, "out");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 2, "sdc0_d0");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 3, "dbg_di");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 4, "reserved");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 5, "reserved");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 6, "eintf1");
    gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 7, "disabled");

    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 0, "in");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 1, "out");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 2, "sdc0_clk");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 3, "uart0_tx");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 4, "reserved");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 5, "reserved");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 6, "eintf2");
    gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 7, "disabled");

    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 0, "in");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 1, "out");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 2, "sdc0_cmd");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 3, "dbg_do");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 4, "reserved");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 5, "reserved");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 6, "eintf3");
    gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 7, "disabled");

    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 0, "in");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 1, "out");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 2, "sdc0_d3");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 3, "uart0_tx");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 4, "reserved");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 5, "reserved");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 6, "eintf4");
    gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 7, "disabled");

    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 0, "in");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 1, "out");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 2, "sdc0_d2");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 3, "dbg_ck");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 4, "pwm1");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 5, "reserved");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 6, "eintf5");
    gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 7, "disabled");
}

void usage(char *program_name)
{
    fprintf(stdout, "usage: %s help \n", program_name);
    fprintf(stdout, "       %s read  [PA0|PA1...] \n", program_name);
    fprintf(stdout, "       %s write [PA0|PA1...] \n", program_name);
    fprintf(stdout, "       %s mode  [PA0|PA1...] [in|out|...]\n", program_name);
    fprintf(stdout, "       %s readall\n", program_name);
    fprintf(stdout, "       %s dumpall\n", program_name);
    fprintf(stdout, "       %s info\n", program_name);
    fprintf(stdout, "-- github.com/wuxx/f1c100s-gpio-tools --\n");
    exit(0);
}

void dump_gpio_info()
{
    u32 i;
    u32 group, index;
    u32 cfg_value, cfg_mask;
    u32 dvalue;
    u32 current_group = PA;
    u32 current_index = 0;
    u32 mode = 0;
    u32 b = 0;

    fprintf(stdout, "\tvalue\tmode\n");
    fprintf(stdout, "PA:\n");

    for(i = 0; i < gindex; i = i + 8) {

        group = gi[i].pio >> 5;
        index = gi[i].pio & 0x1f;

        if (group != current_group) {
            fprintf(stdout, "P%c:\n", 'A' + group);
            current_group = group;
        }

        fprintf(stdout, "P%c%d:", 'A' + group, index);

        cfg_value = readl(gi[i].cfg_addr);
        mode = (cfg_value >> gi[i].cfg_off) & 0x7;

        dvalue = readl(GPIO_DATA(group));
        b = get_bit(dvalue, index);

        fprintf(stdout, "\t%d\t[%s]\n", b, gi_get_mode_desc(gi[i].pio, mode));
    }

}

void dump_gpio_mode()
{
    u32 i, x;
    u32 group, index;

    for(i = 0; i < gindex; i = i + 8) {
        group = gi[i].pio >> 5;
        index = gi[i].pio & 0x1f;

        fprintf(stdout, "P%c%d:\t(", 'A' + group, index);

        for(x = 0; x < 8; x++) {
            fprintf(stdout, "%s ", gi[i + x].mode_desc);
        }

        fprintf(stdout, ")\n");
    }
}

void dump_reg(u32 pio)
{
    fprintf(stdout, "GPIO_CFG0: 0x%08x\n", readl(GPIO_CFG0(pio)));
    fprintf(stdout, "GPIO_CFG1: 0x%08x\n", readl(GPIO_CFG1(pio)));
    fprintf(stdout, "GPIO_CFG2: 0x%08x\n", readl(GPIO_CFG2(pio)));
    fprintf(stdout, "GPIO_CFG3: 0x%08x\n", readl(GPIO_CFG3(pio)));
    fprintf(stdout, "GPIO_DATA: 0x%08x\n", readl(GPIO_DATA(pio)));
    fprintf(stdout, "GPIO_DRV0: 0x%08x\n", readl(GPIO_DRV0(pio)));
    fprintf(stdout, "GPIO_DRV1: 0x%08x\n", readl(GPIO_DRV1(pio)));
    fprintf(stdout, "GPIO_PUL0: 0x%08x\n", readl(GPIO_PUL0(pio)));
    fprintf(stdout, "GPIO_PUL1: 0x%08x\n", readl(GPIO_PUL1(pio)));
}

void dump_gpio_reg()
{
    fprintf(stdout, "PA:\n");
    dump_reg(PA);

    fprintf(stdout, "PB:\n");
    dump_reg(PB);

    fprintf(stdout, "PC:\n");
    dump_reg(PC);

    fprintf(stdout, "PD:\n");
    dump_reg(PD);

    fprintf(stdout, "PE:\n");
    dump_reg(PE);

    fprintf(stdout, "PF:\n");
    dump_reg(PF);
}


int main(int argc, char **argv)
{
    u32 group, index;
    u32 cfg_value, cfg_mask;
    u32 dvalue, b;
    char *m;

    struct gpio_info *pgi;

   	if (argc == 1) {
        usage(argv[0]);
	}

    gi_init();

    if (strcmp("read", argv[1]) == 0) {
        /* e.g. gpio read PA0 */
        if(argc != 3) {
            fprintf(stderr, "%s read pio, e.g. %s read PA0\n", argv[0], argv[0]);
            exit(-1);
        }
        pgi = gi_get(argv[2], NULL);

        if (pgi == NULL) {
            fprintf(stderr, "gi_get(%s) fail!\n", argv[2]);
            exit(-1);
        }

        group = pgi->pio >> 5;      /* high 3 bit */
        index = pgi->pio & 0x1f;    /* low 5 bit */
        dvalue = readl(GPIO_DATA(group));
        fprintf(stdout, "%s: %d\n", argv[2], get_bit(dvalue, index));

    } else if (strcmp("write", argv[1]) == 0) {
        /* e.g. gpio write PA0 1 */
        if (argc != 4) {
            fprintf(stderr, "%s write pio [0|1], e.g. %s write PA 1\n", argv[0], argv[0]);
            exit(-1);
        }

        pgi = gi_get(argv[2], NULL);
		b   = atoi(argv[3]);

        if (pgi == NULL) {
            fprintf(stderr, "gi_get(%s) fail!\n", argv[2]);
            exit(-1);
        }

        group = pgi->pio >> 5;      /* high 3 bit */
        index = pgi->pio & 0x1f;    /* low 5 bit */
            
        cfg_value = readl(pgi->cfg_addr);
        cfg_mask  = 0x7 << pgi->cfg_off;
        cfg_value = cfg_value & (~cfg_mask);
        cfg_value = cfg_value | OUT << pgi->cfg_off;
        writel(pgi->cfg_addr, cfg_value);

        dvalue = readl(GPIO_DATA(group));
        set_bit(&dvalue, index, b);
		writel(GPIO_DATA(group), dvalue);
    } else if (strcmp("mode", argv[1]) == 0) {
        /* e.g. gpio mode PA0 in|out|... */
        if (argc != 4) {
            fprintf(stderr, "%s mode pio [in|out|...], e.g. %s mode PA in\n", argv[0], argv[0]);
            exit(-1);
        }

		m   = argv[3];
        pgi = gi_get(argv[2], m);

        if (pgi == NULL) {
            fprintf(stderr, "gi_get(%s, %s) fail!\n", argv[2], m);
            exit(-1);
        }

        group = pgi->pio >> 5;      /* high 3 bit */
        index = pgi->pio & 0x1f;    /* low 5 bit */

        cfg_value = readl(pgi->cfg_addr);
        cfg_mask  = 0x7 << pgi->cfg_off;
        cfg_value = cfg_value & (~cfg_mask);
        cfg_value = cfg_value | pgi->mode << pgi->cfg_off;
        writel(pgi->cfg_addr, cfg_value);

    } else if (strcmp("readall", argv[1]) == 0) {
        dump_gpio_info();

    } else if (strcmp("dumpall", argv[1]) == 0) {
        dump_gpio_reg();
    } else if (strcmp("info", argv[1]) == 0) {
        dump_gpio_mode();
    } else {
        fprintf(stderr, "unknown cmd [%s]\n", argv[1]);
        usage(argv[0]);
    }


    return 0;
}




taobao： V3s/F1C100s/F1C200s/D1-H/D1s/T113-S3/XR32/XR829/A523/A133/H133/V831/V851s/V853

在线

#4 2019-05-24 08:45:01

Jmhh247
会员
注册时间： 2018-12-21
已发帖子： 262
积分： 262

Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

不错  感谢分享

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#5 2019-05-24 12:49:40

kekemuyu
会员
注册时间： 2018-12-13
已发帖子： 849
积分： 720

Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

wuxx 说：

之前大概花半个下午写的小工具，类似树莓派的gpio命令。
源码和二进制都在 https://github.com/wuxx/f1c100s-gpio-tools
具体用法和树莓派的gpio命令类似，如下

root@f1c100s:~#gpio
usage: gpio help
       gpio read  [PA0|PA1...]
       gpio write [PA0|PA1...]
       gpio mode  [PA0|PA1...] [in|out|...]
       gpio readall
       gpio dumpall
       gpio info
-- github.com/wuxx/f1c100s-gpio-tools --

root@f1c100s:~#gpio read PA0
PA0: 1

root@f1c100s:~#gpio write PA0 0
root@f1c100s:~#gpio read PA0
PA0: 0
root@f1c100s:~#gpio mode PA0 in

root@f1c100s:~#gpio readall
        value   mode
PA:
PA0:    0       [in]
PA1:    0       [disabled]
PA2:    0       [out]
PA3:    1       [out]
PB:
PB3:    0       [disabled]
PC:
PC0:    0       [spi0_clk]
PC1:    0       [spi0_cs]
PC2:    0       [spi0_miso]
PC3:    0       [spi0_mosi]
PD:
PD0:    0       [lcd_d2]
PD1:    0       [lcd_d3]
PD2:    0       [lcd_d4]
PD3:    0       [lcd_d5]
PD4:    0       [lcd_d6]
PD5:    0       [lcd_d7]
PD6:    0       [lcd_d10]
PD7:    0       [lcd_d11]
PD8:    0       [lcd_d12]
PD9:    0       [lcd_d13]
PD10:   0       [lcd_d14]
PD11:   0       [lcd_d15]
PD12:   0       [lcd_d18]
PD13:   0       [lcd_d19]
PD14:   0       [lcd_d20]
PD15:   0       [lcd_d21]
PD16:   0       [lcd_d22]
PD17:   0       [lcd_d23]
PD18:   0       [lcd_clk]
PD19:   0       [lcd_de]
PD20:   0       [lcd_hsync]
PD21:   0       [lcd_vsync]
PE:
PE0:    0       [uart0_rx]
PE1:    0       [uart0_tx]
PE2:    0       [out]
PE3:    1       [out]
PE4:    1       [out]
PE5:    1       [in]
PE6:    1       [out]
PE7:    0       [disabled]
PE8:    0       [disabled]
PE9:    0       [disabled]
PE10:   1       [out]
PE11:   0       [twi0_sck]
PE12:   0       [twi0_sda]
PF:
PF0:    0       [sdc0_d1]
PF1:    0       [sdc0_d0]
PF2:    0       [sdc0_clk]
PF3:    0       [sdc0_cmd]
PF4:    0       [sdc0_d3]
PF5:    0       [sdc0_d2]

root@f1c100s:~#gpio info
PA0:    (in out tp_x1 reserved da_bclk uart1_rts spi1_cs disabled )
PA1:    (in out tp_x2 reserved da_lrck uart1_cts spi1_miso disabled )
PA2:    (in out tp_y1 pwm0 da_in uart1_rx spi1_clk disabled )
PA3:    (in out tp_y2 ir_rx da_out uart1_tx spi1_miso disabled )
PB3:    (in out ddr_ref_d ir_rx reserved reserved reserved disabled )
PC0:    (reserved out spi0_clk sdc1_clk reserved reserved reserved disabled )
PC1:    (in out spi0_cs sdc1_cmd reserved reserved reserved disabled )
PC2:    (in out spi0_miso sdc1_d0 reserved reserved reserved disabled )
PC3:    (in out spi0_mosi uart0_tx reserved reserved reserved disabled )
PD0:    (in out lcd_d2 twi0_sda rsb_sda reserved eintd0 disabled )
PD1:    (in out lcd_d3 uart1_rts reserved reserved eintd1 disabled )
PD2:    (in out lcd_d4 uart1_cts reserved reserved eintd2 disabled )
PD3:    (in out lcd_d5 uart1_rx reserved reserved eintd3 disabled )
PD4:    (in out lcd_d6 uart1_tx reserved reserved eintd4 disabled )
PD5:    (in out lcd_d7 twi1_sck reserved reserved eintd5 disabled )
PD6:    (in out lcd_d10 twi1_sda reserved reserved eintd6 disabled )
PD7:    (in out lcd_d11 da_mclk reserved reserved eintd7 disabled )
PD8:    (in out lcd_d12 da_bclk reserved reserved eintd8 disabled )
PD9:    (in out lcd_d13 da_lrck reserved reserved eintd9 disabled )
PD10:   (in out lcd_d14 da_in reserved reserved eintd10 disabled )
PD11:   (in out lcd_d15 da_out reserved reserved eintd11 disabled )
PD12:   (in out lcd_d18 twi0_sck rsb_sck reserved eintd12 disabled )
PD13:   (in out lcd_d19 uart2_tx rsb_sck reserved eintd13 disabled )
PD14:   (in out lcd_d20 uart2_rx reserved reserved eintd14 disabled )
PD15:   (in out lcd_d21 uart2_rts twi2_sck reserved eintd15 disabled )
PD16:   (in out lcd_d22 uart2_cts twi2_sda reserved eintd16 disabled )
PD17:   (in out lcd_d23 owa_out reserved reserved eintd17 disabled )
PD18:   (in out lcd_clk spi0_cs reserved reserved eintd18 disabled )
PD19:   (in out lcd_de spi0_mosi reserved reserved eintd19 disabled )
PD20:   (in out lcd_hsync spi0_clk reserved reserved eintd20 disabled )
PD21:   (in out lcd_vsync spi0_miso reserved reserved eintd21 disabled )
PE0:    (in out csi_hsync lcd_d0 twi2_sck uart0_rx einte0 disabled )
PE1:    (in out csi_vsync lcd_d1 twi2_sda uart0_tx einte1 disabled )
PE2:    (in out csi_pclk lcd_d8 clk_out reserved einte2 disabled )
PE3:    (in out csi_d0 lcd_d9 da_bclk rsb_sck einte3 disabled )
PE4:    (in out csi_d1 lcd_d16 da_lrck rsb_sda einte4 disabled )
PE5:    (in out csi_d2 lcd_d17 da_in reserved einte5 disabled )
PE6:    (in out csi_d3 pwm1 da_out owa_out einte6 disabled )
PE7:    (in out csi_d4 uart2_tx spi1_cs reserved einte7 disabled )
PE8:    (in out csi_d5 uart2_rx spi1_mosi reserved einte8 disabled )
PE9:    (in out csi_d6 uart2_rts spi1_clk reserved einte9 disabled )
PE10:   (in out csi_d7 uart2_cts spi1_miso reserved einte10 disabled )
PE11:   (in out clk_out twi0_sck ir_rx reserved einte11 disabled )
PE12:   (in out da_mclk twi0_sda pwm0 reserved einte12 disabled )
PF0:    (in out sdc0_d1 dbg_ms ir_rx reserved eintf0 disabled )
PF1:    (in out sdc0_d0 dbg_di reserved reserved eintf1 disabled )
PF2:    (in out sdc0_clk uart0_tx reserved reserved eintf2 disabled )
PF3:    (in out sdc0_cmd dbg_do reserved reserved eintf3 disabled )
PF4:    (in out sdc0_d3 uart0_tx reserved reserved eintf4 disabled )
PF5:    (in out sdc0_d2 dbg_ck pwm1 reserved eintf5 disabled )

root@f1c100s:~#gpio dumpall
PA:
GPIO_CFG0: 0x00001170
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000008
GPIO_DRV0: 0x00000055
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PB:
GPIO_CFG0: 0x00007222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000055
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PC:
GPIO_CFG0: 0x00002222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000000
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PD:
GPIO_CFG0: 0x22222222
GPIO_CFG1: 0x22222222
GPIO_CFG2: 0x00222222
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x55555555
GPIO_DRV1: 0x00000555
GPIO_PUL0: 0x00000000
GPIO_PUL1: 0x00000000
PE:
GPIO_CFG0: 0x71011155
GPIO_CFG1: 0x00033177
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000478
GPIO_DRV0: 0x01555555
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000004
GPIO_PUL1: 0x00000000
PF:
GPIO_CFG0: 0x00222222
GPIO_CFG1: 0x00000000
GPIO_CFG2: 0x00000000
GPIO_CFG3: 0x00000000
GPIO_DATA: 0x00000000
GPIO_DRV0: 0x00000aaa
GPIO_DRV1: 0x00000000
GPIO_PUL0: 0x00000555
GPIO_PUL1: 0x00000000

感谢分享，很有用。大神能不能打包一个f1c100s的带所有常用外设驱动的spi-flash镜像,我等小白刚买的licheepi开发板官方镜像外设只有gpio能用，编译内核对于新手太复杂了，得慢慢学，有个可用的镜像就好了

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#6 2020-05-22 09:18:12

pajoke
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

竟然有如此神器，多谢楼主！

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#7 2020-05-22 09:29:18

小熊猫
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

赞赞

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#8 2020-07-24 12:42:06

lignin
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

我也才开始学，看的b站的视频，还有荔枝派zero的文档学，向大佬学习

kekemuyu 说：

感谢分享，很有用。大神能不能打包一个f1c100s的带所有常用外设驱动的spi-flash镜像,我等小白刚买的licheepi开发板官方镜像外设只有gpio能用，编译内核对于新手太复杂了，得慢慢学，有个可用的镜像就好了

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#9 2020-07-25 10:22:03

飞觞醉月
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

感谢楼主，看起来挺有用的，源码和二进制文件一块给了，方便许多

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#10 2020-07-25 20:16:47

大海88
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

调试方便多了， 收下备用

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#11 2020-08-12 16:23:55

jkl
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

有这个就比较方便了，非常感谢，收下了

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#12 2021-06-07 00:07:26

microxp
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

居然还有这么好的东西，感谢分享

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#13 2021-06-07 15:39:45

microxp
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注册时间： 2021-04-27
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

这玩意有没有v3s版本的

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#15 2023-04-28 23:07:51

姚juiyu
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

F1C200S不太适配，会出现sh: 1: devmem: not found的错误

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#17 2023-05-10 00:10:06

CHSHIQING
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注册时间： 2020-11-27
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

F1C200s还能用么，Linux5.4的内核

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#18 2023-08-04 17:51:06

wuxing0911
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

大佬，具体怎么用啊？怎么给添加到板子上呢？小白一个

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#20 2023-08-11 10:42:02

willX
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Re: 写了一个f1c100s gpio工具，方便命令行操作gpio，开源分享

看代码是用devmem实现的，这种方法如果能带一个config参数表，就能适配到别的Soc上了，现在看只能f1c100s/f1c200s用。

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