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//	3.4.2.4 CPU0 Hotplug Process
//
//	The Hotplug Flag Register is 0x070005C0.
//	The Soft Entry Address Register is 0x070005C4.

//	3.4.2.3 NON_CPU0 Boot Process
//
//	The Soft Entry Address Register of CPU0 is 0x070005C4
//	The Soft Entry Address Register of CPU1 is 0x070005C8

#define HARDWARE_HOTPLUG_FLAG 0xFA50392F	// CPU Hotplug Flag value

// In Allwinner h133 this i/o block named R_CPUCFG

//#define HARDWARE_NCORES 2

static void aarch32_mp_cpuN_start(uintptr_t startfunc, unsigned targetcore)
{
	const uint32_t CORE_RESET_MASK = UINT32_C(1) << targetcore;	// CPUx_CORE_RESET
	volatile uint32_t * const rvaddr = ((volatile uint32_t *) (R_CPUCFG_BASE + 0x1c4 + targetcore * 4));
	ASSERT(startfunc != 0);
	ASSERT(targetcore != 0);

	C0_CPUX_CFG->C0_RST_CTRL &= ~ CORE_RESET_MASK;
	* rvaddr = startfunc;
	ASSERT(* rvaddr == startfunc);
	dcache_clean_all();	// startup code should be copied in to sysram for example.
	C0_CPUX_CFG->C0_RST_CTRL |= CORE_RESET_MASK;
}

void sunxi_usart_init(sunxi_usart_t *usart)
{
  uint32_t addr;
  uint32_t val;

  /* Config usart TXD and RXD pins */
  sunxi_gpio_init(usart->gpio_tx.pin, usart->gpio_tx.mux);
  sunxi_gpio_init(usart->gpio_rx.pin, usart->gpio_rx.mux);

  /* Open the clock gate for usart */
  addr = T113_CCU_BASE + CCU_USART_BGR_REG;
  val	 = read32(addr);
  val |= 1 << usart->id;
  write32(addr, val);

  /* Deassert USART reset */
  addr = T113_CCU_BASE + CCU_USART_BGR_REG;
  val	 = read32(addr);
  val |= 1 << (16 + usart->id);
  write32(addr, val);

  /* Config USART to 115200-8-1-0 */
  addr = usart->base;
  write32(addr + 0x04, 0x0);
  write32(addr + 0x08, 0xf7);
  write32(addr + 0x10, 0x0);
  val = read32(addr + 0x0c);
  val |= (1 << 7);
  write32(addr + 0x0c, val);
  write32(addr + 0x00, 0xd & 0xff);
  write32(addr + 0x04, (0xd >> 8) & 0xff);
  val = read32(addr + 0x0c);
  val &= ~(1 << 7);
  write32(addr + 0x0c, val);
  val = read32(addr + 0x0c);
  val &= ~0x1f;
  val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
  write32(addr + 0x0c, val);
}