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C:\msys64\mingw64\bin>openocd.exe -f t113s3-mangguo.cfg -f t113s3.cfg -d -s E:\资料\T113S3\
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
User : 3 3 options.c:52 configuration_output_handler(): debug_level: 3
User : 4 5 options.c:52 configuration_output_handler():
Debug: 5 7 configuration.c:33 add_script_search_dir(): adding E:\资料\T113S3\
Debug: 6 9 options.c:233 add_default_dirs(): bindir=D:/a/msys64/mingw64/bin
Debug: 7 11 options.c:234 add_default_dirs(): pkgdatadir=D:/a/msys64/mingw64/share/openocd
Debug: 8 13 options.c:235 add_default_dirs(): exepath=C:/msys64/mingw64/bin
Debug: 9 15 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 10 17 configuration.c:33 add_script_search_dir(): adding C:/Users/17204/AppData/Roaming/OpenOCD
Debug: 11 19 configuration.c:33 add_script_search_dir(): adding C:/msys64/mingw64/bin/../share/openocd/site
Debug: 12 24 configuration.c:33 add_script_search_dir(): adding C:/msys64/mingw64/bin/../share/openocd/scripts
Debug: 13 26 command.c:155 script_debug(): command - ocd_find t113s3-mangguo.cfg
Debug: 14 28 configuration.c:88 find_file(): found E:\资料\T113S3\/t113s3-mangguo.cfg
Debug: 15 31 command.c:155 script_debug(): command - ocd_find interface/jlink.cfg
Debug: 16 33 configuration.c:88 find_file(): found C:/msys64/mingw64/bin/../share/openocd/scripts/interface/jlink.cfg
Debug: 17 36 command.c:155 script_debug(): command - adapter driver jlink
Debug: 18 39 command.c:155 script_debug(): command - adapter speed 1000
Debug: 19 41 adapter.c:251 adapter_config_khz(): handle adapter khz
Debug: 20 42 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 21 45 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 22 47 command.c:155 script_debug(): command - transport select jtag
User : 23 49 options.c:52 configuration_output_handler(): jtagUser : 24 50 options.c:52 configuration_output_handler():
Debug: 25 51 command.c:155 script_debug(): command - ocd_find t113s3.cfg
Debug: 26 55 configuration.c:88 find_file(): found E:\资料\T113S3\/t113s3.cfg
Debug: 27 57 command.c:155 script_debug(): command - reset_config none srst_pulls_trst
Debug: 28 59 command.c:155 script_debug(): command - jtag newtap t113s3 cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id 0x5ba00477
Debug: 29 62 tcl.c:557 jim_newtap_cmd(): Creating New Tap, Chip: t113s3, Tap: cpu, Dotted: t113s3.cpu, 8 params
Debug: 30 65 tcl.c:582 jim_newtap_cmd(): Processing option: -irlen
Debug: 31 67 tcl.c:582 jim_newtap_cmd(): Processing option: -ircapture
Debug: 32 70 tcl.c:582 jim_newtap_cmd(): Processing option: -irmask
Debug: 33 72 tcl.c:582 jim_newtap_cmd(): Processing option: -expected-id
Debug: 34 74 core.c:1474 jtag_tap_init(): Created Tap: t113s3.cpu @ abs position 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 35 76 command.c:155 script_debug(): command - dap create t113s3.dap -chain-position t113s3.cpu
Debug: 36 79 command.c:155 script_debug(): command - target create t113s3.cpu cortex_a -dap t113s3.dap
Info : 37 82 server.c:297 add_service(): Listening on port 6666 for tcl connections
Info : 38 85 server.c:297 add_service(): Listening on port 4444 for telnet connections
Debug: 39 88 command.c:155 script_debug(): command - init
Debug: 40 89 command.c:155 script_debug(): command - target init
Debug: 41 91 command.c:155 script_debug(): command - target names
Debug: 42 92 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-flash-erase-start
Debug: 43 95 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-flash-erase-start reset init
Debug: 44 97 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-flash-write-end
Debug: 45 102 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-flash-write-end reset halt
Debug: 46 105 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-attach
Debug: 47 107 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-attach halt 1000
Debug: 48 110 target.c:1657 handle_target_init_command(): Initializing targets...
Debug: 49 111 semihosting_common.c:109 semihosting_common_init():
Debug: 50 114 jlink.c:635 jlink_init(): Using libjaylink 0.4.0 (compiled with 0.4.0)
Debug: 51 130 jlink.c:514 jaylink_log_handler(): Found device (VID:PID = 1366:0105, bus:address = 002:055)
Debug: 52 133 jlink.c:514 jaylink_log_handler(): Device: USB address = 0
Debug: 53 135 jlink.c:514 jaylink_log_handler(): Device: Serial number = 4294967295
Debug: 54 137 jlink.c:514 jaylink_log_handler(): Allocating new device instance
Debug: 55 139 jlink.c:514 jaylink_log_handler(): Found 1 USB device(s)
Debug: 56 141 jlink.c:514 jaylink_log_handler(): Trying to open device (bus:address = 002:055)
Debug: 57 143 jlink.c:514 jaylink_log_handler(): Using endpoint 83 (IN) and 02 (OUT)
Debug: 58 147 jlink.c:514 jaylink_log_handler(): Device opened successfully
Info : 66 149 jlink.c:707 jlink_init(): J-Link V1n compiled Feb 13 2023 17:39:21
Info : 79 152 jlink.c:748 jlink_init(): Hardware version: 11.00
Info : 88 153 jlink.c:789 jlink_init(): VTarget = 3.321 V
Debug: 94 155 jlink.c:514 jaylink_log_handler(): Last read operation left 16 bytes in the buffer
Debug: 104 158 jlink.c:942 jlink_reset(): TRST: 0, SRST: 0
Debug: 124 174 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 125 178 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Debug: 132 180 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 133 183 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Info : 134 185 adapter.c:179 adapter_init(): clock speed 1000 kHz
Debug: 135 187 openocd.c:134 handle_init_command(): Debug Adapter init complete
Debug: 136 191 command.c:155 script_debug(): command - transport init
Debug: 137 193 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 138 195 jlink.c:942 jlink_reset(): TRST: 0, SRST: 0
Debug: 143 196 core.c:830 jtag_add_reset(): SRST line released
Debug: 144 198 core.c:855 jtag_add_reset(): TRST line released
Debug: 145 199 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 146 201 command.c:155 script_debug(): command - jtag arp_init
Debug: 147 203 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 148 207 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 158 209 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 159 212 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 169 215 core.c:1133 jtag_examine_chain_display(): JTAG tap: t113s3.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x5)
Debug: 170 219 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Debug: 180 222 core.c:1421 jtag_validate_ircapture(): t113s3.cpu: IR capture 0x01
Debug: 181 224 command.c:155 script_debug(): command - dap init
Debug: 182 226 arm_dap.c:97 dap_init_all(): Initializing all DAPs ...
Debug: 183 228 arm_dap.c:121 dap_init_all(): DAP t113s3.cpu configured by default to use ADIv5 protocol
Debug: 184 230 arm_adi_v5.c:679 dap_dp_init(): t113s3.dap
Debug: 185 232 arm_adi_v5.c:711 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 186 233 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 205 239 arm_adi_v5.c:719 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 206 241 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 243 244 openocd.c:151 handle_init_command(): Examining targets...
Debug: 244 246 target.c:1843 target_call_event_callbacks(): target event 19 (examine-start) for core t113s3.cpu
Debug: 245 250 arm_adi_v5.c:1095 dap_get_ap(): refcount AP#0x0 get 1
Debug: 264 253 arm_adi_v5.c:1120 dap_put_ap(): refcount AP#0x0 put 0
Debug: 265 255 arm_adi_v5.c:1095 dap_get_ap(): refcount AP#0x1 get 1
Debug: 284 258 arm_adi_v5.c:1038 dap_find_get_ap(): Found MEM-AP APB2 or APB3 at AP index: 1 (IDR=0x44770002)
Debug: 321 263 arm_adi_v5.c:825 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 322 267 arm_adi_v5.c:836 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 323 270 cortex_a.c:2901 cortex_a_examine_first(): t113s3.cpu's dbgbase is not set, trying to detect using the ROM table
Debug: 576 308 arm_adi_v5.c:2200 dap_lookup_cs_component(): CS lookup found at 0x81410000
Debug: 577 313 cortex_a.c:2911 cortex_a_examine_first(): Detected core 0 dbgbase: 0x81410000
Debug: 614 318 cortex_a.c:2934 cortex_a_examine_first(): didr = 0x3515f005
Debug: 615 320 cortex_a.c:2935 cortex_a_examine_first(): cpuid = 0x410fc075
Debug: 634 324 cortex_a.c:2944 cortex_a_examine_first(): target->coreid 0 DBGPRSR  0x2b
Debug: 635 327 cortex_a.c:2953 cortex_a_examine_first(): target->coreid 0 was reset!
Debug: 654 330 cortex_a.c:2960 cortex_a_examine_first(): target->coreid 0 DBGOSLSR 0xa
Debug: 655 332 cortex_a.c:2966 cortex_a_examine_first(): target->coreid 0 OSLock set! Trying to unlock
Debug: 710 337 cortex_a.c:2991 cortex_a_examine_first(): target->coreid 0 has security extensions
Debug: 711 341 cortex_a.c:2996 cortex_a_examine_first(): target->coreid 0 has virtualization extensions
Info : 712 344 arm_dpm.c:1100 arm_dpm_setup(): t113s3.cpu: hardware has 6 breakpoints, 4 watchpoints
Debug: 713 347 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 81410140
Debug: 732 350 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 81410144
Debug: 751 353 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 81410148
Debug: 770 357 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 8141014c
Debug: 789 361 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 81410150
Debug: 808 364 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 81410154
Debug: 827 367 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 814101c0
Debug: 846 371 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 814101c4
Debug: 865 375 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 814101c8
Debug: 884 378 cortex_a.c:595 cortex_a_bpwp_disable(): A: bpwp disable, cr 814101cc
Debug: 903 381 cortex_a.c:3030 cortex_a_examine_first(): Configured 6 hw breakpoints
Debug: 904 383 cortex_a.c:3044 cortex_a_examine_first(): Configured 4 hw watchpoints
Debug: 977 391 target.c:1843 target_call_event_callbacks(): target event 21 (examine-end) for core t113s3.cpu
Debug: 978 394 command.c:155 script_debug(): command - flash init
Debug: 979 395 tcl.c:1375 handle_flash_init_command(): Initializing flash devices...
Debug: 980 397 command.c:155 script_debug(): command - nand init
Debug: 981 399 tcl.c:487 handle_nand_init_command(): Initializing NAND devices...
Debug: 982 402 command.c:155 script_debug(): command - pld init
Debug: 983 404 pld.c:194 handle_pld_init_command(): Initializing PLDs...
Debug: 984 407 command.c:155 script_debug(): command - tpiu init
Info : 985 409 gdb_server.c:3791 gdb_target_start(): starting gdb server for t113s3.cpu on 3333
Info : 986 412 server.c:297 add_service(): Listening on port 3333 for gdb connections

#include <xboot.h>

void sys_jtag_init(void)
{
	virtual_addr_t addr;
	u32_t val;

	/* Config GPIOF0, GPIOF1, GPIOF3 and GPIOF5 to JTAG mode */
	addr = 0x020000f0 + 0x00;
	val = read32(addr);
	val &= ~(0xf << ((0 & 0x7) << 2));
	val |= ((0x3 & 0xf) << ((0 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((1 & 0x7) << 2));
	val |= ((0x3 & 0xf) << ((1 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((3 & 0x7) << 2));
	val |= ((0x3 & 0xf) << ((3 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((5 & 0x7) << 2));
	val |= ((0x3 & 0xf) << ((5 & 0x7) << 2));
	write32(addr, val);
}



void sys_jtag_init2(void)
{
	virtual_addr_t addr;
	u32_t val;

	/* Config GPIOE8, GPIOE9, GPIOE10 and GPIOE11 to JTAG mode 
			  MS        DI      DO          CK*/
	addr = 0x020000c4 + 0x00;
	val = read32(addr);
	val &= ~(0xf << (((8-8) & 0x7) << 2));
	val |= ((0x6 & 0xf) << (((8-8) & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << (((9-8) & 0x7) << 2));
	val |= ((0x6 & 0xf) << (((9-8) & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << (((10-8) & 0x7) << 2));
	val |= ((0x6 & 0xf) << (((10-8) & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << (((11-8) & 0x7) << 2));
	val |= ((0x6 & 0xf) << (((11-8) & 0x7) << 2));
	write32(addr, val);
} 

 /*
 * start.S
 *
 * Copyright(c) 2007-2021 Jianjun Jiang <8192542@qq.com>
 * Official site: http://xboot.org
 * Mobile phone: +86-18665388956
 * QQ: 8192542
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

	.global _start
_start:
	mov r0, #0
	mcr p15, 0, r0, c8, c7, 0
	mcr p15, 0, r0, c7, c5, 0
	mcr p15, 0, r0, c7, c5, 6
	mcr p15, 0, r0, c7, c10, 4
	mcr p15, 0, r0, c7, c5, 4
	b reset

reset:
	ldr r0, =0x00047fe0
	str sp, [r0, #0]
	str lr, [r0, #4]
	mrs lr, cpsr
	str lr, [r0, #8]
	mrc p15, 0, lr, c1, c0, 0
	str lr, [r0, #12]
	mrc p15, 0, lr, c12, c0, 0
	str lr, [r0, #16]
	mrc p15, 0, lr, c1, c0, 0
	str lr, [r0, #20]

	bl sys_jtag_init2

	ldr r0, =0x00047fe0
	ldr sp, [r0, #0]
	ldr lr, [r0, #4]
	ldr r1, [r0, #20]
	mcr p15, 0, r1, c1, c0, 0
	ldr r1, [r0, #16]
	mcr p15, 0, r1, c12, c0, 0
	ldr r1, [r0, #12]
	mcr p15, 0, r1, c1, c0, 0
	ldr r1, [r0, #8]
	msr cpsr, r1
	bx lr

xfel ddr t113-s3
xfel jtag

C:\msys64\mingw64\bin>openocd.exe -f t113s3-mangguo.cfg -f t113s3.cfg -d -s E:\资料\T113S3\
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
User : 3 3 options.c:52 configuration_output_handler(): debug_level: 3
User : 4 5 options.c:52 configuration_output_handler():
Debug: 5 7 configuration.c:33 add_script_search_dir(): adding E:\资料\T113S3\
Debug: 6 10 options.c:233 add_default_dirs(): bindir=D:/a/msys64/mingw64/bin
Debug: 7 12 options.c:234 add_default_dirs(): pkgdatadir=D:/a/msys64/mingw64/share/openocd
Debug: 8 14 options.c:235 add_default_dirs(): exepath=C:/msys64/mingw64/bin
Debug: 9 16 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 10 18 configuration.c:33 add_script_search_dir(): adding C:/Users/17204/AppData/Roaming/OpenOCD
Debug: 11 22 configuration.c:33 add_script_search_dir(): adding C:/msys64/mingw64/bin/../share/openocd/site
Debug: 12 26 configuration.c:33 add_script_search_dir(): adding C:/msys64/mingw64/bin/../share/openocd/scripts
Debug: 13 29 command.c:155 script_debug(): command - ocd_find t113s3-mangguo.cfg
Debug: 14 31 configuration.c:88 find_file(): found E:\资料\T113S3\/t113s3-mangguo.cfg
Debug: 15 37 command.c:155 script_debug(): command - ocd_find interface/jlink.cfg
Debug: 16 40 configuration.c:88 find_file(): found C:/msys64/mingw64/bin/../share/openocd/scripts/interface/jlink.cfg
Debug: 17 45 command.c:155 script_debug(): command - adapter driver jlink
Debug: 18 47 command.c:155 script_debug(): command - adapter speed 1000
Debug: 19 50 adapter.c:251 adapter_config_khz(): handle adapter khz
Debug: 20 52 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 21 54 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 22 57 command.c:155 script_debug(): command - transport select jtag
User : 23 61 options.c:52 configuration_output_handler(): jtagUser : 24 63 options.c:52 configuration_output_handler():
Debug: 25 65 command.c:155 script_debug(): command - ocd_find t113s3.cfg
Debug: 26 68 configuration.c:88 find_file(): found E:\资料\T113S3\/t113s3.cfg
Debug: 27 70 command.c:155 script_debug(): command - reset_config none srst_pulls_trst
Debug: 28 72 command.c:155 script_debug(): command - jtag newtap t113s3 cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id 0x5ba00477
Debug: 29 78 tcl.c:557 jim_newtap_cmd(): Creating New Tap, Chip: t113s3, Tap: cpu, Dotted: t113s3.cpu, 8 params
Debug: 30 82 tcl.c:582 jim_newtap_cmd(): Processing option: -irlen
Debug: 31 83 tcl.c:582 jim_newtap_cmd(): Processing option: -ircapture
Debug: 32 85 tcl.c:582 jim_newtap_cmd(): Processing option: -irmask
Debug: 33 87 tcl.c:582 jim_newtap_cmd(): Processing option: -expected-id
Debug: 34 89 core.c:1474 jtag_tap_init(): Created Tap: t113s3.cpu @ abs position 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 35 93 command.c:155 script_debug(): command - dap create t113s3.dap -chain-position t113s3.cpu
Debug: 36 98 command.c:155 script_debug(): command - target create t113s3.cpu cortex_a -dap t113s3.dap
Info : 37 101 server.c:297 add_service(): Listening on port 6666 for tcl connections
Info : 38 103 server.c:297 add_service(): Listening on port 4444 for telnet connections
Debug: 39 105 command.c:155 script_debug(): command - init
Debug: 40 107 command.c:155 script_debug(): command - target init
Debug: 41 110 command.c:155 script_debug(): command - target names
Debug: 42 112 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-flash-erase-start
Debug: 43 114 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-flash-erase-start reset init
Debug: 44 117 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-flash-write-end
Debug: 45 119 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-flash-write-end reset halt
Debug: 46 122 command.c:155 script_debug(): command - t113s3.cpu cget -event gdb-attach
Debug: 47 126 command.c:155 script_debug(): command - t113s3.cpu configure -event gdb-attach halt 1000
Debug: 48 129 target.c:1657 handle_target_init_command(): Initializing targets...
Debug: 49 131 semihosting_common.c:109 semihosting_common_init():
Debug: 50 133 jlink.c:635 jlink_init(): Using libjaylink 0.4.0 (compiled with 0.4.0)
Debug: 51 149 jlink.c:514 jaylink_log_handler(): Found device (VID:PID = 1366:0105, bus:address = 002:055)
Debug: 52 152 jlink.c:514 jaylink_log_handler(): Device: USB address = 0
Debug: 53 154 jlink.c:514 jaylink_log_handler(): Device: Serial number = 4294967295
Debug: 54 158 jlink.c:514 jaylink_log_handler(): Allocating new device instance
Debug: 55 160 jlink.c:514 jaylink_log_handler(): Found 1 USB device(s)
Debug: 56 162 jlink.c:514 jaylink_log_handler(): Trying to open device (bus:address = 002:055)
Debug: 57 164 jlink.c:514 jaylink_log_handler(): Using endpoint 83 (IN) and 02 (OUT)
Debug: 58 167 jlink.c:514 jaylink_log_handler(): Device opened successfully
Info : 66 169 jlink.c:707 jlink_init(): J-Link V1n compiled Feb 13 2023 17:39:21
Info : 79 173 jlink.c:748 jlink_init(): Hardware version: 11.00
Info : 88 175 jlink.c:789 jlink_init(): VTarget = 3.322 V
Debug: 94 176 jlink.c:514 jaylink_log_handler(): Last read operation left 16 bytes in the buffer
Debug: 104 179 jlink.c:942 jlink_reset(): TRST: 0, SRST: 0
Debug: 124 185 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 125 188 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Debug: 132 190 adapter.c:215 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 133 193 adapter.c:219 adapter_khz_to_speed(): have adapter set up
Info : 134 195 adapter.c:179 adapter_init(): clock speed 1000 kHz
Debug: 135 196 openocd.c:134 handle_init_command(): Debug Adapter init complete
Debug: 136 198 command.c:155 script_debug(): command - transport init
Debug: 137 202 transport.c:219 handle_transport_init(): handle_transport_init
Debug: 138 204 jlink.c:942 jlink_reset(): TRST: 0, SRST: 0
Debug: 143 206 core.c:830 jtag_add_reset(): SRST line released
Debug: 144 208 core.c:855 jtag_add_reset(): TRST line released
Debug: 145 210 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 146 212 command.c:155 script_debug(): command - jtag arp_init
Debug: 147 216 core.c:1509 jtag_init_inner(): Init JTAG chain
Debug: 148 219 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 158 222 core.c:1234 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 159 224 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Error: 169 227 core.c:1122 jtag_examine_chain_check(): JTAG scan chain interrogation failed: all zeroes
Error: 170 234 core.c:1124 jtag_examine_chain_check(): Check JTAG interface, timings, target power, etc.
Error: 171 237 core.c:1554 jtag_init_inner(): Trying to use configured scan chain anyway...
Debug: 172 239 core.c:1364 jtag_validate_ircapture(): IR capture validation scan
Error: 182 242 core.c:1413 jtag_validate_ircapture(): t113s3.cpu: IR capture error; saw 0x00 not 0x01
Debug: 183 248 core.c:328 jtag_call_event_callbacks(): jtag event: TAP reset
Warn : 193 252 core.c:1577 jtag_init_inner(): Bypassing JTAG setup events due to errors
Debug: 194 254 command.c:155 script_debug(): command - dap init
Debug: 195 256 arm_dap.c:97 dap_init_all(): Initializing all DAPs ...
Debug: 196 258 arm_dap.c:121 dap_init_all(): DAP t113s3.cpu configured by default to use ADIv5 protocol
Debug: 197 264 arm_adi_v5.c:679 dap_dp_init(): t113s3.dap
Debug: 198 266 arm_adi_v5.c:711 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 199 268 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Error: 209 271 adi_v5_jtag.c:446 jtagdp_overrun_check(): Invalid ACK (0) in DAP response
Debug: 219 274 command.c:544 run_command(): Command 'dap init' failed with error code -107
User : 220 280 command.c:608 command_run_line():
Debug: 221 281 command.c:544 run_command(): Command 'init' failed with error code -4
User : 222 283 command.c:608 command_run_line():
Debug: 223 285 target.c:2199 target_free_all_working_areas_restore(): freeing all working areas
Debug: 229 288 jlink.c:514 jaylink_log_handler(): Last read operation left 16 bytes in the buffer
Debug: 231 292 jlink.c:514 jaylink_log_handler(): Closing device (bus:address = 002:055)
Debug: 232 296 jlink.c:514 jaylink_log_handler(): Device closed successfully
Debug: 233 299 jlink.c:514 jaylink_log_handler(): Device destroyed (bus:address = 002:055)

dram start
dram init ok
welcome to T113s3
now run in security
[D] CLK: CPU PLL=PLL_CPU FREQ=1200MHz
[D] CLK: PLL_peri (2X)=1200MHz, (1X)=600MHz, (800M)=800MHz
[D] CLK: PLL_ddr=1584MHz
gic_base address is 0x3020000
gic irqs supported is 224
0)  current val = 0
1)  current val = 22779507
2)  current val = 21555507
3)  current val = 20331507
4)  current val = 19107507
5)  current val = 17883507
6)  current val = 16659507
7)  current val = 15435507
8)  current val = 14211506
9)  current val = 12987506
10)  current val = 11763507
11)  current val = 10539507
12)  current val = 9315507
13)  current val = 8091507
14)  current val = 6867506
15)  current val = 5643506
16)  current val = 4419507
17)  current val = 3195507
18)  current val = 1971507
19)  current val = 747506
20)  current val = 23523507

#include "debug.h"
#include "arch_timer/arch_timer.h"
#include "timer/timer.h"
#include "gic400/gic400.h"
#include "gic400/t113_irq.h"
#include "t113_clk/sunxi_clk.h"
#include "arm32.h"
#include "bit_ops.h"
static void timer0_irq_handler(void * data);
static void timer1_irq_handler(void * data);
int main(void)
{
    u32 cur_val = 0;
    u32 scr;
    message("welcome to T113s3\r\n");
    scr = arm32_read_scr_ns();
    if(GET_BIT(scr,0))//获取SCR.NS位，如果是0则是安全模式，如果是1则是非安全模式
    {
        message("now run in non_security\r\n");
    }
    else
    {
        message("now run in security\r\n");
    }

    sunxi_clk_dump();
    start_gic();
    register_irq(T113_IRQ_TIMER1,timer1_irq_handler,NULL,(30 << 3),3);
    start_ms_timer(TIMER1,1000);
    int i = 0;
    while(1)
    {
        cur_val = get_current_timer_value(TIMER1);
        message("%d)  current val = %d \r\n",i,cur_val);
        mdelay(50);
        i ++;
    }
    
    
}

static void timer0_irq_handler(void * data)
{
    //清中断
    clear_timern_irq(TIMER0);
    message("timer0 irq get \r\n");
}

static void timer1_irq_handler(void * data)
{
    //清中断
    clear_timern_irq(TIMER1);
    message("timer1 irq get \r\n");
}

#include "gic400/gic400.h"
#include "gic400/t113_irq.h"
#include "io.h"
#include "smp.h"
#include "debug.h"
enum {
	DIST_CTRL 			= 0x1000,
	DIST_CTR 			= 0x1004,
	DIST_IIDR           = 0X1008,
	DIST_IGROUPRn       = 0x1080,
	DIST_ENABLE_SET 	= 0x1100,
	DIST_ENABLE_CLEAR 	= 0x1180,
	DIST_PENDING_SET 	= 0x1200,
	DIST_PENDING_CLEAR	= 0x1280,
	DIST_ACTIVE_BIT		= 0x1300,
	DIST_PRI			= 0x1400,
	DIST_TARGET			= 0x1800,
	DIST_CONFIG			= 0x1c00,
	DIST_SOFTINT		= 0x1f00,

	CPU_CTRL 			= 0x2000,
	CPU_PRIMASK 		= 0x2004,
	CPU_BINPOINT 		= 0x2008,
	CPU_INTACK 			= 0x200c,
	CPU_EOI 			= 0x2010,
	CPU_RUNNINGPRI 		= 0x2014,
	CPU_HIGHPRI 		= 0x2018,
}GIC_REG_NUM;

#define FGicPs_PRIORITY_OFFSET_CALC(InterruptID) \
	((u32)DIST_PRI + (((InterruptID)/4U) * 4U))
#define FGicPs_INT_CFG_OFFSET_CALC(InterruptID) \
	((u32)DIST_CONFIG + (((InterruptID)/16U) * 4U))

u32 read_gicd_pri(int int_id)
{
	return read32(T113_GIC_400_BASE + FGicPs_PRIORITY_OFFSET_CALC(int_id));
}

void write_gicd_pri(int int_id, u32 val)
{
	write32(T113_GIC_400_BASE + FGicPs_PRIORITY_OFFSET_CALC(int_id),val);
}

u32 read_gicd_cfg(int int_id)
{
	return read32(T113_GIC_400_BASE + FGicPs_INT_CFG_OFFSET_CALC(int_id));
}

void write_gicd_cfg(int int_id, u32 val)
{
	write32(T113_GIC_400_BASE + FGicPs_INT_CFG_OFFSET_CALC(int_id),val);
}

#if 0
static  inline uint32_t arm32_get_gic_base(void)
{
	uint32_t value;

	__asm__ __volatile__(
		"mrc p15, 4, %0, c15, c0, 0"
		: "=r" (value)
		:
		: "memory");

	return value;
}
#endif

void gic400_dist_init(void)
{
	u32_t gic_irqs;
	u32_t cpumask;

    u32_t gic_base = T113_GIC_400_BASE;
	int i;
	message("gic_base address is 0x%x \r\n",gic_base);
	write32(gic_base + DIST_CTRL, 0x0);

	/*
	 * Find out how many interrupts are supported.
	 * The GIC only supports up to 1020 interrupt sources.
	 */
	gic_irqs = read32(gic_base + DIST_CTR) & 0x1f;
	gic_irqs = (gic_irqs + 1) * 32;
	message("gic irqs supported is %d \r\n",gic_irqs);
	if(gic_irqs > 1020)
		gic_irqs = 1020;


	/*
	 * Set all global interrupts to this CPU only.
	 */
	cpumask = 1 << smp_processor_id();
	cpumask |= cpumask << 8;
	cpumask |= cpumask << 16;
	
	for(i = 32; i < gic_irqs; i += 4)
		write32(gic_base + DIST_TARGET + (i / 4 )* 4, cpumask);

	/*
	 * Set all global interrupts to be level triggered, active low.
	 */
	for(i = 32; i < gic_irqs; i += 16)
		write32(gic_base + DIST_CONFIG + (i /16) * 4 , 0);

	/*
	 * Set priority on all global interrupts.
	 */
	for(i = 32; i < gic_irqs; i += 4)
		write32(gic_base + DIST_PRI + (i / 4) * 4, 0xa0a0a0a0);

	/*
	 * Disable all interrupts, leave the SGI and PPI alone
	 * as these enables are banked registers.
	 */
	for(i = 32; i < gic_irqs; i += 32)
		write32(gic_base + DIST_ENABLE_CLEAR + (i / 32) * 4, 0xffffffff);

	//将所有中断设为group0
	for(i = 32 ; i < gic_irqs; i += 32)
		write32(gic_base + DIST_IGROUPRn + (i / 32) * 4, 0x0);


	write32(gic_base + DIST_CTRL, 0x1);
}

void gic400_cpu_init(void)
{
	int i;
    u32_t gic_base = T113_GIC_400_BASE;
	/*
	 * Deal with the banked SGI and PPI interrupts - enable all
	 * SGI interrupts, ensure all PPI interrupts are disabled.
	 */
	write32(gic_base + DIST_ENABLE_CLEAR, 0xffff0000);
	write32(gic_base + DIST_ENABLE_SET, 0x0000ffff);

	/*
	 * Set priority on SGI and PPI interrupts
	 */
	for(i = 0; i < 32; i += 4)
		write32(gic_base + DIST_PRI + ( i / 4 ) * 4, 0xa0a0a0a0);

	write32(gic_base + CPU_PRIMASK, 0xf0);
	write32(gic_base + CPU_CTRL, 0x1);
}

void irq_gic400_enable(int irq) //unmask对应中断
{
	write32(T113_GIC_400_BASE + DIST_ENABLE_SET + (irq / 32) * 4, 1 << (irq % 32));
}

void irq_gic400_disable(int irq)//mask对应中断
{
	write32(T113_GIC_400_BASE + DIST_ENABLE_CLEAR + (irq / 32) * 4, 1 << (irq % 32));
}

void irq_gic400_settype(void)
{

}

void irq_gic400_dispatch(void)//处理中断后清除中断标志
{
	int irq = read32(T113_GIC_400_BASE + CPU_INTACK) & 0x3ff;
    irq_gic400_disable(irq);

    do_handler(irq);

    write32(T113_GIC_400_BASE + CPU_EOI, irq);//清除中断
	irq_gic400_enable(irq);
}


void gic_interrupt_handle_exception(void* regs)
{
    irq_gic400_dispatch();
}


void start_gic(void)
{
    gic400_dist_init();
    gic400_cpu_init();
    
}

bool_t register_irq(int irq,void (*func)(void *), void * data, u8 Priority, u8 trigger)
{
    u32 val;
    u8 LocalPriority;
    if(!func)
		return FALSE;
    if(irq_hanlder_arry[irq].func != null_interrupt_function)
        return FALSE;
    irq_hanlder_arry[irq].func = func;
    irq_hanlder_arry[irq].data = data;

    // val = read_gicd_pri(irq);
    // LocalPriority = LocalPriority & (u8)(0x000000F8U);
    // val &= ~(0x000000FFU << ((irq%4U)*8U));
	// val |= (u32)LocalPriority << ((irq%4U)*8U);
    // write_gicd_pri(irq,val);

    // val = read_gicd_cfg(irq);
    // val &= ~(0x00000003U << ((irq%16U)*2U));
	// val |= (u32)trigger << ((irq%16U)*2U);

  //  write_gicd_cfg(irq,val);

    irq_gic400_enable(irq);
    arm32_interrupt_enable();
    return TRUE;
}

#include "timer/timer.h"

enum {
	TMR_IRQ_EN_REG 		       =0x0000	,
	TMR_IRQ_STA_REG 		   =0x0004  , 
	TMR0_CTRL_REG 	           =0x0010  ,
	TMR0_INTV_VALUE_REG 	   =0x0014  ,
	TMR0_CUR_VALUE_REG 	       =0x0018,
	TMR1_CTRL_REG              =0x0020  ,
    TMR1_INTV_VALUE_REG        =0x0024,
    TMR1_CUR_VALUE_REG         =0x0028,

}TIMER_REG_OFFSET;

#define Timer_Periodic_mode 0
#define Timer_Single_mode   1

//a &= ~(数值<<每组位数*组编号) ：将连续几位清零的方法
//数值表示一组中每个bit都是1的情况下的值，比如组位数是2，则数值就是11b所代表的值，即3
//组编号是给寄存器多少个bit为1组进行分组，组号从0开始




void timern_init(int timer_id,  int timing_mode) //时钟频率为24000000/2
{
    u32 addr,val;
    if(timer_id == 0)
        addr = TIMER_BASE + TMR0_CTRL_REG;
    else
        addr = TIMER_BASE + TMR1_CTRL_REG;

    if(timing_mode == Timer_Periodic_mode)
        val = (u32)0x14;
    else
        val = (u32)0x94;

    write32(addr,val);

}

void set_timern_interval_value(int timer_id, u32 value)
{
    u32 addr,val;
    val = value;
    if(timer_id == 0)
        addr = TIMER_BASE + TMR0_INTV_VALUE_REG;
    else
        addr = TIMER_BASE + TMR1_INTV_VALUE_REG;

    write32(addr,val);//设置间隔值
}

void load_timern_interval_value(int timer_id)
{
    u32 addr,val;
    if(timer_id == 0)
        addr = TIMER_BASE + TMR0_CTRL_REG;
    else
        addr = TIMER_BASE + TMR1_CTRL_REG;
    write32(addr, read32(addr)|(1<<1)); //Set the Reload bit
    
}

void start_timer(int timer_id)
{
    u32 addr,val;
    if(timer_id == 0)
        addr = TIMER_BASE + TMR0_CTRL_REG;
    else
        addr = TIMER_BASE + TMR1_CTRL_REG;
    val	 = read32(addr);    
    val |= (0x1 << 0);
    write32(addr,val);

}

void start_ms_timer(int timer_id,u32 ms)
{
    u32 value = (24000 * ms);
    u32 addr;
    enable_timern_irq(timer_id);
    set_timern_interval_value(timer_id,value);
    timern_init(timer_id, Timer_Periodic_mode);
    load_timern_interval_value(timer_id);
    if(timer_id == 0)
        addr = TIMER_BASE + TMR0_CTRL_REG;
    else
        addr = TIMER_BASE + TMR1_CTRL_REG;
    while((read32(addr)>>1)&1);
    start_timer(timer_id);
}

void enable_timern_irq(int timer_id)
{
    u32 addr,val;
    addr = TIMER_BASE + TMR_IRQ_EN_REG;
    if(timer_id == 0)
    {
         val = read32(addr);  
         val |= (1 << 0);

    }
    else
    {
         val = read32(addr);  
         val |= (1 << 1);
    }

    write32(addr,val);

    addr = TIMER_BASE + TMR_IRQ_STA_REG;
    if(timer_id == 0)
    {
        val = read32(addr);
         
        val |= (1 << 0);
            

    }
    else
    {
        val = read32(addr); 
        
        val |= (1 << 1);
         
    }
    write32(addr,val);
}

void clear_timern_irq(int timer_id)
{
    u32 addr,val;
    addr = TIMER_BASE + TMR_IRQ_STA_REG;
    
    if(timer_id == 0)
    {
         val = read32(addr);
         if( (val & 0x01))
         {
            val |= (1 << 0);
            
         }  
            

    }
    else
    {
         val = read32(addr); 
         if((val & 0x2)) 
         {
            val |= (1 << 1);
         }
         
    }
    write32(addr,val);
}


u32 get_current_timer_value(int timer_id)
{
    u32 addr,val;
     if(timer_id == 0)
        addr = TIMER_BASE + TMR0_CUR_VALUE_REG;
    else
        addr = TIMER_BASE + TMR1_CUR_VALUE_REG;

    val = read32(addr);
    
    return val;
}