WhyCan Forum(哇酷开发者社区)

The Broadcom® BCM56150 System-on-a-Chip (SoC)
switch family offers industry-leading integration and
performance in a small footprint. The device offers up to
24 multilayer GbE ports and a maximum of four integrated
10G SerDes transceivers and associated PCS for native
support of SGMII, XFI, 10GBASE-KR/CR/LR/SR with
Broadcom’s proprietary HiGig2™ and HiGig+ interfaces in
a 29 mm x 29 mm package. Offering the industry's highest
level of integration, the BCM56150 has embedded 16
GPHYs and a powerful 1 GHz ARM® Cortex™-A9 single-
core processor. The BCM56150 is ideal for cost-sensitive
edge connectivity applications, such as L3-managed
wiring closet switches for enterprise or MTU/MDU
switches for service providers.
The BCM56150 device offers multiple I/O configurations
and speed (1G/2.5G/5G/10G) that address key segments
of edge connectivity. A single BCM56150 device supports
the popular 24x GbE switch with 4x 10GbE uplinks.
Two BCM56150 devices can be connected to build non-
blocking 48x GbE switch systems with 4x 10GbE uplinks.
To reduce the overall system cost, the device is
engineered for low power operation to enable 48x GbE +
4x 10GbE (or 13G stacking) designs. Furthermore, the
device I/O is optimized for board layout.
When used with the Broadcom QSGMII PHY, the
BCM56150 device can be cascaded to the PHYs without
any trace crossovers. The optimized I/O map reduces
system design effort and enables low-cost PCB design.
The BCM56150 device offers many advanced features,
such as IEEE 802.1Q VLAN, VLAN translation, enhanced
Denial of Service (DoS) protection, IP-MAC binding
checks, ARP spoofing detection, IPv4 and IPv6 support,
advanced ContentAware™ Engine, IEEE 802.1p Quality
of Service (QoS), Energy Efficient Ethernet™ (EEE), and
HiGig™ stacking.

Integrated High-Performance Cortex-A9 processor.
• Highly integrated 24-port 10/100/1000 Mbps Ethernet
switch SoC.
• Embedded 16 integrated copper 10/100/1000 EEE
PHYs.
• Two integrated QSGMII/1GbE interfaces.
• Up to four XFI/SFI uplink/stacking ports or 2 XFI + 2
HiGig-Duo™[13] cascade ports for non-blocking 48-
port design.
• Non-blocking architecture, line rate for all packet sizes.
• Fully integrated 1.5 MB packet buffer.
• Intelligent Memory Management Unit (MMU) optimized
for handling bursty data traffic.
• Advanced TCAM-based ContentAware™ Engine
• L2, IPv4/IPv6 L3 packet classification.
• Flow-based classification, metering, and marking of
frames.
• Flexible Access Control List (ACL).
• Parallel lookup engines.
• Full IPv4 and IPv6 L3 routing support.
• Enhanced DoS attack statistics gathering.
• Low-power Energy Efficient Ethernet (EEE) support
with Burst and Batch control policy.
• Enterprise-class L2 scalability.
• Public key acceleration (PKA) engine to support Diffie-
Hellman, RSA, DSA, Elliptic Curve Diffie-Hellman
(ECDH), and ECDSA for up to 4096-bit modulus size.
• Non-deterministic hardware random number generator.
• Ethernet OAM support in hardware.
• 1588 (1-step TC) support.
• 1588 Time Stamping support (2-step).
• AVB support.
• MII interface to ARM A9 for management and debug.
• Support for Industrial Temperature.
• 40 nm CMOS process.