WhyCan Forum(哇酷开发者社区)

/*
New Instruction:   MOVX @DPTR1,A
Instruction Code:  0xA5
Instruction Cycle: 1
Instruction Operation:
   step-1. write ACC @DPTR1 into xdata SRAM embedded chip
   step-2. increase DPTR1
ASM example:
       INC  XBUS_AUX
       MOV  DPTR,#TARGET_ADDR ;DPTR1
       DEC  XBUS_AUX
       MOV  DPTR,#SOURCE_ADDR ;DPTR0
       MOV  R7,#xxH
 LOOP: MOVX A,@DPTR ;DPTR0
       INC  DPTR    ;DPTR0, if need
       DB   0A5H    ;MOVX @DPTR1,A & INC DPTR1
       DJNZ R7,LOOP
*/

extern UINT8X Ep1Buffer[];
extern UINT8X syscall_buf[];

BOOL VerifyMemory(void)
{
	uint8_t i = 0;

	for(i=0; i<0xFF; i++)
	{
		if(Ep1Buffer[i] != syscall_buf[i])
		{
			return FALSE;
		}
	}

	return TRUE;
}

void testDualDPTR(void)
{
	// memcpy
	memset(syscall_buf, 0, 0xFF);
	P33 = 1;
	memcpy(syscall_buf, Ep1Buffer, 0xFF);
	P33 = 0;
	if(VerifyMemory())
	{
	#pragma ASM
		SETB P33
		NOP
		CLR P33
	#pragma ENDASM
	}

	// Dual DPTR without AUTO_INC
	memset(syscall_buf, 0, 0xFF);
#pragma ASM
	SETB P33
	ORL  XBUS_AUX, #01H     ;DPS=1
	MOV  DPTR, #syscall_buf ;DPTR1
	ANL  XBUS_AUX, #0FEH    ;DPS=0
	MOV  DPTR, #Ep1Buffer   ;DPTR0
	MOV  R7,#0FFH
L0: MOVX A, @DPTR           ;DPTR0
	INC  DPTR               ;DPTR0++
	DB   0A5H               ;MOVX @DPTR1,A & INC DPTR1
	DJNZ R7, L0
	CLR P33
#pragma ENDASM
	if(VerifyMemory())
	{
	#pragma ASM
		SETB P33
		NOP
		CLR P33
	#pragma ENDASM
	}

	// Dual DPTR with AUTO_INC
	memset(syscall_buf, 0, 0xFF);
#pragma ASM
	SETB P33
	ORL  XBUS_AUX, #05H     ;bDPTR_AUTO_INC=1 DPS=1
	MOV  DPTR, #syscall_buf ;DPTR1
	ANL  XBUS_AUX, #0FEH    ;DPS=0
	MOV  DPTR, #Ep1Buffer   ;DPTR0
	MOV  R7,#0FFH
L1: MOVX A, @DPTR           ;DPTR0
	DB   0A5H               ;MOVX @DPTR1,A & INC DPTR1
	DJNZ R7, L1
	ANL  XBUS_AUX, #0FBH    ;bDPTR_AUTO_INC=0
	CLR P33
#pragma ENDASM
	if(VerifyMemory())
	{
	#pragma ASM
		SETB P33
		NOP
		CLR P33
	#pragma ENDASM
	}
}