WhyCan Forum(哇酷开发者社区)

U-Boot SPL 2013.07 (Jan 26 2018 - 14:37:18)
Timer init
CLK stop
PLL init
pll_init:411
pll_cfg.pdiv = 10, pll_cfg.h2div = 5, pll_cfg.h0div = 5, pll_cfg.cdiv = 1, pll_cfg.l2div = 2
fbdiv = 62 , refdiv = 1 , fdivq = 4 ,pllod = 2 range = 3
cppcr is 03d01060
CPM_CPAPCR 07c0504d
fbdiv = 42 , refdiv = 1 , fdivq = 2 ,pllod = 1 range = 3
cppcr is 02900860
CPM_CPMPCR 07c0882d
fbdiv = 50 , refdiv = 1 , fdivq = 2 ,pllod = 1 range = 3
cppcr is 03100860
CPM_CPVPCR 0310086d
fbdiv = 50 , refdiv = 1 , fdivq = 2 ,pllod = 1 range = 3
cppcr is 03100860
CPM_CPEPCR 0310086d
cppcr 0x9a773310
apll_freq 750000000 
mpll_freq 1000000000 
vpll_freq = 1200000000 epll = 1200000000 
ddr sel mpll, cpu sel apll
ddrfreq 500000000
cclk  750000000
l2clk 375000000
h0clk 200000000
h2clk 200000000
pclk  100000000
CLK init
SDRAM init
sdram init start
ddr_inno_phy_init ..!
phy reg = 0x00000007, CL = 0x00000007