哇酷®开发者社区(WhyCan® Forum)

我拔掉SD 卡, 接入一个新的 W25Q128

重启 没有检测到 usb 设备啊
那个
是通过那个接口 使用的 请问

通过 arm-linux-gnueabihf-objdump -D u-boot > u-boot.dis
但是 生成的 代码 是纯汇编,两者没有混排起来,不知道 那些虹 被执行了
有没有 生成 混排起来的 反汇编, 应该是 gcc 优化掉了 它对应的调试消息 怎么改
例如:函数 s_init对应的 C 代码是

void s_init(void)
{
/*

• Undocumented magic taken from boot0, without this DRAM

• access gets messed up (seems cache related).

• The boot0 sources describe this as: "config ema for cache sram"
  */
  #if defined CONFIG_MACH_SUN6I
  setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  #elif defined CONFIG_MACH_SUN8I
  __maybe_unused uint version;

/ Unlock sram version info reg, read it, relock /
setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

/*

• Ideally this would be a switch case, but we do not know exactly

• which versions there are and which version needs which settings,

• so reproduce the per SoC code from the BSP.
  */
  #if defined CONFIG_MACH_SUN8I_A23
  if (version == 0x1650)
  setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  else / 0x1661 ? /
  setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  #elif defined CONFIG_MACH_SUN8I_A33
  if (version != 0x1667)
  setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  #endif
  / A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 /
  / No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 /
  #endif

#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN8I || \
defined CONFIG_MACH_SUN9I
/ Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg /
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
/ Enable non-secure access to some peripherals /
tzpc_init();
#endif

clock_init();
timer_init();
gpio_init();
i2c_init_board();
eth_init_board();
}

对应的 汇编是:

42e01140 <s_init>:
42e01140: e3a03507 mov r3, #29360128 ; 0x1c00000
42e01144: e92d4010 push {r4, lr}
42e01148: e5932024 ldr r2, [r3, #36] ; 0x24
42e0114c: e3822902 orr r2, r2, #32768 ; 0x8000
42e01150: e5832024 str r2, [r3, #36] ; 0x24
42e01154: e5932024 ldr r2, [r3, #36] ; 0x24
42e01158: f57ff05f dmb sy
42e0115c: e5932024 ldr r2, [r3, #36] ; 0x24
42e01160: e3c22902 bic r2, r2, #32768 ; 0x8000
42e01164: e5832024 str r2, [r3, #36] ; 0x24
42e01168: ee110f30 mrc 15, 0, r0, cr1, cr0, {1}
42e0116c: e3800040 orr r0, r0, #64 ; 0x40
42e01170: ee010f30 mcr 15, 0, r0, cr1, cr0, {1}
42e01174: eb000023 bl 42e01208 <clock_init>
42e01178: ebfffd29 bl 42e00624 <timer_init>
42e0117c: e3a01003 mov r1, #3
42e01180: e3a00028 mov r0, #40 ; 0x28
42e01184: eb00004e bl 42e012c4 <sunxi_gpio_set_cfgpin>
42e01188: e3a01003 mov r1, #3
42e0118c: e3a00029 mov r0, #41 ; 0x29
42e01190: eb00004b bl 42e012c4 <sunxi_gpio_set_cfgpin>
42e01194: e3a01001 mov r1, #1
42e01198: e3a00029 mov r0, #41 ; 0x29
42e0119c: eb000074 bl 42e01374 <sunxi_gpio_set_pull>
42e011a0: e8bd4010 pop {r4, lr}
42e011a4: ea000190 b 42e017ec <i2c_init_board>

如题

如题