WhyCan Forum(哇酷开发者社区)

楼主你好，

你在D1h上有没有遇到sunxifbsink组件只能运行一次的情况？我这边在T113平台上，第一次播放成功了，但是第二次运行的时候就不出图像了。我用fbdevsink也做过对比测试，fbdevsink就可以反复播放。

这是第一次播放时候的log：
root@(none):/# gst-launch-1.0 filesrc location=/mnt/vfat/album/video/2020BLACKPI
NK1280x480.mp4 ! decodebin3 ! sunxifbsink rotate-angle=3
-->sunxifbsink init.
Setting pipeline to PAUSED ...
dd: error writing '/dev/fb0': No space left on device
6406+0 records in
6405+0 records out
[  105.577056] VE: enable hw clock
[  105.582910] enable_cedar_hw_clk,552
Succesfully opened fbdev framebuffer device /dev/fb0, mapped sized 12.00 MB of which 10.95 MB (7 buffers) usable for page flipping.
fbdev phy=0x00000000,len=0x320a00,vir=0xb5a79000,size=0xc00000.
-->/dev/transform does not exist, hardware rotation is not supported.
-->reserver layer called (screen = 480 x 854).
-->Hardware overlay available.
Succesfully opened screen of pixel depth 32, dimensions 480 x 854, format BGRx, 12.00 MB video memory available, max 7 pannable screen buffers, vsync enabled.
Pipeline is PREROLLING ...
INFO   : cedarc <VeInitialize:1476>: *** ic_version = 0x1301000010210,
[  105.811615] VE: VE real_freq=576000000
[  105.811615]
INFO   : cedarc <VeRelease:1667>: not malloc locks

INFO   : cedarc <VeInitialize:1476>: *** ic_version = 0x1301000010210,
WARNING: omx_vdec <__AwOmxVdecSetParameter:1593>: Set Parameter called in valid state
ERROR  : omx_vdec <AwOmxVdecPortGetFormat:364>: erro: pParamData->nIndex > m_sPortFormatType.nIndex
WARNING: omx_vdec <__AwOmxVdecGetConfig:1667>: +++++ get display crop: top[0],left[0],width[1280],height[480]
WARNING: cedarc <AddVDPlugin:1614>: 1117 get local path: /usr/lib/
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_aacdec.so
---->sunxifb pre overlay(SCWxSCN=1280 x 480,out_rec=[0 187,480,480]).
Using one framebuffer plus 8 overlays in video memory (format YV12).
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_alacdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_amrdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_apedec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_atrcdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_dsddec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_flacdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624[  105.971969] VE: VE real_freq=576000000
[  105.971969]
>:  1117 load so: /usr/lib/libaw_g729dec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_mp3dec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_oggdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_opusdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_radec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_siprdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libaw_wavdec.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawh264.so
INFO   : cedarc <CedarPluginVDInit:80>: register h264 decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawh265.so
INFO   : cedarc <CedarPluginVDInit:85>: register h265 decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmjpeg.so
INFO   : cedarc <CedarPluginVDInit:84>: register mjpeg decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmpeg2.so
INFO   : cedarc <CedarPluginVDInit:86>: register mpeg2 decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmpeg4base.so
WARNING: cedarc <AddVDPluginSingle:1464>: Invalid plugin, CedarPluginVDInit not found.
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmpeg4dx.so
INFO   : cedarc <CedarPluginVDInit:98>: register mpeg4dx decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmpeg4h263.so
INFO   : cedarc <CedarPluginVDInit:79>: register mpeg4H263 decoder success!
WARNING: cedarc <AddVDPlugin:1624>:  1117 load so: /usr/lib/libawmpeg4normal.so
INFO   : cedarc <CedarPluginVDInit:90>: register mpeg4Normal decoder success!
INFO   : cedarc <log_set_level:71>: Set log level to 5 from /vendor/etc/cedarc.conf
ERROR  : cedarc <DebugCheckConfig:360>: now cedarc log level:5
WARNING: cedarc <InitializeVideoDecoder:668>: warning: the nDeInterlaceHoldingFrameBufferNum is 0
WARNING: cedarc <InitializeVideoDecoder:677>: warning: the nDisplayHoldingFrameBufferNum is 0
WARNING: omx_vdec <__AwOmxVdecGetConfig:1667>: +++++ get display crop: top[0],left[0],width[1280],height[480]
-->show_layer id (0).
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
New clock: GstSystemClock
Got EOS from element "pipeline0".
Execution ended after 0:00:20.060249177
Setting pipeline to NULL ...
482 frames rendered, 482 from system memory, 0 from video memory.
[  126.293057] L2 PageTable Invalid
[  126.302169] 0x23ae000 is not mapped!
[  126.306173] DE invalid address: 0x23ae000, data:0x0, id:0x4
-->sunxifbsink close.
-->sunxifbsink_hide_layer.
-->sunxifbsink_release_layer.
[  126.312479] L2 PageTable Invalid
[  126.323177] 0x2300000 is not mapped!
[  126.327179] DE invalid address: 0x2300000, data:0x0, id:0x4
[  126.333438] L2 PageTable Invalid
[  126.337049] 0x2300000 is not mapped!
[  126.341051] DE invalid address: 0x2300000, data:0x0, id:0x4
[  126.348407] VE: disable hw clock
[  126.352057] disable_cedar_hw_clk,592
Freeing pipeline ...

由错误日志
L2 PageTable Invalid
[   19.590243] 0x321000 is not mapped!
[   19.594130] DE invalid address: 0x321000, data:0x0, id:0x4

跟踪到了sunxi-iommu.c文件当中的
static irqreturn_t sunxi_iommu_irq(int irq, void *dev_id)
{

    u32 inter_status_reg = 0;
    u32 addr_reg = 0;
    u32    int_masterid_bitmap = 0;
    u32    data_reg = 0;
    u32    l1_pgint_reg = 0;
    u32    l2_pgint_reg = 0;
    u32    master_id = 0;
    unsigned long mflag;
    struct sunxi_iommu_dev *iommu = dev_id;

    spin_lock_irqsave(&iommu->iommu_lock, mflag);
    inter_status_reg = sunxi_iommu_read(iommu, IOMMU_INT_STA_REG) & 0x3ffff;
    l1_pgint_reg = sunxi_iommu_read(iommu, IOMMU_L1PG_INT_REG);
    l2_pgint_reg = sunxi_iommu_read(iommu, IOMMU_L2PG_INT_REG);
    int_masterid_bitmap = inter_status_reg | l1_pgint_reg | l2_pgint_reg;

    if (inter_status_reg & MICRO_TLB0_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[0]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG0);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG0);
    } else if (inter_status_reg & MICRO_TLB1_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[1]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG1);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG1);
    } else if (inter_status_reg & MICRO_TLB2_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[2]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG2);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG2);
    } else if (inter_status_reg & MICRO_TLB3_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[3]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG3);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG3);
    } else if (inter_status_reg & MICRO_TLB4_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[4]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG4);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG4);
    } else if (inter_status_reg & MICRO_TLB5_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[5]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG5);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG5);
    }
#if IS_ENABLED(CONFIG_ARCH_SUN8IW15) || IS_ENABLED(CONFIG_ARCH_SUN50IW9) \
    || IS_ENABLED(CONFIG_ARCH_SUN8IW19) || IS_ENABLED(CONFIG_ARCH_SUN50IW10) \
    || IS_ENABLED(CONFIG_ARCH_SUN8IW20) || IS_ENABLED(CONFIG_ARCH_SUN50IW12) \
    || IS_ENABLED(CONFIG_ARCH_SUN20IW1) || IS_ENABLED(CONFIG_ARCH_SUN55IW3)
    else if (inter_status_reg & MICRO_TLB6_INVALID_INTER_MASK) {
        pr_err("%s Invalid Authority\n", master[6]);
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG6);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG6);
    } else if (inter_status_reg & L1_PAGETABLE_INVALID_INTER_MASK) {
        /*It's OK to prefetch an invalid pagetable,no need to print msg for debug.*/
        if (!(int_masterid_bitmap & (1U << 31)))
            pr_err("L1 PageTable Invalid\n");
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG7);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG7);
    } else if (inter_status_reg & L2_PAGETABLE_INVALID_INTER_MASK) {
        if (!(int_masterid_bitmap & (1U << 31)))
            pr_err("L2 PageTable Invalid\n");
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG8);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG8);
    }
#else
    else if (inter_status_reg & L1_PAGETABLE_INVALID_INTER_MASK) {
        pr_err("L1 PageTable Invalid\n");
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG6);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG6);
    } else if (inter_status_reg & L2_PAGETABLE_INVALID_INTER_MASK) {
        pr_err("L2 PageTable Invalid\n");
        addr_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG7);
        data_reg = sunxi_iommu_read(iommu, IOMMU_INT_ERR_DATA_REG7);
    }
#endif
    else
        pr_err("sunxi iommu int error!!!\n");

    if (!(int_masterid_bitmap & (1U << 31))) {
        if (sunxi_iova_invalid_helper(addr_reg)) {
            int_masterid_bitmap &= 0xffff;
            master_id = __ffs(int_masterid_bitmap);
        }
        pr_err("%s invalid address: 0x%x, data:0x%x, id:0x%x\n",
            master[master_id], addr_reg, data_reg,
                int_masterid_bitmap);
    }

#if IS_ENABLED(CONFIG_ARCH_SUN8IW19) || IS_ENABLED(CONFIG_ARCH_SUN50IW9) \
    || IS_ENABLED(CONFIG_ARCH_SUN50IW10)
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_START_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_END_ADDR_REG, addr_reg + 4 * SPAGE_SIZE);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_TLB_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_PC_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG,
        addr_reg + 0x200000);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_PC_IVLD_ENABLE_REG) & 0x1)
        ;
#elif IS_ENABLED(CONFIG_ARCH_SUN8IW20) || IS_ENABLED(CONFIG_ARCH_SUN50IW12) \
    || IS_ENABLED(CONFIG_ARCH_SUN20IW1) || IS_ENABLED(CONFIG_ARCH_SUN55IW3)
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_START_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_END_ADDR_REG, addr_reg + 4 * SPAGE_SIZE);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_TLB_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_START_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_END_ADDR_REG, addr_reg + 2 * SPD_SIZE);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_PC_IVLD_ENABLE_REG) & 0x1)
        ;
#else
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_MASK_REG,
        (u32)IOMMU_PT_MASK);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_TLB_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_REG,
        addr_reg + 0x2000);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_MASK_REG,
        (u32)IOMMU_PT_MASK);
    sunxi_iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_TLB_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG, addr_reg);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_PC_IVLD_ENABLE_REG) & 0x1)
        ;
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG,
        addr_reg + 0x200000);
    sunxi_iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, 0x1);
    while (sunxi_iommu_read(iommu, IOMMU_PC_IVLD_ENABLE_REG) & 0x1)
        ;
#endif

    sunxi_iommu_write(iommu, IOMMU_INT_CLR_REG, inter_status_reg);
    inter_status_reg |= (l1_pgint_reg | l2_pgint_reg);
    inter_status_reg &= 0xffff;
    sunxi_iommu_write(iommu, IOMMU_RESET_REG, ~inter_status_reg);
    sunxi_iommu_write(iommu, IOMMU_RESET_REG, 0xffffffff);
    spin_unlock_irqrestore(&iommu->iommu_lock, mflag);

    return IRQ_HANDLED;
}

感觉内存还没有映射好。也就是初始化的问题。

通过ioctl函数传递的图层参数，framebuffer地址（即上面的config.info.fb.addr[0]）到底是物理地址还是虚拟地址？这个framebuffer由应用层提供，有没有什么特别要求？比如地址对齐要求、连续内存要求等等。另外哪里能找到有关的说明文档或者参考代码？

楼主你的rootfs启动就有一个dhcpcd进程，定时查找dhcp server。在哪里可以禁止这个进程？我的环境上不需要网络通信。dropbear我也不需要。

@司徒
给楼主点个赞。楼主是个热心人。当初我点屏遇到问题的时候，他曾好心相助。
祝你在开源领域继续纵横驰骋！

楼主的硬件转RGB搞定了吗？我现在用widora tiny200 R3,采用了aodzip大佬的 buildroot一键生成生成的image可以用modetest做四层叠加，但是只能支持RGB格式的图像，如果是yuv格式的图像，则会显示成全绿色。有没有什么线索在主线drm中使用这个硬件转码功能？ @晕哥 有线索吗？

@晕哥
楼主，我用licheepi zero（V3S）。在主线5.19.3的内核中尝试初始化LCD的时候，也遇到了fb0设备不出现的问题。
按照你的方法打印了drm的初始化log

[    0.056344] [drm:0xc070eda1] Initialized
[    0.056506] [drm:0xc02a4577] Adding component /soc/mixer@1100000
[    0.056609] [drm:0xc02a4577] Adding component /soc/lcd-controller@1c0c000
[    0.056676] [drm:0xc02a43ff] Endpoint is our panel... skipping
[    0.060684] panel-simple panel: supply power not found, using dummy regulator
[    0.060947] panel-simple panel: Specify missing connector_type

能帮着分析一下是什么原因导致的吗？还是说V3S DE设备的初始化只能在v5.2内核版本下工作？
吊诡的是，panel设备不出现，对应的backlight设备也没有出现在设备树当中。

我用的dts文件是参照licheepi zero官方的修改而来，官方的内核版本是v5.2

[	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 0 1000000 0>;
		brightness-levels = <0 30 40 50 60 70 100>;
		default-brightness-level = <6>;
	};

	panel: panel {
		compatible = "urt,umsh-8596md-t", "simple-panel";
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			backlight = <&backlight>;
			#address-cells = <1>;
			#size-cells = <0>;

			panel_input: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&tcon0_out_lcd>;
			};
		};
	};
&de {
	status = "okay";
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_pins>;
	status = "okay";
};

&tcon0 {
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_rgb666_pins_a>;
	status = "okay";
};

&tcon0_out {
	tcon0_out_lcd: endpoint@0 {
		reg = <0>;
		remote-endpoint = <&panel_input>;
	};
};
]

官方的v5.2版本，fb设备初始化成功的时候，还有下面的打印信息，我这边就没有

[
[    1.259771] sun8i-v3s-pinctrl 1c20800.pinctrl: 1c20800.pinctrl supply vcc-pe                                                    not found, using dummy regulator
[    1.272296] sun4i-drm display-engine: bound 1100000.mixer (ops 0xc0773d40)
[    1.279881] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops 0xc07                                                   7103c)
[    1.287569] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    1.294258] [drm] No driver support for vblank timestamp query.
[    1.301264] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on  
]

这个屏还没有调出来。现在在查RGB口，对比时序发现有个问题。卖家开发板HSYNC和VSYNC信号之间似乎有个相位差，大概32个时钟左右。而通常mpu的lcd控制器，HSYNC和VSYNC是完全同步的。请问会是这个问题吗？R61529驱动，是不是哪里可以设置这个相位差？

我选取了set_address_mode 0x36 寄存器测试，每次写入以后用get_address_mode 0x0B 寄存器读回。

发现写入0x6A，读回是0x68；
写入0x08，读回是0x08。
是不是可以认定写入基本是成功了？

@哇酷小二
试过了大佬的代码，还是黑屏。csx在整个初始化期间都是拉低的。

@memory
这是我们的初始化代码，可以看到读device id都是成功的，就是代码中的byte1和byte2。感觉spi口时序已经对了。

{	
	unsigned char byte1,byte2;
	
	/* Initialize the pins */
	if (r61408_enable_gpio(cfg) != 0)
		return ;

	gpio_set_value(cfg->csx_pin, 1);
	mdelay(20);
	gpio_set_value(cfg->csx_pin, 0);
	gpio_set_value(cfg->reset_pin, 0);
	mdelay(200);
	gpio_set_value(cfg->reset_pin, 1);
	mdelay(200);

#if 1
	// Enter read mode
	SPI_WriteComm(0xB0);
	SPI_WriteData(0x04);

	SPI_WriteComm(0xBF);
	SPI_ReadData();

	printf("DDB0=%x, DDB1=%x\n", SPI_ReadData(), SPI_ReadData());
	byte1 = SPI_ReadData();
	byte2 = SPI_ReadData();

	// Enter read mode
	SPI_WriteComm(0xB0);
	SPI_WriteData(0x04);
			
  if (byte1==0x15 && byte2==0x29) {
  	printf("R61259 found!\n");
		r61529_Reg_Fill();

  }

	gpio_set_value(cfg->csx_pin, 1);  	
		  	
#else 
#endif

}

static void r61529_Reg_Fill(void)
{
	SPI_WriteComm(0xB4);
	SPI_WriteData(0x00);
	
	SPI_WriteComm(0xB0);
	SPI_WriteData(0x04);

	SPI_WriteComm(0x20);
	
	SPI_WriteComm(0x36); //Set_address_mode
 	SPI_WriteData(0x6A); //
	SPI_WriteComm(0x3A); 
	SPI_WriteData(0x77);
	
	SPI_WriteComm(0xB3);
	SPI_WriteData(0x02);
	SPI_WriteData(0x00);
	SPI_WriteData(0x00);
	SPI_WriteData(0x20);
	
	
	
	SPI_WriteComm(0xc0);
	SPI_WriteData(0x03);
	SPI_WriteData(0xdf);
	SPI_WriteData(0x40);
	SPI_WriteData(0x12);
	SPI_WriteData(0x00);
	SPI_WriteData(0x01);
	SPI_WriteData(0x00);
	SPI_WriteData(0x55);// 
	
	SPI_WriteComm(0xc1);
	SPI_WriteData(0x07);
	SPI_WriteData(0x28);
	SPI_WriteData(0x08);// 
	SPI_WriteData(0x08);//
	SPI_WriteData(0x00);//
	
	SPI_WriteComm(0xc4);
	SPI_WriteData(0x70);//
	SPI_WriteData(0x00);
	SPI_WriteData(0x03);
	SPI_WriteData(0x01);
	
	SPI_WriteComm(0xc6);
	SPI_WriteData(0x1d);//1d
	
	SPI_WriteComm(0xc8);
	SPI_WriteData(0x06);
	SPI_WriteData(0x0c);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3d);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0c);
	SPI_WriteData(0x04);
	SPI_WriteData(0x06);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3D);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x04);
	
	SPI_WriteComm(0xC9);
	SPI_WriteData(0x06);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3D);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x04);	
	SPI_WriteData(0x06);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3D);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x04);
	
	SPI_WriteComm(0xCA);
	SPI_WriteData(0x06);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3D);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x04);	
	SPI_WriteData(0x06);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x16);
	SPI_WriteData(0x24);
	SPI_WriteData(0x30);
	SPI_WriteData(0x48);
	SPI_WriteData(0x3D);
	SPI_WriteData(0x28);
	SPI_WriteData(0x20);
	SPI_WriteData(0x14);
	SPI_WriteData(0x0C);
	SPI_WriteData(0x04);
	
	SPI_WriteComm(0xD0);
	SPI_WriteData(0x95);
	SPI_WriteData(0x0A);
	SPI_WriteData(0x08);
	SPI_WriteData(0x10);
	SPI_WriteData(0x39);
	
	SPI_WriteComm(0xD1);
	SPI_WriteData(0x02);
	SPI_WriteData(0x2c);//
	SPI_WriteData(0x2c);//
	SPI_WriteData(0x44);//	
	SPI_WriteData(0x00);//0x08 
	
	SPI_WriteComm(0x11);
	mdelay(100);
	SPI_WriteComm(0x29);
	mdelay(100);
	SPI_WriteComm(0x2C);
		
	SPI_WriteComm(0x36);
#if LCD_RGB_ORIENTATION //
 SPI_WriteData(0x09);
#else
 SPI_WriteData(0x08);
#endif
	
}

现在和他们协商，想买一套他们的开发板，带3.5寸屏，要求他们烧好支持RGB888模式的固件。这样我们调试的时候可以对比测试。
还不知道他们能不能做到。

谢谢版主！