楼主 #1 2020-11-10 16:04:45 分享评论
- hanzixi_angel
- 会员
- 注册时间： 2020-09-21
- 已发帖子： 54
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关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
最近更换了一块高亮屏 其实参数都一样 但是运行起来屏幕出现抖动的现象 很明显 uboot中显示正常 一旦进入内核就会出现画面抖动; 换了其他的屏幕就正常 推测应该是参数不匹配的问题 然后修改设备树和驱动 使用sun8i-v3s-licheepi-zero-with-800x480-lcd.dts的设备树 启用了display-engine功能 但是测试发现仍然抖动 根据设备树找到了内核的屏幕参数 更改参数仍然抖动 最终没有办法用示波器测量时钟 发现屏幕的时钟变成了24M-25M 跟晶振频率基本一致 在uboot中的频率是33M 这就导致屏幕出现抖动 在驱动中修改屏幕的之中频率 时钟无法超过24M 推测就是设备树时钟的限制 但是参看设备树 找不到如何修改设备树时钟相关的参数 设备树文件内容如下
sun8i-v3s.tdsi
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
simplefb_lcd: framebuffer@0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de0-lcd0";
clocks = <&ccu CLK_BUS_TCON0>, <&display_clocks 0>,
<&display_clocks 6>, <&ccu CLK_TCON0>;
status = "disabled";
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_CPU>;
};
};
de: display-engine {
compatible = "allwinner,sun8i-v3s-display-engine";
allwinner,pipelines = <&mixer0>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-v3s-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-v3s-de2-mixer";
reg = <0x01100000 0x100000>;
clocks = <&display_clocks 0>,
<&display_clocks 6>;
clock-names = "bus",
"mod";
resets = <&display_clocks 0>;
assigned-clocks = <&display_clocks 6>;
assigned-clock-rates = <150000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_mixer0>;
};
};
};
};
/*
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-v3s-system-controller",
"syscon";
reg = <0x01c00000 0x1000>;
};
*/
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-v3s-system-controller", "allwinner,sun8i-h3-system-control", "syscon";
reg = <0x01c00000 0xd0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0x80000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-v3s-sram-c", "allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
cedarx: video-codec@1c0e000 {
compatible = "allwinner,sun8i-v3-cedar";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_VE>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
//status = "disabled";
status = "okay";
};
ion: ion {
compatible = "allwinner,sunxi-ion";
//status = "disabled";
status = "okay";
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
};
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>,
<&ccu CLK_TCON0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
reg = <0>;
tcon0_in_mixer0: endpoint {
remote-endpoint = <&mixer0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-v3s-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
<&ccu CLK_MMC2>,
<&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@1c19400 {
compatible = "allwinner,sun8i-v3s-usb-phy";
reg = <0x01c19400 0x2c>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
status = "disabled";
};
ohci0: usb@01c1a400 {
compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
status = "disabled";
};
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@1c20400 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01c20400 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-v3s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
emac_rgmii_pins: emac-rgmii-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10",
"PD12", "PD13", "PD15", "PD16", "PD17";
function = "emac";
drive-strength = <40>;
};
i2c0_pins: i2c0-pins {
pins = "PB6", "PB7";
function = "i2c0";
};
pwm0_pins: pwm0 {
pins = "PB4";
function = "pwm0";
};
uart0_pb_pins: uart0-pb-pins {
pins = "PB8", "PB9";
function = "uart0";
};
lcd_rgb666_pins_a: lcd-rgb666-pe {
pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10", "PE11",
"PE12", "PE13", "PE14", "PE15", "PE16", "PE17",
"PE18", "PE19", "PE23", "PE24";
function = "lcd";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
spi0_pins: spi0-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
pwm: pwm@1c21400 {
compatible = "allwinner,sun8i-v3s-pwm",
"allwinner,sun7i-a20-pwm";
reg = <0x01c21400 0x400>;
clocks = <&osc24M>;
#pwm-cells = <3>;
status = "disabled";
};
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x400>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
codec: codec@01c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-v3s-codec";
reg = <0x01c22c00 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
clock-names = "apb", "codec";
resets = <&ccu RST_BUS_CODEC>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
allwinner,codec-analog-controls = <&codec_analog>;
status = "disabled";
};
codec_analog: codec-analog@01c23000 {
compatible = "allwinner,sun8i-v3s-codec-analog";
reg = <0x01c23000 0x4>;
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio-mux {
compatible = "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
/* Only one MDIO is usable at the time */
internal_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
external_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
};sun8i-v3s-licheepi-zero-with-lcd.tdsi
/*
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR X11)
*/
#include "sun8i-v3s-licheepi-zero.dts"
/ {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 30 40 50 60 70 100>;
default-brightness-level = <6>;
};
panel: panel {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_lcd>;
};
};
};
};
&de {
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>;
status = "okay";
};
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins_a>;
status = "okay";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};sun8i-v3s-licheepi-zero-with-800x480-lcd.dts
/*
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR X11)
*/
#include "sun8i-v3s-licheepi-zero-with-lcd.dtsi"
&panel {
compatible = "urt,umsh-8596md-t", "simple-panel";
};本人是新手 关于时钟配置不是很精通 希望各位大牛不吝赐教
离线
楼主 #3 2020-11-10 16:37:25 分享评论
- hanzixi_angel
- 会员
- 注册时间： 2020-09-21
- 已发帖子： 54
- 积分： 35.5
Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
哇酷小二 说：
用 sun8i-v3s-licheepi-zero.dts 这个dts呢?
你上面的dts可能用drm驱动的，而不是simplefb
使用simplefb也一样 时钟被降低到25M 我测试发现屏蔽sun8i-v3s.dtsi中de相关的配置就可以了 不会被降低时钟了 去掉了display_clocks /mixer0和tcon0的配置 但是如果使用de改如何配置时钟呢?
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楼主 #4 2020-11-11 09:48:59 分享评论
- hanzixi_angel
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-v3s-de2-mixer";
reg = <0x01100000 0x100000>;
clocks = <&display_clocks 0>,
<&display_clocks 6>;
clock-names = "bus",
"mod";
resets = <&display_clocks 0>;
assigned-clocks = <&display_clocks 6>;
//assigned-clock-rates = <150000000>;
assigned-clock-rates = <200000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_mixer0>;
};
};
};
};经过查看设备树以及对比测试发现 lcd的时钟被降到25Mhz 发现正好是mixer0中时钟频率150M的6分频 然后将assigned-clock-rates的150M改为200M之后解决 测量发现时钟正好是33.3M 正好符合7寸屏的时钟需求 大家如果使用de驱动液晶屏的话如果出现屏幕抖动的问题可以参考下
最近编辑记录 hanzixi_angel (2020-11-11 09:49:20)
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#5 2020-11-11 09:52:41 分享评论
- 孤星泪
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
楼主研究精神可嘉
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楼主 #6 2020-11-11 10:13:19 分享评论
- hanzixi_angel
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
孤星泪 说：
楼主研究精神可嘉
踩坑嘛 没有办法 
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#7 2020-11-19 00:40:21 分享评论
- wupaul2001
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
不用搞了，直接换新的内核，虽然我知道是那里问题，根本问题不在设备树
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#8 2020-11-19 07:25:33 分享评论
- raspberryman
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
wupaul2001 说：
不用搞了，直接换新的内核，虽然我知道是那里问题，根本问题不在设备树
请教用哪个版本? Linux5.9?
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楼主 #9 2020-11-19 19:08:52 分享评论
- hanzixi_angel
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
wupaul2001 说：
不用搞了，直接换新的内核，虽然我知道是那里问题，根本问题不在设备树
根本问题在哪 能指点一二吗 使用哪个内核?
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#10 2020-11-24 18:10:39 分享评论
- wupaul2001
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
我使用5,2的内核
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#11 2020-11-24 18:13:15 分享评论
- wupaul2001
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
不想换内核的话。修改/drivers/gpu/drm/sun4i/sun4i_tcon.c
-tcon->dclk_min_div = 6;
+tcon->dclk_min_div = 1;
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楼主 #12 2020-11-25 15:20:20 分享评论
- hanzixi_angel
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
wupaul2001 说：
我使用5,2的内核
我使用的也是5.2的内核 您是从那个地址clone的?
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楼主 #13 2020-11-25 15:20:50 分享评论
- hanzixi_angel
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
wupaul2001 说：
不想换内核的话。修改/drivers/gpu/drm/sun4i/sun4i_tcon.c
-tcon->dclk_min_div = 6;
+tcon->dclk_min_div = 1;
这个就是分频设置了吧
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#14 2020-11-27 15:20:07 分享评论
- wupaul2001
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
hanzixi_angel 说：
wupaul2001 说：我使用5,2的内核
我使用的也是5.2的内核 您是从那个地址clone的?
主线clone的
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#15 2020-11-27 15:20:51 分享评论
- wupaul2001
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
hanzixi_angel 说：
wupaul2001 说：不想换内核的话。修改/drivers/gpu/drm/sun4i/sun4i_tcon.c
-tcon->dclk_min_div = 6;
+tcon->dclk_min_div = 1;
这个就是分频设置了吧
解决最小分频限制
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#16 2020-12-17 17:17:43 分享评论
- b7376811
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
mark 一下
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#17 2022-09-06 02:41:11 分享评论
- iamseer
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Re: 关于V3s display-engine/display_clocks /mixer0和tcon0 有关lcd时钟配置的一些问题
我也遇到了类似问题，帧率想要60.却只有40.
检查的手册发现24M主时钟通过PLL_VIDEO_CTRL_REG配置到PLL_VIDEO频率，再通过TCON_CLK_REG降低到指定屏幕PCLK频率。PLL参数内核会自动设置，但是PLL_VIDEO频率需要指定。
不知道是不是我打的补丁冲突原因，assigned-clock-rates = <200000000>;不起作用。修改 sun8i_mixer.c 里对应板子的 .mod_rate 可行。
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