WhyCan Forum(哇酷开发者社区)

Administrator@PC-20170510YOBI MINGW64 /f/fff/l
$ "D:\Downloads\sunxi-tools-win32support_f1c100s_v3s_201812219\V3s\sunxi-fel.exe                                                                              " -p spiflash-info
ERROR: Allwinner USB FEL device not found!

Administrator@PC-20170510YOBI MINGW64 /f/fff/l
$ "D:\Downloads\sunxi-tools-win32support_f1c100s_v3s_201812219\V3s\sunxi-fel.exe                                                                              " -p spiflash-info
Manufacturer: Unknown (20h), model: BAh, size: 16777216 bytes.

Administrator@PC-20170510YOBI MINGW64 /f/fff/l
$ "D:\Downloads\sunxi-tools-win32support_f1c100s_v3s_201812219\V3s\sunxi-fel.exe" -p spiflash-read 0 16777216 read1.bin
100% [================================================] 16777 kB,   95.6 kB/s

Administrator@PC-20170510YOBI MINGW64 /f/fff/l
$ "D:\Downloads\sunxi-tools-win32support_f1c100s_v3s_201812219\V3s\sunxi-fel.exe" -p spiflash-read 0 16777216 read2.bin
100% [================================================] 16777 kB,   89.7 kB/s

// SPDX-License-Identifier: GPL-2.0
/*
 * gc0403 driver
 *
 * Copyright (C) 2019 Fuzhou Rockchip Electronics Co.,Ltd.
 * V0.0X01.0X02 add enum_frame_interval function.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/sysfs.h>
#include <media/media-entity.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include <linux/rk-camera-module.h>

/*
 * GC0403 register definitions
 */
#define GC0403_REG_EXP_H		0x03
#define GC0403_REG_EXP_L		0x04
#define GC0403_REG_VBLK_H		0x07
#define GC0403_REG_VBLK_L		0x08
#define GC0403_REG_MIPI_EN		0x10
#define GC0403_REG_DGAIN_H		0xb1
#define GC0403_REG_DGAIN_L		0xb2
#define GC0403_REG_AGAIN		0xb6
#define GC0403_REG_CHIP_ID_H		0xf0
#define GC0403_REG_CHIP_ID_L		0xf1
#define PAGE_SELECT_REG			0xfe
#define REG_NULL			0xff

#define GC0403_CHIP_ID			0x0403
#define SENSOR_ID(_msb, _lsb)	((_msb) << 8 | (_lsb))

#define GC0403_ANALOG_GAIN_MIN		0
#define GC0403_ANALOG_GAIN_MAX		0x0a
#define GC0403_ANALOG_GAIN_STP		1
#define GC0403_ANALOG_GAIN_DFT		1
/* gain[4:0]  [0x00,0x0a]*/
#define GC0403_FETCH_ANALOG_GAIN(VAL) ((VAL) & 0x0F)

#ifndef V4L2_CID_DIGITAL_GAIN
#define V4L2_CID_DIGITAL_GAIN	V4L2_CID_GAIN
#endif

#define GC0403_DIGI_GAIN_MIN		0x40
#define GC0403_DIGI_GAIN_MAX		0x3ff
#define GC0403_DIGI_GAIN_STP		1
#define GC0403_DIGI_GAIN_DFT		0x40
/* gain[9:6] */
#define GC0403_FETCH_DIGITAL_GAIN_HIGH(VAL) (((VAL) >> 6) & 0x0F)
/* gain[5:0] */
#define GC0403_FETCH_DIGITAL_GAIN_LOW(VAL) (((VAL) << 2) & 0xFC)

#define GC0403_TOTAL_GAIN_MIN		100
#define GC0403_TOTAL_GAIN_MAX		3200
#define GC0403_TOTAL_GAIN_STEP		1

#define GC0403_EXPOSURE_MAX		8191
#define GC0403_EXPOSURE_MIN		1

#define GC0403_NAME			"gc0403"
#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x02)

#define GC0403_XVCLK_FREQ		24000000
#define GC0403_LINK_FREQ		96000000
#define GC0403_PIXEL_RATE		(GC0403_LINK_FREQ * 2 * 1 / 10)

static const s64 link_freq_menu_items[] = {
	GC0403_LINK_FREQ
};

static const char * const gc0403_supply_names[] = {
	"dovdd",	/* Digital I/O power */
	"avdd",		/* Analog power */
};

#define GC0403_NUM_SUPPLIES	ARRAY_SIZE(gc0403_supply_names)

struct regval {
	u8 addr;
	u8 val;
};

struct gc0403_mode {
	u32 width;
	u32 height;
	struct v4l2_fract max_fps;
	u32 hts_def;
	u32 vts_def;
	u32 exp_def;
	const struct regval *reg_list;
};

struct gc0403 {
	struct i2c_client	*client;
	struct clk		*xvclk;
	struct gpio_desc	*pwdn_gpio;
	struct regulator_bulk_data supplies[GC0403_NUM_SUPPLIES];

	struct v4l2_subdev	subdev;
	struct media_pad	pad;
	struct v4l2_ctrl_handler ctrl_handler;
	struct v4l2_ctrl	*exposure;
	struct v4l2_ctrl	*anal_gain;
	struct v4l2_ctrl	*digi_gain;
	struct v4l2_ctrl	*hblank;
	struct v4l2_ctrl	*vblank;
	/* mutex lock, protect current operation */
	struct mutex		mutex;
	bool			streaming;
	const struct gc0403_mode *cur_mode;
	u32			module_index;
	const char		*module_facing;
	const char		*module_name;
	const char		*len_name;
};

#define to_gc0403(sd) container_of(sd, struct gc0403, subdev)

/*
 * MCLK=24Mhz
 * MIPI_CLOCK=192Mbps
 * Actual_window_size=640*480
 * HD=1362
 * VD=586
 * row_time=56.75us,FPS = 30fps;
 */
static const struct regval gc0403_vga_regs[] = {
	/****SYS****/
	{0xfe, 0x80},
	{0xfe, 0x80},
	{0xfe, 0x80},
	{0xf2, 0x00},	/* sync_pad_io_ebi */
	{0xf6, 0x00},	/*up down */
	{0xfc, 0xc6},
	{0xf7, 0x19},	/* pll enable */
	{0xf8, 0x01},	/* Pll mode 2 */
	{0xf9, 0x3e},	/* [0] pll enable solve IOVDD large current problem */
	{0xfe, 0x03},
	{0x06, 0x80},
	{0x06, 0x00},
	{0xfe, 0x00},
	{0xf9, 0x2e},
	{0xfe, 0x00},
	{0xfa, 0x00},	/* div */
	{0xfe, 0x00},
	/**ANALOG&CISCTL**/
	{0x03, 0x02},
	{0x04, 0x55},
	{0x05, 0x01},	/* H blank */
	{0x06, 0x49},	/* H blank=bb=187 */
	{0x07, 0x00},	/* VB */
	{0x08, 0x5a},	/* VB=E8=232 */
	{0x09, 0x00},
	{0x0a, 0x2c},
	{0x0b, 0x00},
	{0x0c, 0x3c},
	{0x0d, 0x01},	/* win_height */
	{0x0e, 0xf0},	/* 496 */
	{0x0f, 0x02},	/* win_width */
	{0x10, 0x90},	/* 656 */
	{0x11, 0x23},	/* 44FPN abnormal column */
	{0x12, 0x10},
	{0x13, 0x11},
	{0x14, 0x01},
	{0x15, 0x00},
	{0x16, 0xc0},
	{0x17, 0x14},
	{0x18, 0x02},
	{0x19, 0x38},
	{0x1a, 0x11},
	{0x1b, 0x06},
	{0x1c, 0x04},
	{0x1d, 0x00},
	{0x1e, 0xfc},
	{0x1f, 0x09},
	{0x20, 0xb5},
	{0x21, 0x3f},
	{0x22, 0xe6},
	{0x23, 0x32},
	{0x24, 0x2f},
	{0x27, 0x00},
	{0x28, 0x00},
	{0x2a, 0x00},
	{0x2b, 0x00},
	{0x2c, 0x00},
	{0x2d, 0x01},
	{0x2e, 0xf0},
	{0x2f, 0x01},
	{0x25, 0xc0},
	{0x3d, 0xe0},
	{0x3e, 0x45},
	{0x3f, 0x1f},
	{0xc2, 0x17},
	{0x30, 0x22},
	{0x31, 0x23},
	{0x32, 0x02},
	{0x33, 0x03},
	{0x34, 0x04},
	{0x35, 0x05},
	{0x36, 0x06},
	{0x37, 0x07},
	{0x38, 0x0f},
	{0x39, 0x17},
	{0x3a, 0x1f},
	/****ISP****/
	{0xfe, 0x00},
	{0x8a, 0x00},
	{0x8c, 0x07},
	{0x8e, 0x02},	/* luma value not normal */
	{0x90, 0x01},
	{0x94, 0x02},
	{0x95, 0x01},
	{0x96, 0xe0},	/* 480 */
	{0x97, 0x02},
	{0x98, 0x80},	/* 640 */
	/****BLK****/
	{0xfe, 0x00},
	{0x18, 0x02},
	{0x40, 0x22},
	{0x41, 0x01},
	{0x5e, 0x00},
	{0x66, 0x20},
	/****MIPI****/
	{0xfe, 0x03},
	{0x01, 0x83},
	{0x02, 0x11},
	{0x03, 0x96},
	{0x04, 0x01},
	{0x05, 0x00},
	{0x06, 0xa4},
	{0x10, 0x90},
	{0x11, 0x2b},
	{0x12, 0x20},
	{0x13, 0x03},
	{0x15, 0x00},
	{0x21, 0x10},
	{0x22, 0x03},
	{0x23, 0x20},
	{0x24, 0x02},
	{0x25, 0x10},
	{0x26, 0x05},
	{0x21, 0x10},
	{0x29, 0x03},
	{0x2a, 0x0a},
	{0x2b, 0x04},
	{0xfe, 0x00},
	{0xb0, 0x50},
	{0xb6, 0x09},
	{REG_NULL, 0x00},
};

/*
 * MCLK=24Mhz
 * MIPI_CLOCK=192Mbps
 * Actual_window_size=768*576
 * HD=1206
 * VD=663
 * row_time=50.25us,FPS = 30fps;
 */
static const struct regval gc0403_768x576_regs[] = {
	/****SYS****/
	{0xfe, 0x80},
	{0xfe, 0x80},
	{0xfe, 0x80},
	{0xf2, 0x00},	/* sync_pad_io_ebi */
	{0xf6, 0x00},	/* up down */
	{0xfc, 0xc6},
	{0xf7, 0x19},	/* pll enable */
	{0xf8, 0x01},	/* Pll mode 2 */
	{0xf9, 0x3e},	/* [0] pll enable solve IOVDD large current problem */
	{0xfe, 0x03},
	{0x06, 0x80},
	{0x06, 0x00},
	{0xfe, 0x00},
	{0xf9, 0x2e},
	{0xfe, 0x00},
	{0xfa, 0x00},	/* div */
	{0xfe, 0x00},
	/**ANALOG&CISCTL**/
	{0x03, 0x02},
	{0x04, 0x55},
	{0x05, 0x00},	/* H blank */
	{0x06, 0xbb},	/* H blank=bb=187 */
	{0x07, 0x00},	/* VB */
	{0x08, 0x46},	/* VB=E8=232 */
	{0x0c, 0x04},
	{0x0d, 0x02},	/* win_height */
	{0x0e, 0x48},	/* 584 */
	{0x0f, 0x03},	/* win_width */
	{0x10, 0x08},	/* 776 */
	{0x11, 0x23},	/* 44FPN abnormal column */
	{0x12, 0x10},
	{0x13, 0x11},
	{0x14, 0x01},
	{0x15, 0x00},
	{0x16, 0xc0},
	{0x17, 0x14},
	{0x18, 0x02},
	{0x19, 0x38},
	{0x1a, 0x11},
	{0x1b, 0x06},
	{0x1c, 0x04},
	{0x1d, 0x00},
	{0x1e, 0xfc},
	{0x1f, 0x09},
	{0x20, 0xb5},
	{0x21, 0x3f},
	{0x22, 0xe6},
	{0x23, 0x32},
	{0x24, 0x2f},
	{0x27, 0x00},
	{0x28, 0x00},
	{0x2a, 0x00},
	{0x2b, 0x00},
	{0x2c, 0x00},
	{0x2d, 0x01},
	{0x2e, 0xf0},
	{0x2f, 0x01},
	{0x25, 0xc0},
	{0x3d, 0xe0},
	{0x3e, 0x45},
	{0x3f, 0x1f},
	{0xc2, 0x17},
	{0x30, 0x22},
	{0x31, 0x23},
	{0x32, 0x02},
	{0x33, 0x03},
	{0x34, 0x04},
	{0x35, 0x05},
	{0x36, 0x06},
	{0x37, 0x07},
	{0x38, 0x0f},
	{0x39, 0x17},
	{0x3a, 0x1f},
	/****ISP****/
	{0xfe, 0x00},
	{0x8a, 0x00},
	{0x8c, 0x07},
	{0x8e, 0x02},	/* luma value not normal */
	{0x90, 0x01},
	{0x94, 0x02},
	{0x95, 0x02},
	{0x96, 0x40},	/* 576 */
	{0x97, 0x03},
	{0x98, 0x00},	/* 768 */
	/****BLK****/
	{0xfe, 0x00},
	{0x18, 0x02},
	{0x40, 0x22},
	{0x41, 0x01},
	{0x5e, 0x00},
	{0x66, 0x20},
	/****MIPI****/
	{0xfe, 0x03},
	{0x01, 0x83},
	{0x02, 0x11},
	{0x03, 0x96},
	{0x04, 0x01},
	{0x05, 0x00},
	{0x06, 0xa4},
	{0x10, 0x80},
	{0x11, 0x2b},
	{0x12, 0xc0},
	{0x13, 0x03},
	{0x15, 0x00},
	{0x21, 0x10},
	{0x22, 0x03},
	{0x23, 0x20},
	{0x24, 0x02},
	{0x25, 0x10},
	{0x26, 0x05},
	{0x21, 0x10},
	{0x29, 0x01},
	{0x2a, 0x0a},
	{0x2b, 0x04},
	{0xfe, 0x00},
	{0xb0, 0x50},
	{0xb6, 0x01},
	{REG_NULL, 0x00},
};

static const struct gc0403_mode supported_modes[] = {
	{
		.width = 640,
		.height = 480,
		.max_fps = {
			.numerator = 10000,
			.denominator = 300000,
		},
		.exp_def = 500,
		.hts_def = 1362,
		.vts_def = 586,
		.reg_list = gc0403_vga_regs,
	},
	{
		.width = 768,
		.height = 576,
		.max_fps = {
			.numerator = 10000,
			.denominator = 300000,
		},
		.exp_def = 500,
		.hts_def = 1206,
		.vts_def = 663,
		.reg_list = gc0403_768x576_regs,
	}
};

/* sensor register write */
static int gc0403_write_reg(struct i2c_client *client, u8 reg, u8 val)
{
	struct i2c_msg msg;
	u8 buf[2];
	int ret;

	buf[0] = reg & 0xFF;
	buf[1] = val;

	msg.addr = client->addr;
	msg.flags = client->flags;
	msg.buf = buf;
	msg.len = sizeof(buf);

	ret = i2c_transfer(client->adapter, &msg, 1);
	if (ret >= 0)
		return 0;

	dev_err(&client->dev,
		"gc0403 write reg(0x%x val:0x%x) failed !\n", reg, val);

	return ret;
}

static int gc0403_write_array(struct i2c_client *client,
			      const struct regval *regs)
{
	int i, ret = 0;

	i = 0;
	while (regs[i].addr != REG_NULL) {
		ret = gc0403_write_reg(client, regs[i].addr, regs[i].val);
		if (ret) {
			dev_err(&client->dev, "%s failed !\n", __func__);
			break;
		}
		i++;
	}

	return ret;
}

/* sensor register read */
static int gc0403_read_reg(struct i2c_client *client, u8 reg, u8 *val)
{
	struct i2c_msg msg[2];
	u8 buf[1];
	int ret;

	buf[0] = reg & 0xFF;

	msg[0].addr = client->addr;
	msg[0].flags = client->flags;
	msg[0].buf = buf;
	msg[0].len = sizeof(buf);

	msg[1].addr = client->addr;
	msg[1].flags = client->flags | I2C_M_RD;
	msg[1].buf = buf;
	msg[1].len = 1;

	ret = i2c_transfer(client->adapter, msg, 2);
	if (ret >= 0) {
		*val = buf[0];
		return 0;
	}

	dev_err(&client->dev,
		"gc0403 read reg(0x%x val:0x%x) failed !\n", reg, *val);

	return ret;
}

static int gc0403_get_reso_dist(const struct gc0403_mode *mode,
				struct v4l2_mbus_framefmt *framefmt)
{
	return abs(mode->width - framefmt->width) +
	       abs(mode->height - framefmt->height);
}

static const struct gc0403_mode *
gc0403_find_best_fit(struct v4l2_subdev_format *fmt)
{
	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
	int dist;
	int cur_best_fit = 0;
	int cur_best_fit_dist = -1;
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
		dist = gc0403_get_reso_dist(&supported_modes[i], framefmt);
		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
			cur_best_fit_dist = dist;
			cur_best_fit = i;
		}
	}

	return &supported_modes[cur_best_fit];
}

static int gc0403_set_fmt(struct v4l2_subdev *sd,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	const struct gc0403_mode *mode;

	mutex_lock(&gc0403->mutex);

	mode = gc0403_find_best_fit(fmt);
	fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
	fmt->format.width = mode->width;
	fmt->format.height = mode->height;
	fmt->format.field = V4L2_FIELD_NONE;
	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
#else
		mutex_unlock(&gc0403->mutex);
		return -ENOTTY;
#endif
	} else {
		gc0403->cur_mode = mode;
	}

	mutex_unlock(&gc0403->mutex);

	return 0;
}

static int gc0403_get_fmt(struct v4l2_subdev *sd,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	const struct gc0403_mode *mode = gc0403->cur_mode;

	mutex_lock(&gc0403->mutex);
	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
#else
		mutex_unlock(&gc0403->mutex);
		return -ENOTTY;
#endif
	} else {
		fmt->format.width = mode->width;
		fmt->format.height = mode->height;
		fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
		fmt->format.field = V4L2_FIELD_NONE;
	}
	mutex_unlock(&gc0403->mutex);

	return 0;
}

static int gc0403_enum_mbus_code(struct v4l2_subdev *sd,
				 struct v4l2_subdev_pad_config *cfg,
				 struct v4l2_subdev_mbus_code_enum *code)
{
	if (code->index != 0)
		return -EINVAL;

	code->code = MEDIA_BUS_FMT_SRGGB10_1X10;

	return 0;
}

static int gc0403_enum_frame_sizes(struct v4l2_subdev *sd,
				   struct v4l2_subdev_pad_config *cfg,
				   struct v4l2_subdev_frame_size_enum *fse)
{
	if (fse->index >= ARRAY_SIZE(supported_modes))
		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
		return -EINVAL;

	fse->min_width  = supported_modes[fse->index].width;
	fse->max_width  = supported_modes[fse->index].width;
	fse->max_height = supported_modes[fse->index].height;
	fse->min_height = supported_modes[fse->index].height;

	return 0;
}

static int gc0403_g_frame_interval(struct v4l2_subdev *sd,
				   struct v4l2_subdev_frame_interval *fi)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	const struct gc0403_mode *mode = gc0403->cur_mode;

	mutex_lock(&gc0403->mutex);
	fi->interval = mode->max_fps;
	mutex_unlock(&gc0403->mutex);

	return 0;
}

static void gc0403_get_module_inf(struct gc0403 *gc0403,
				  struct rkmodule_inf *inf)
{
	memset(inf, 0, sizeof(*inf));
	strlcpy(inf->base.sensor, GC0403_NAME, sizeof(inf->base.sensor));
	strlcpy(inf->base.module, gc0403->module_name,
		sizeof(inf->base.module));
	strlcpy(inf->base.lens, gc0403->len_name, sizeof(inf->base.lens));
}

static long gc0403_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	long ret = 0;

	switch (cmd) {
	case RKMODULE_GET_MODULE_INFO:
		gc0403_get_module_inf(gc0403, (struct rkmodule_inf *)arg);
		break;
	default:
		ret = -ENOIOCTLCMD;
		break;
	}

	return ret;
}

#ifdef CONFIG_COMPAT
static long gc0403_compat_ioctl32(struct v4l2_subdev *sd,
				  unsigned int cmd, unsigned long arg)
{
	void __user *up = compat_ptr(arg);
	struct rkmodule_inf *inf;
	struct rkmodule_awb_cfg *cfg;
	long ret;

	switch (cmd) {
	case RKMODULE_GET_MODULE_INFO:
		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
		if (!inf) {
			ret = -ENOMEM;
			return ret;
		}

		ret = gc0403_ioctl(sd, cmd, inf);
		if (!ret) {
			ret = copy_to_user(up, inf, sizeof(*inf));
			if (ret) {
				ret = -EFAULT;
				return ret;
				}
		}
		kfree(inf);
		break;
	case RKMODULE_AWB_CFG:
		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
		if (!cfg) {
			ret = -ENOMEM;
			return ret;
		}

		ret = copy_from_user(cfg, up, sizeof(*cfg));
		if (!ret)
			ret = gc0403_ioctl(sd, cmd, cfg);
		else
			ret = -EFAULT;
		kfree(cfg);
		break;
	default:
		ret = -ENOIOCTLCMD;
		break;
	}

	return ret;
}
#endif

static int __gc0403_start_stream(struct gc0403 *gc0403)
{
	int ret = 0;

	/* In case these controls are set before streaming */
	mutex_unlock(&gc0403->mutex);
	ret = v4l2_ctrl_handler_setup(&gc0403->ctrl_handler);
	mutex_lock(&gc0403->mutex);
	if (ret)
		return ret;
	ret = gc0403_write_reg(gc0403->client, PAGE_SELECT_REG, 0x03);
	ret |= gc0403_write_reg(gc0403->client, GC0403_REG_MIPI_EN, 0x90);
	ret |= gc0403_write_reg(gc0403->client, PAGE_SELECT_REG, 0x00);

	return ret;
}

static int __gc0403_stop_stream(struct gc0403 *gc0403)
{
	int ret = 0;

	ret = gc0403_write_reg(gc0403->client, PAGE_SELECT_REG, 0x03);
	ret |= gc0403_write_reg(gc0403->client, GC0403_REG_MIPI_EN, 0x80);
	ret |= gc0403_write_reg(gc0403->client, PAGE_SELECT_REG, 0x00);

	return ret;
}

static int __gc0403_power_on(struct gc0403 *gc0403);
static void __gc0403_power_off(struct gc0403 *gc0403);

static int gc0403_s_power(struct v4l2_subdev *sd, int on)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	int ret = 0;

	mutex_lock(&gc0403->mutex);

	on = !!on;
	if (on)
		ret = pm_runtime_get_sync(&gc0403->client->dev);
	else
		ret = pm_runtime_put(&gc0403->client->dev);

	mutex_unlock(&gc0403->mutex);

	return ret;
}

static int gc0403_s_stream(struct v4l2_subdev *sd, int on)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	int ret = 0;

	mutex_lock(&gc0403->mutex);
	on = !!on;
	if (on == gc0403->streaming)
		goto unlock_and_return;

	if (on) {
		ret = __gc0403_start_stream(gc0403);
		if (ret) {
			v4l2_err(sd, "start stream failed while write regs\n");
			goto unlock_and_return;
		}
	} else {
		__gc0403_stop_stream(gc0403);
		usleep_range(33 * 1000, 35 * 1000);
	}

	gc0403->streaming = on;

unlock_and_return:
	mutex_unlock(&gc0403->mutex);

	return ret;
}

/* Calculate the delay in us by clock rate and clock cycles */
static int __gc0403_power_on(struct gc0403 *gc0403)
{
	int ret;
	struct device *dev = &gc0403->client->dev;

	ret = clk_set_rate(gc0403->xvclk, GC0403_XVCLK_FREQ);
	if (ret < 0) {
		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
		return ret;
	}
	if (clk_get_rate(gc0403->xvclk) != GC0403_XVCLK_FREQ)
		dev_warn(dev, "xvclk mismatched,modes are based on 24MHz\n");
	ret = clk_prepare_enable(gc0403->xvclk);
	if (ret < 0) {
		dev_err(dev, "Failed to enable xvclk\n");
		return ret;
	}

	ret = regulator_bulk_enable(GC0403_NUM_SUPPLIES, gc0403->supplies);
	if (ret < 0) {
		dev_err(dev, "Failed to enable regulators\n");
		goto disable_clk;
	}

	if (!IS_ERR(gc0403->pwdn_gpio))
		gpiod_set_value_cansleep(gc0403->pwdn_gpio, 0);
	/* here usleep at least 10~15ms，will better */
	usleep_range(10 * 1000, 15 * 1000);

	ret = gc0403_write_array(gc0403->client, gc0403->cur_mode->reg_list);
	if (ret)
		return ret;
	usleep_range(10 * 1000, 20 * 1000);

	return 0;

disable_clk:
	clk_disable_unprepare(gc0403->xvclk);

	return ret;
}

static void __gc0403_power_off(struct gc0403 *gc0403)
{
	if (!IS_ERR(gc0403->pwdn_gpio))
		gpiod_set_value_cansleep(gc0403->pwdn_gpio, 1);
	clk_disable_unprepare(gc0403->xvclk);
	regulator_bulk_disable(GC0403_NUM_SUPPLIES, gc0403->supplies);
}

static int gc0403_runtime_resume(struct device *dev)
{
	struct i2c_client *client = to_i2c_client(dev);
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct gc0403 *gc0403 = to_gc0403(sd);
	int ret;

	ret = __gc0403_power_on(gc0403);
	if (ret)
		return ret;

	if (gc0403->streaming) {
		ret = gc0403_s_stream(sd, 1);
		if (ret)
			__gc0403_power_off(gc0403);
	}

	return ret;
}

static int gc0403_runtime_suspend(struct device *dev)
{
	struct i2c_client *client = to_i2c_client(dev);
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct gc0403 *gc0403 = to_gc0403(sd);

	__gc0403_power_off(gc0403);

	return 0;
}

#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
static int gc0403_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
	struct gc0403 *gc0403 = to_gc0403(sd);
	struct v4l2_mbus_framefmt *try_fmt =
				v4l2_subdev_get_try_format(sd, fh->pad, 0);
	const struct gc0403_mode *def_mode = &supported_modes[1];

	mutex_lock(&gc0403->mutex);
	/* Initialize try_fmt */
	try_fmt->width = def_mode->width;
	try_fmt->height = def_mode->height;
	try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
	try_fmt->field = V4L2_FIELD_NONE;

	mutex_unlock(&gc0403->mutex);
	/* No crop or compose */

	return 0;
}
#endif

static int gc0403_enum_frame_interval(struct v4l2_subdev *sd,
				       struct v4l2_subdev_pad_config *cfg,
				       struct v4l2_subdev_frame_interval_enum *fie)
{
	if (fie->index >= ARRAY_SIZE(supported_modes))
		return -EINVAL;

	if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10)
		return -EINVAL;

	fie->width = supported_modes[fie->index].width;
	fie->height = supported_modes[fie->index].height;
	fie->interval = supported_modes[fie->index].max_fps;
	return 0;
}

static const struct dev_pm_ops gc0403_pm_ops = {
	SET_RUNTIME_PM_OPS(gc0403_runtime_suspend,
			   gc0403_runtime_resume, NULL)
};

#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
static const struct v4l2_subdev_internal_ops gc0403_internal_ops = {
	.open = gc0403_open,
};
#endif

static struct v4l2_subdev_core_ops gc0403_core_ops = {
	.s_power = gc0403_s_power,
	.ioctl = gc0403_ioctl,
#ifdef CONFIG_COMPAT
	.compat_ioctl32 = gc0403_compat_ioctl32,
#endif
};

static const struct v4l2_subdev_video_ops gc0403_video_ops = {
	.s_stream = gc0403_s_stream,
	.g_frame_interval = gc0403_g_frame_interval,
};

static const struct v4l2_subdev_pad_ops gc0403_pad_ops = {
	.enum_mbus_code = gc0403_enum_mbus_code,
	.enum_frame_size = gc0403_enum_frame_sizes,
	.enum_frame_interval = gc0403_enum_frame_interval,
	.get_fmt = gc0403_get_fmt,
	.set_fmt = gc0403_set_fmt,
};

static const struct v4l2_subdev_ops gc0403_subdev_ops = {
	.core	= &gc0403_core_ops,
	.video	= &gc0403_video_ops,
	.pad	= &gc0403_pad_ops,
};

static int gc0403_set_ctrl(struct v4l2_ctrl *ctrl)
{
	struct gc0403 *gc0403 = container_of(ctrl->handler,
					     struct gc0403, ctrl_handler);
	struct i2c_client *client = gc0403->client;
	int ret = 0;
	int analog_gain_table[] = {100, 142, 250, 354, 490, 691, 970,
				   1363, 1945, 2704, 3889};
	int table_cnt = 11;
	int analog_gain_reg_value = 0x00;
	int digital_gain_reg_value = 0x00;
	int total_gain = 0;
	int analog_gain = 0;
	int i = 0;

	if (pm_runtime_get(&client->dev) <= 0)
		return 0;

	switch (ctrl->id) {
	case V4L2_CID_EXPOSURE:
		dev_dbg(&client->dev,
			"gc0403: V4L2_CID_EXPOSURE exp val = 0x%x\n",
			ctrl->val);
		/* 4 least significant bits of expsoure are fractional part */
		ret = gc0403_write_reg(gc0403->client, GC0403_REG_EXP_H,
				       (ctrl->val >> 8) & 0x1f);
		ret |= gc0403_write_reg(gc0403->client, GC0403_REG_EXP_L,
				       ctrl->val & 0xff);
		break;
	case V4L2_CID_ANALOGUE_GAIN:
	case V4L2_CID_DIGITAL_GAIN:
		total_gain = ctrl->val;
		for (i = 0; i < table_cnt; i++) {
			if (total_gain < analog_gain_table[i])
				break;
		}

		i = i - 1;
		if (i < 0)
			i = 0;

		analog_gain = analog_gain_table[i];
		analog_gain_reg_value = i;
		digital_gain_reg_value =  total_gain * 64 / analog_gain;

		if (analog_gain_reg_value < GC0403_ANALOG_GAIN_MIN)
			analog_gain_reg_value = GC0403_ANALOG_GAIN_MIN;
		if (analog_gain_reg_value > GC0403_ANALOG_GAIN_MAX)
			analog_gain_reg_value = GC0403_ANALOG_GAIN_MAX;

		if (digital_gain_reg_value < GC0403_DIGI_GAIN_MIN)
			digital_gain_reg_value = GC0403_DIGI_GAIN_MIN;
		if (digital_gain_reg_value > GC0403_DIGI_GAIN_MAX)
			digital_gain_reg_value = GC0403_DIGI_GAIN_MAX;

		ret = gc0403_write_reg(gc0403->client,
				GC0403_REG_AGAIN,
				GC0403_FETCH_ANALOG_GAIN
					(analog_gain_reg_value));
		ret |= gc0403_write_reg(gc0403->client,
				GC0403_REG_DGAIN_H,
				GC0403_FETCH_DIGITAL_GAIN_HIGH
					(digital_gain_reg_value));
		ret |= gc0403_write_reg(gc0403->client,
				GC0403_REG_DGAIN_L,
				GC0403_FETCH_DIGITAL_GAIN_LOW
					(digital_gain_reg_value));

		dev_dbg(&client->dev, "gc0403: gain: %d,a: %d,d: %d\n",
			total_gain, analog_gain_reg_value,
			digital_gain_reg_value);
		break;
	case V4L2_CID_VBLANK:
		ret = gc0403_write_reg(gc0403->client, GC0403_REG_VBLK_H,
				       (ctrl->val) >> 8);
		ret |= gc0403_write_reg(gc0403->client, GC0403_REG_VBLK_L,
				       (ctrl->val) & 0xff);
		break;
	default:
		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
			 __func__, ctrl->id, ctrl->val);
		break;
	}

	pm_runtime_put(&client->dev);

	return ret;
}

static const struct v4l2_ctrl_ops gc0403_ctrl_ops = {
	.s_ctrl = gc0403_set_ctrl,
};

static int gc0403_initialize_controls(struct gc0403 *gc0403)
{
	const struct gc0403_mode *mode;
	struct v4l2_ctrl_handler *handler;
	struct v4l2_ctrl *ctrl;
	s64 vblank_def;
	u32 h_blank;
	int ret;

	handler = &gc0403->ctrl_handler;
	mode = gc0403->cur_mode;
	ret = v4l2_ctrl_handler_init(handler, 5);
	if (ret)
		return ret;
	handler->lock = &gc0403->mutex;

	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
				      0, 0, link_freq_menu_items);
	if (ctrl)
		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;

	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
			  0, GC0403_PIXEL_RATE, 1, GC0403_PIXEL_RATE);

	h_blank = mode->hts_def - mode->width;
	gc0403->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
				h_blank, h_blank, 1, h_blank);
	if (gc0403->hblank)
		gc0403->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;

	vblank_def = mode->vts_def - mode->height;
	gc0403->vblank = v4l2_ctrl_new_std(handler, &gc0403_ctrl_ops,
				V4L2_CID_VBLANK, vblank_def, vblank_def,
				1, vblank_def);

	gc0403->exposure = v4l2_ctrl_new_std(handler, &gc0403_ctrl_ops,
				V4L2_CID_EXPOSURE,
				GC0403_EXPOSURE_MIN, GC0403_EXPOSURE_MAX,
				1, mode->exp_def);

	/* Anolog gain */
	gc0403->anal_gain = v4l2_ctrl_new_std(handler, &gc0403_ctrl_ops,
				V4L2_CID_ANALOGUE_GAIN, GC0403_TOTAL_GAIN_MIN,
				GC0403_TOTAL_GAIN_MAX, GC0403_TOTAL_GAIN_STEP,
				GC0403_TOTAL_GAIN_MIN);

	/* Digital gain */
	gc0403->digi_gain = v4l2_ctrl_new_std(handler, &gc0403_ctrl_ops,
				V4L2_CID_DIGITAL_GAIN, GC0403_TOTAL_GAIN_MIN,
				GC0403_TOTAL_GAIN_MAX, GC0403_TOTAL_GAIN_STEP,
				GC0403_TOTAL_GAIN_MIN);

	if (handler->error) {
		ret = handler->error;
		dev_err(&gc0403->client->dev,
			"Failed to init controls(%d)\n", ret);
		goto err_free_handler;
	}

	gc0403->subdev.ctrl_handler = handler;

	return 0;

err_free_handler:
	v4l2_ctrl_handler_free(handler);

	return ret;
}

static int gc0403_check_sensor_id(struct gc0403 *gc0403,
				  struct i2c_client *client)
{
	struct device *dev = &gc0403->client->dev;
	u8 pid = 0, ver = 0;
	u16 id = 0;
	int ret = 0;

	/* Check sensor revision */
	ret = gc0403_read_reg(client, GC0403_REG_CHIP_ID_H, &pid);
	ret |= gc0403_read_reg(client, GC0403_REG_CHIP_ID_L, &ver);
	if (ret) {
		dev_err(&client->dev, "gc0403_read_reg failed (%d)\n", ret);
		return ret;
	}

	id = SENSOR_ID(pid, ver);
	if (id != GC0403_CHIP_ID) {
		dev_err(&client->dev,
				"Sensor detection failed (%04X,%d)\n",
				id, ret);
		return -ENODEV;
	}

	dev_info(dev, "Detected GC%04x sensor\n", id);

	return 0;
}

static int gc0403_configure_regulators(struct gc0403 *gc0403)
{
	unsigned int i;

	for (i = 0; i < GC0403_NUM_SUPPLIES; i++)
		gc0403->supplies[i].supply = gc0403_supply_names[i];

	return devm_regulator_bulk_get(&gc0403->client->dev,
				       GC0403_NUM_SUPPLIES,
				       gc0403->supplies);
}

static int gc0403_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct device *dev = &client->dev;
	/* add a dev_node */
	struct device_node *node = dev->of_node;
	struct gc0403 *gc0403;
	struct v4l2_subdev *sd;
	char facing[2];
	int ret;

	/* add info */
	dev_info(dev, "driver version: %02x.%02x.%02x",
		DRIVER_VERSION >> 16,
		(DRIVER_VERSION & 0xff00) >> 8,
		DRIVER_VERSION & 0x00ff);

	gc0403 = devm_kzalloc(dev, sizeof(*gc0403), GFP_KERNEL);
	if (!gc0403)
		return -ENOMEM;

	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
				   &gc0403->module_index);
	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
				       &gc0403->module_facing);
	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
				       &gc0403->module_name);
	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
				       &gc0403->len_name);
	if (ret) {
		dev_err(dev, "could not get module information!\n");
		return -EINVAL;
	}

	gc0403->client = client;
	gc0403->cur_mode = &supported_modes[1];

	gc0403->xvclk = devm_clk_get(dev, "xvclk");
	if (IS_ERR(gc0403->xvclk)) {
		dev_err(dev, "Failed to get xvclk\n");
		return -EINVAL;
	}

	gc0403->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
	if (IS_ERR(gc0403->pwdn_gpio))
		dev_warn(dev, "Failed to get pwdn-gpios\n");

	ret = gc0403_configure_regulators(gc0403);
	if (ret) {
		dev_err(dev, "Failed to get power regulators\n");
		return ret;
	}

	mutex_init(&gc0403->mutex);

	sd = &gc0403->subdev;
	v4l2_i2c_subdev_init(sd, client, &gc0403_subdev_ops);
	ret = gc0403_initialize_controls(gc0403);
	if (ret)
		goto err_destroy_mutex;

	ret = __gc0403_power_on(gc0403);
	if (ret)
		goto err_free_handler;

	ret = gc0403_check_sensor_id(gc0403, client);
	if (ret)
		goto err_power_off;

#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
	sd->internal_ops = &gc0403_internal_ops;
	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
#endif
#if defined(CONFIG_MEDIA_CONTROLLER)
	gc0403->pad.flags = MEDIA_PAD_FL_SOURCE;
	sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
	ret = media_entity_init(&sd->entity, 1, &gc0403->pad, 0);
	if (ret < 0)
		goto err_power_off;
#endif

	memset(facing, 0, sizeof(facing));
	if (strcmp(gc0403->module_facing, "back") == 0)
		facing[0] = 'b';
	else
		facing[0] = 'f';

	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
		 gc0403->module_index, facing,
		 GC0403_NAME, dev_name(sd->dev));

	ret = v4l2_async_register_subdev(sd);
	if (ret) {
		dev_err(dev, "v4l2 async register subdev failed\n");
		goto err_clean_entity;
	}

	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_runtime_idle(dev);

	return 0;

err_clean_entity:
#if defined(CONFIG_MEDIA_CONTROLLER)
	media_entity_cleanup(&sd->entity);
#endif
err_power_off:
	__gc0403_power_off(gc0403);
err_free_handler:
	v4l2_ctrl_handler_free(&gc0403->ctrl_handler);
err_destroy_mutex:
	mutex_destroy(&gc0403->mutex);

	return ret;
}

static int gc0403_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct gc0403 *gc0403 = to_gc0403(sd);

	v4l2_async_unregister_subdev(sd);
#if defined(CONFIG_MEDIA_CONTROLLER)
	media_entity_cleanup(&sd->entity);
#endif
	v4l2_ctrl_handler_free(&gc0403->ctrl_handler);
	mutex_destroy(&gc0403->mutex);

	pm_runtime_disable(&client->dev);
	if (!pm_runtime_status_suspended(&client->dev))
		__gc0403_power_off(gc0403);
	pm_runtime_set_suspended(&client->dev);

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id gc0403_of_match[] = {
	{ .compatible = "galaxycore,gc0403" },
	{},
};
MODULE_DEVICE_TABLE(of, gc0403_of_match);
#endif

static const struct i2c_device_id gc0403_match_id[] = {
	{ "gc0403", 0 },
	{ },
};

static struct i2c_driver gc0403_i2c_driver = {
	.driver = {
		.name = "gc0403",
		.pm = &gc0403_pm_ops,
		.of_match_table = of_match_ptr(gc0403_of_match),
	},
	.probe		= &gc0403_probe,
	.remove		= &gc0403_remove,
	.id_table	= gc0403_match_id,
};

static int __init sensor_mod_init(void)
{
	return i2c_add_driver(&gc0403_i2c_driver);
}

static void __exit sensor_mod_exit(void)
{
	i2c_del_driver(&gc0403_i2c_driver);
}

device_initcall_sync(sensor_mod_init);
module_exit(sensor_mod_exit);

MODULE_DESCRIPTION("Galaxycore gc0403 sensor driver");
MODULE_LICENSE("GPL v2");

git clone https://github.com/u-boot/u-boot.git
cd u-boot
git reset --hard v2020.04

#
# Automatically generated file; DO NOT EDIT.
# U-Boot 2020.04 Configuration
#
CONFIG_CREATE_ARCH_SYMLINK=y
# CONFIG_ARC is not set
CONFIG_ARM=y
# CONFIG_M68K is not set
# CONFIG_MICROBLAZE is not set
# CONFIG_MIPS is not set
# CONFIG_NDS32 is not set
# CONFIG_NIOS2 is not set
# CONFIG_PPC is not set
# CONFIG_RISCV is not set
# CONFIG_SANDBOX is not set
# CONFIG_SH is not set
# CONFIG_X86 is not set
# CONFIG_XTENSA is not set
CONFIG_SYS_ARCH="arm"
CONFIG_SYS_CPU="armv7"
CONFIG_SYS_SOC="sunxi"
CONFIG_SYS_BOARD="sunxi"
CONFIG_SYS_CONFIG_NAME="sun8i"
# CONFIG_SYS_ICACHE_OFF is not set
# CONFIG_SPL_SYS_ICACHE_OFF is not set
# CONFIG_SYS_DCACHE_OFF is not set
# CONFIG_SPL_SYS_DCACHE_OFF is not set

#
# ARM architecture
#
# CONFIG_GIC_V3_ITS is not set
CONFIG_HAS_VBAR=y
CONFIG_HAS_THUMB2=y
CONFIG_ARM_ASM_UNIFIED=y
CONFIG_SYS_ARM_CACHE_CP15=y
CONFIG_SYS_ARM_MMU=y
# CONFIG_SYS_ARM_MPU is not set
CONFIG_CPU_V7A=y
CONFIG_SYS_ARM_ARCH=7
CONFIG_SYS_CACHE_SHIFT_6=y
CONFIG_SYS_CACHELINE_SIZE=64
# CONFIG_ARCH_CPU_INIT is not set
# CONFIG_SYS_ARCH_TIMER is not set
# CONFIG_ARM_SMCCC is not set
# CONFIG_SEMIHOSTING is not set
CONFIG_SYS_THUMB_BUILD=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SYS_L2CACHE_OFF is not set
# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
CONFIG_USE_ARCH_MEMCPY=y
CONFIG_SPL_USE_ARCH_MEMCPY=y
CONFIG_USE_ARCH_MEMSET=y
CONFIG_SPL_USE_ARCH_MEMSET=y
# CONFIG_SET_STACK_SIZE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_TARGET_EDB93XX is not set
# CONFIG_TARGET_ASPENITE is not set
# CONFIG_TARGET_GPLUGD is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_KIRKWOOD is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_TARGET_APF27 is not set
# CONFIG_ORION5X is not set
# CONFIG_TARGET_SPEAR300 is not set
# CONFIG_TARGET_SPEAR310 is not set
# CONFIG_TARGET_SPEAR320 is not set
# CONFIG_TARGET_SPEAR600 is not set
# CONFIG_TARGET_STV0991 is not set
# CONFIG_TARGET_X600 is not set
# CONFIG_TARGET_FLEA3 is not set
# CONFIG_TARGET_MX35PDK is not set
# CONFIG_ARCH_BCM283X is not set
# CONFIG_ARCH_BCM63158 is not set
# CONFIG_ARCH_BCM68360 is not set
# CONFIG_ARCH_BCM6858 is not set
# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
# CONFIG_ARCH_BCMSTB is not set
# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
# CONFIG_TARGET_BCM23550_W1D is not set
# CONFIG_TARGET_BCM28155_AP is not set
# CONFIG_TARGET_BCMCYGNUS is not set
# CONFIG_TARGET_BCMNSP is not set
# CONFIG_TARGET_BCMNS2 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_OMAP2PLUS is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_IMX8 is not set
# CONFIG_ARCH_IMX8M is not set
# CONFIG_ARCH_IMXRT is not set
# CONFIG_ARCH_MX23 is not set
# CONFIG_ARCH_MX25 is not set
# CONFIG_ARCH_MX28 is not set
# CONFIG_ARCH_MX31 is not set
# CONFIG_ARCH_MX7ULP is not set
# CONFIG_ARCH_MX7 is not set
# CONFIG_ARCH_MX6 is not set
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_ARCH_MX5 is not set
# CONFIG_ARCH_OWL is not set
# CONFIG_ARCH_QEMU is not set
# CONFIG_ARCH_RMOBILE is not set
# CONFIG_TARGET_S32V234EVB is not set
# CONFIG_ARCH_SNAPDRAGON is not set
# CONFIG_ARCH_SOCFPGA is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VERSAL is not set
# CONFIG_ARCH_VF610 is not set
# CONFIG_ARCH_ZYNQ is not set
# CONFIG_ARCH_ZYNQMP_R5 is not set
# CONFIG_ARCH_ZYNQMP is not set
# CONFIG_TEGRA is not set
# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
# CONFIG_TARGET_VEXPRESS64_JUNO is not set
# CONFIG_TARGET_LS2080A_EMU is not set
# CONFIG_TARGET_LS2080A_SIMU is not set
# CONFIG_TARGET_LS1088AQDS is not set
# CONFIG_TARGET_LS2080AQDS is not set
# CONFIG_TARGET_LS2080ARDB is not set
# CONFIG_TARGET_LS2081ARDB is not set
# CONFIG_TARGET_LX2160ARDB is not set
# CONFIG_TARGET_LX2160AQDS is not set
# CONFIG_TARGET_HIKEY is not set
# CONFIG_TARGET_HIKEY960 is not set
# CONFIG_TARGET_POPLAR is not set
# CONFIG_TARGET_LS1012AQDS is not set
# CONFIG_TARGET_LS1012ARDB is not set
# CONFIG_TARGET_LS1012A2G5RDB is not set
# CONFIG_TARGET_LS1012AFRWY is not set
# CONFIG_TARGET_LS1012AFRDM is not set
# CONFIG_TARGET_LS1028AQDS is not set
# CONFIG_TARGET_LS1028ARDB is not set
# CONFIG_TARGET_LS1088ARDB is not set
# CONFIG_TARGET_LS1021AQDS is not set
# CONFIG_TARGET_LS1021ATWR is not set
# CONFIG_TARGET_LS1021ATSN is not set
# CONFIG_TARGET_LS1021AIOT is not set
# CONFIG_TARGET_LS1043AQDS is not set
# CONFIG_TARGET_LS1043ARDB is not set
# CONFIG_TARGET_LS1046AQDS is not set
# CONFIG_TARGET_LS1046ARDB is not set
# CONFIG_TARGET_LS1046AFRWY is not set
# CONFIG_TARGET_COLIBRI_PXA270 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_STM32 is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_STM32MP is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_TARGET_THUNDERX_88XX is not set
# CONFIG_ARCH_ASPEED is not set
# CONFIG_TARGET_DURIAN is not set
# CONFIG_TARGET_PRESIDIO_ASIC is not set
CONFIG_SYS_TEXT_BASE=0x42e00000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SPL_DRIVERS_MISC_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x4fe00000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_ERR_PTR_OFFSET=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_SIZE_LIMIT=0
CONFIG_SPL=y
CONFIG_PRE_CON_BUF_ADDR=0x4f000000
CONFIG_PRE_CON_BUF_SZ=4096
CONFIG_BOOTSTAGE_STASH_ADDR=0
CONFIG_IDENT_STRING=" Allwinner Technology"
# CONFIG_SUN6I_P2WI is not set
CONFIG_SUN6I_PRCM=y
# CONFIG_AXP_PMIC_BUS is not set
CONFIG_SUN8I_RSB=y
CONFIG_SUNXI_SRAM_ADDRESS=0x0
CONFIG_SUNXI_GEN_SUN6I=y
CONFIG_SUNXI_DRAM_DW=y
CONFIG_SUNXI_DRAM_DW_16BIT=y
CONFIG_SUNXI_DRAM_MAX_SIZE=0x80000000
# CONFIG_MACH_SUN4I is not set
# CONFIG_MACH_SUN5I is not set
# CONFIG_MACH_SUN6I is not set
# CONFIG_MACH_SUN7I is not set
# CONFIG_MACH_SUN8I_A23 is not set
# CONFIG_MACH_SUN8I_A33 is not set
# CONFIG_MACH_SUN8I_A83T is not set
# CONFIG_MACH_SUN8I_H3 is not set
# CONFIG_MACH_SUN8I_R40 is not set
CONFIG_MACH_SUN8I_V3S=y
# CONFIG_MACH_SUN9I is not set
# CONFIG_MACH_SUN50I is not set
# CONFIG_MACH_SUN50I_H5 is not set
# CONFIG_MACH_SUN50I_H6 is not set
CONFIG_MACH_SUN8I=y
# CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER is not set
CONFIG_SUNXI_DRAM_DDR2=y
# CONFIG_SUNXI_DRAM_LPDDR3_STOCK is not set
CONFIG_SUNXI_DRAM_DDR2_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
# CONFIG_DRAM_ODT_EN is not set
CONFIG_SYS_CLK_FREQ=1008000000
CONFIG_UART0_PORT_F=y
# CONFIG_OLD_SUNXI_KERNEL_COMPAT is not set
CONFIG_MACPWR=""
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC1_CD_PIN=""
CONFIG_MMC2_CD_PIN=""
CONFIG_MMC3_CD_PIN=""
CONFIG_MMC1_PINS=""
CONFIG_MMC2_PINS=""
CONFIG_MMC3_PINS=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=-1
CONFIG_INITIAL_USB_SCAN_DELAY=0
CONFIG_USB0_VBUS_PIN=""
CONFIG_USB0_VBUS_DET=""
CONFIG_USB0_ID_DET=""
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_USB3_VBUS_PIN=""
# CONFIG_I2C0_ENABLE is not set
# CONFIG_I2C1_ENABLE is not set
# CONFIG_I2C2_ENABLE is not set
# CONFIG_R_I2C_ENABLE is not set
# CONFIG_AXP_GPIO is not set
CONFIG_SATAPWR=""
CONFIG_GMAC_TX_DELAY=0
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_SPL_SPI_SUPPORT is not set
CONFIG_CPU_V7_HAS_NONSEC=y
CONFIG_CPU_V7_HAS_VIRT=y
CONFIG_ARCH_SUPPORT_PSCI=y
CONFIG_ARMV7_NONSEC=y
# CONFIG_ARMV7_BOOT_SEC_DEFAULT is not set
CONFIG_ARMV7_VIRT=y
CONFIG_ARMV7_PSCI=y
CONFIG_ARMV7_PSCI_NR_CPUS=4
CONFIG_ARMV7_LPAE=y
CONFIG_CSF_SIZE=0x2060
# CONFIG_CMD_DEKBLOB is not set
# CONFIG_CMD_HDMIDETECT is not set
CONFIG_IMX_DCD_ADDR=0x00910000

#
# ARM debug
#
# CONFIG_DEBUG_LL is not set
CONFIG_SMBIOS_PRODUCT_NAME="sunxi"
# CONFIG_DEBUG_UART is not set
# CONFIG_AHCI is not set
CONFIG_SPL_TEXT_BASE=0x00060

#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_SYS_BOOT_GET_CMDLINE is not set
# CONFIG_SYS_BOOT_GET_KBD is not set
CONFIG_SYS_MALLOC_F=y
CONFIG_EXPERT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_TOOLS_DEBUG is not set
# CONFIG_PHYS_64BIT is not set
CONFIG_SPL_IMAGE="spl/u-boot-spl.bin"
CONFIG_BUILD_TARGET=""
# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
CONFIG_PLATFORM_ELFENTRY="_start"

#
# Boot images
#
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x0
CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
# CONFIG_FIT_SIGNATURE is not set
# CONFIG_FIT_CIPHER is not set
# CONFIG_FIT_VERBOSE is not set
# CONFIG_FIT_BEST_MATCH is not set
# CONFIG_SPL_FIT is not set
# CONFIG_SPL_LOAD_FIT is not set
# CONFIG_SPL_LOAD_FIT_FULL is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_OF_SYSTEM_SETUP is not set
# CONFIG_OF_STDOUT_VIA_ALIAS is not set
CONFIG_SYS_EXTRA_OPTIONS=""
CONFIG_HAVE_SYS_TEXT_BASE=y
CONFIG_ARCH_FIXUP_FDT_MEMORY=y

#
# API
#
# CONFIG_API is not set

#
# Boot timing
#
# CONFIG_BOOTSTAGE is not set
CONFIG_BOOTSTAGE_RECORD_COUNT=30
CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=5
CONFIG_TPL_BOOTSTAGE_RECORD_COUNT=5
CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
# CONFIG_SHOW_BOOT_PROGRESS is not set

#
# Boot media
#
# CONFIG_NAND_BOOT is not set
# CONFIG_ONENAND_BOOT is not set
# CONFIG_QSPI_BOOT is not set
# CONFIG_SATA_BOOT is not set
# CONFIG_SD_BOOT is not set
# CONFIG_SPI_BOOT is not set
CONFIG_BOOTDELAY=2
# CONFIG_USE_BOOTARGS is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT=""

#
# Console
#
CONFIG_MENU=y
# CONFIG_CONSOLE_RECORD is not set
# CONFIG_DISABLE_CONSOLE is not set
CONFIG_LOGLEVEL=4
CONFIG_SPL_LOGLEVEL=4
CONFIG_TPL_LOGLEVEL=4
# CONFIG_SILENT_CONSOLE is not set
CONFIG_PRE_CONSOLE_BUFFER=y
# CONFIG_CONSOLE_MUX is not set
# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set
# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
CONFIG_SYS_STDIO_DEREGISTER=y

#
# Logging
#
# CONFIG_LOG is not set
CONFIG_LOG_DEFAULT_LEVEL=6
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE=""
CONFIG_MISC_INIT_R=y
# CONFIG_VERSION_VARIABLE is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_DISPLAY_BOARDINFO_LATE is not set
# CONFIG_BOUNCE_BUFFER is not set
# CONFIG_BOARD_TYPES is not set

#
# Start-up hooks
#
# CONFIG_ARCH_EARLY_INIT_R is not set
# CONFIG_ARCH_MISC_INIT is not set
# CONFIG_BOARD_EARLY_INIT_F is not set
# CONFIG_BOARD_EARLY_INIT_R is not set
# CONFIG_LAST_STAGE_INIT is not set

#
# Security support
#
CONFIG_HASH=y

#
# Update support
#
# CONFIG_UPDATE_TFTP is not set
# CONFIG_ANDROID_AB is not set

#
# Blob list
#
# CONFIG_BLOBLIST is not set

#
# SPL / TPL
#
CONFIG_SUPPORT_SPL=y
CONFIG_SPL_FRAMEWORK=y
# CONFIG_SPL_FRAMEWORK_BOARD_INIT_F is not set
CONFIG_SPL_SYS_STACK_F_CHECK_BYTE=0xaa
# CONFIG_SPL_SYS_REPORT_STACK_F_USAGE is not set

#
# PowerPC and LayerScape SPL Boot options
#
# CONFIG_SPL_BOARD_INIT is not set
# CONFIG_SPL_BOOTROM_SUPPORT is not set
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
# CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
# CONFIG_SPL_SEPARATE_BSS is not set
CONFIG_SPL_BANNER_PRINT=y
# CONFIG_SPL_EARLY_BSS is not set
# CONFIG_SPL_DISPLAY_PRINT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x50
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x0
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
CONFIG_SPL_CRC32_SUPPORT=y
# CONFIG_SPL_CACHE_SUPPORT is not set
# CONFIG_SPL_CPU_SUPPORT is not set
# CONFIG_SPL_CRYPTO_SUPPORT is not set
# CONFIG_SPL_HASH_SUPPORT is not set
# CONFIG_SPL_DMA is not set
# CONFIG_SPL_DM_GPIO is not set
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_FAT_WRITE is not set
# CONFIG_SPL_FPGA_SUPPORT is not set
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_DM_MAILBOX is not set
# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set
# CONFIG_SPL_MTD_SUPPORT is not set
# CONFIG_SPL_MUSB_NEW_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_UBI is not set
# CONFIG_SPL_NET_SUPPORT is not set
# CONFIG_SPL_NO_CPU_SUPPORT is not set
# CONFIG_SPL_NOR_SUPPORT is not set
# CONFIG_SPL_XIP_SUPPORT is not set
# CONFIG_SPL_ONENAND_SUPPORT is not set
# CONFIG_SPL_OS_BOOT is not set
CONFIG_SPL_PAYLOAD="u-boot.bin"
# CONFIG_SPL_PCI is not set
# CONFIG_SPL_PCH_SUPPORT is not set
# CONFIG_SPL_POST_MEM_SUPPORT is not set
# CONFIG_SPL_DM_RESET is not set
CONFIG_SPL_POWER_SUPPORT=y
# CONFIG_SPL_POWER_DOMAIN is not set
# CONFIG_SPL_RAM_SUPPORT is not set
# CONFIG_SPL_REMOTEPROC is not set
# CONFIG_SPL_RTC_SUPPORT is not set
# CONFIG_SPL_SATA_SUPPORT is not set
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_SPL_THERMAL is not set
# CONFIG_SPL_USB_HOST_SUPPORT is not set
# CONFIG_SPL_USB_GADGET is not set
# CONFIG_SPL_WATCHDOG_SUPPORT is not set
# CONFIG_SPL_YMODEM_SUPPORT is not set
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
# CONFIG_SPL_OPTEE is not set

#
# Command line interface
#
CONFIG_CMDLINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_SYS_LONGHELP=y
CONFIG_SYS_PROMPT="=> "
CONFIG_SYS_XTRACE="y"

#
# Autoboot options
#
CONFIG_AUTOBOOT=y
# CONFIG_AUTOBOOT_KEYED is not set
# CONFIG_AUTOBOOT_USE_MENUKEY is not set

#
# Commands
#

#
# Info commands
#
CONFIG_CMD_BDI=y
# CONFIG_CMD_CONFIG is not set
CONFIG_CMD_CONSOLE=y
# CONFIG_CMD_CPU is not set
# CONFIG_CMD_LICENSE is not set
# CONFIG_CMD_PMC is not set

#
# Boot commands
#
CONFIG_CMD_BOOTD=y
CONFIG_CMD_BOOTM=y
CONFIG_BOOTM_EFI=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTM_LINUX=y
CONFIG_BOOTM_NETBSD=y
# CONFIG_BOOTM_OPENRTOS is not set
# CONFIG_BOOTM_OSE is not set
CONFIG_BOOTM_PLAN9=y
CONFIG_BOOTM_RTEMS=y
CONFIG_BOOTM_VXWORKS=y
CONFIG_CMD_BOOTEFI=y
CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
# CONFIG_CMD_BOOTEFI_HELLO is not set
# CONFIG_CMD_BOOTEFI_SELFTEST is not set
# CONFIG_CMD_BOOTMENU is not set
# CONFIG_CMD_ADTIMG is not set
CONFIG_CMD_ELF=y
CONFIG_CMD_FDT=y
CONFIG_CMD_GO=y
CONFIG_CMD_RUN=y
CONFIG_CMD_IMI=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_XIMG=y
# CONFIG_CMD_SPL is not set
# CONFIG_CMD_FITUPD is not set
# CONFIG_CMD_THOR_DOWNLOAD is not set
# CONFIG_CMD_ZBOOT is not set

#
# Environment commands
#
# CONFIG_CMD_ASKENV is not set
CONFIG_CMD_EXPORTENV=y
CONFIG_CMD_IMPORTENV=y
CONFIG_CMD_EDITENV=y
# CONFIG_CMD_GREPENV is not set
CONFIG_CMD_SAVEENV=y
# CONFIG_CMD_ERASEENV is not set
CONFIG_CMD_ENV_EXISTS=y
# CONFIG_CMD_ENV_CALLBACK is not set
# CONFIG_CMD_ENV_FLAGS is not set
# CONFIG_CMD_NVEDIT_EFI is not set
# CONFIG_CMD_NVEDIT_INFO is not set

#
# Memory commands
#
# CONFIG_CMD_BINOP is not set
CONFIG_CMD_CRC32=y
# CONFIG_CRC32_VERIFY is not set
# CONFIG_CMD_EEPROM is not set
# CONFIG_LOOPW is not set
# CONFIG_CMD_MD5SUM is not set
# CONFIG_CMD_MEMINFO is not set
CONFIG_CMD_MEMORY=y
# CONFIG_CMD_MX_CYCLIC is not set
CONFIG_CMD_RANDOM=y
# CONFIG_CMD_MEMTEST is not set
# CONFIG_CMD_SHA1SUM is not set
# CONFIG_CMD_STRINGS is not set

#
# Compression commands
#
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_ZIP is not set

#
# Device access commands
#
# CONFIG_CMD_ARMFLASH is not set
# CONFIG_CMD_ADC is not set
# CONFIG_CMD_BIND is not set
# CONFIG_CMD_CLK is not set
# CONFIG_CMD_DEMO is not set
# CONFIG_CMD_DFU is not set
CONFIG_CMD_DM=y
# CONFIG_CMD_FPGAD is not set
# CONFIG_CMD_FUSE is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_GPT_RENAME is not set
# CONFIG_CMD_IDE is not set
# CONFIG_CMD_IO is not set
# CONFIG_CMD_IOTRACE is not set
# CONFIG_CMD_I2C is not set
CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
# CONFIG_CMD_MMC is not set
# CONFIG_CMD_OSD is not set
CONFIG_CMD_PART=y
# CONFIG_CMD_PCI is not set
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_POWEROFF is not set
# CONFIG_CMD_READ is not set
# CONFIG_CMD_SATA is not set
# CONFIG_CMD_SAVES is not set
# CONFIG_CMD_SCSI is not set
# CONFIG_CMD_SDRAM is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_SF_TEST is not set
# CONFIG_CMD_SPI is not set
# CONFIG_CMD_TSI148 is not set
# CONFIG_CMD_UNIVERSE is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_USB_SDP is not set
# CONFIG_CMD_USB_MASS_STORAGE is not set

#
# Shell scripting commands
#
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
CONFIG_CMD_SOURCE=y
CONFIG_CMD_SETEXPR=y

#
# Android support commands
#
CONFIG_CMD_NET=y
CONFIG_CMD_BOOTP=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_DNS=y
# CONFIG_BOOTP_DNS2 is not set
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_BOOTP_PREFER_SERVERIP is not set
CONFIG_BOOTP_SUBNETMASK=y
# CONFIG_BOOTP_NTPSERVER is not set
# CONFIG_CMD_PCAP is not set
CONFIG_BOOTP_PXE=y
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CMD_TFTPBOOT=y
# CONFIG_CMD_TFTPPUT is not set
# CONFIG_CMD_TFTPSRV is not set
CONFIG_NET_TFTP_VARS=y
# CONFIG_CMD_RARP is not set
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_CDP is not set
# CONFIG_CMD_SNTP is not set
# CONFIG_CMD_DNS is not set
# CONFIG_CMD_LINK_LOCAL is not set
# CONFIG_CMD_ETHSW is not set
CONFIG_CMD_PXE=y
# CONFIG_CMD_WOL is not set

#
# Misc commands
#
# CONFIG_CMD_BSP is not set
CONFIG_CMD_BLOCK_CACHE=y
# CONFIG_CMD_CACHE is not set
# CONFIG_CMD_CONITRACE is not set
# CONFIG_CMD_EFIDEBUG is not set
# CONFIG_CMD_EXCEPTION is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_GETTIME is not set
CONFIG_CMD_MISC=y
# CONFIG_MP is not set
# CONFIG_CMD_TIMER is not set
CONFIG_CMD_SYSBOOT=y
# CONFIG_CMD_QFW is not set
# CONFIG_CMD_TERMINAL is not set
# CONFIG_CMD_UUID is not set

#
# TI specific command line interface
#
# CONFIG_CMD_DDR3 is not set

#
# Power commands
#

#
# Security commands
#
# CONFIG_CMD_AES is not set
# CONFIG_CMD_BLOB is not set
# CONFIG_CMD_HASH is not set

#
# Firmware commands
#

#
# Filesystem commands
#
# CONFIG_CMD_BTRFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
# CONFIG_CMD_EXT4_WRITE is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_CMD_FS_UUID is not set
# CONFIG_CMD_JFFS2 is not set
CONFIG_MTDIDS_DEFAULT=""
CONFIG_MTDPARTS_DEFAULT=""
# CONFIG_CMD_REISER is not set
# CONFIG_CMD_ZFS is not set

#
# Debug commands
#
# CONFIG_CMD_BEDBUG is not set
# CONFIG_CMD_DIAG is not set
# CONFIG_CMD_LOG is not set
# CONFIG_CMD_TRACE is not set
# CONFIG_CMD_UBI is not set

#
# Partition Types
#
CONFIG_PARTITIONS=y
# CONFIG_MAC_PARTITION is not set
# CONFIG_SPL_MAC_PARTITION is not set
CONFIG_DOS_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_ISO_PARTITION=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_SPL_AMIGA_PARTITION is not set
CONFIG_EFI_PARTITION=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=56
CONFIG_EFI_PARTITION_ENTRIES_OFF=0
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_PARTITION_UUIDS=y
# CONFIG_SPL_PARTITION_UUIDS is not set
# CONFIG_PARTITION_TYPE_GUID is not set
CONFIG_SUPPORT_OF_CONTROL=y
CONFIG_DTC=y
CONFIG_PYLIBFDT=y
CONFIG_DTOC=y
CONFIG_BINMAN=y

#
# Device Tree Control
#
CONFIG_OF_CONTROL=y
# CONFIG_OF_BOARD_FIXUP is not set
# CONFIG_SPL_OF_CONTROL is not set
# CONFIG_OF_LIVE is not set
CONFIG_OF_SEPARATE=y
# CONFIG_OF_EMBED is not set
# CONFIG_OF_BOARD is not set
# CONFIG_OF_PRIOR_STAGE is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
# CONFIG_MULTI_DTB_FIT is not set
# CONFIG_OF_DTB_PROPS_REMOVE is not set
CONFIG_MKIMAGE_DTC_PATH="dtc"

#
# Environment
#
CONFIG_ENV_SUPPORT=y
# CONFIG_ENV_IS_NOWHERE is not set
# CONFIG_ENV_IS_IN_EEPROM is not set
CONFIG_ENV_IS_IN_FAT=y
# CONFIG_ENV_IS_IN_EXT4 is not set
# CONFIG_ENV_IS_IN_FLASH is not set
# CONFIG_ENV_IS_IN_NAND is not set
# CONFIG_ENV_IS_IN_NVRAM is not set
# CONFIG_ENV_IS_IN_ONENAND is not set
# CONFIG_ENV_IS_IN_REMOTE is not set
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto"
CONFIG_ENV_FAT_FILE="uboot.env"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_USE_DEFAULT_ENV_FILE is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
CONFIG_NET=y
# CONFIG_NET_RANDOM_ETHADDR is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_IP_DEFRAG is not set
CONFIG_TFTP_BLOCKSIZE=1468

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_DM=y
# CONFIG_SPL_DM is not set
CONFIG_DM_WARN=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_DEVICE_REMOVE=y
CONFIG_DM_STDIO=y
CONFIG_DM_SEQ_ALIAS=y
# CONFIG_REGMAP is not set
# CONFIG_DEVRES is not set
CONFIG_SIMPLE_BUS=y
CONFIG_OF_TRANSLATE=y
# CONFIG_TRANSLATION_OFFSET is not set
CONFIG_DM_DEV_READ_INLINE=y
# CONFIG_ADC is not set
# CONFIG_ADC_EXYNOS is not set
# CONFIG_ADC_SANDBOX is not set
# CONFIG_SARADC_MESON is not set
# CONFIG_SARADC_ROCKCHIP is not set
# CONFIG_SATA is not set
# CONFIG_SCSI_AHCI is not set

#
# SATA/SCSI device support
#
# CONFIG_DWC_AHSATA is not set
# CONFIG_FSL_SATA is not set
# CONFIG_MVSATA_IDE is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL3114 is not set
# CONFIG_AXI is not set
CONFIG_BLK=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BLOCK_CACHE=y
# CONFIG_IDE is not set
# CONFIG_BOOTCOUNT_LIMIT is not set

#
# Cache Controller drivers
#
# CONFIG_CACHE is not set
# CONFIG_L2X0_CACHE is not set
# CONFIG_NCORE_CACHE is not set

#
# Clock
#
CONFIG_CLK=y
# CONFIG_SPL_CLK_CCF is not set
# CONFIG_CLK_CCF is not set
# CONFIG_CLK_HSDK is not set
# CONFIG_CLK_CDCE9XX is not set
# CONFIG_CLK_AT91 is not set
CONFIG_CLK_SUNXI=y
# CONFIG_CLK_SUN4I_A10 is not set
# CONFIG_CLK_SUN5I_A10S is not set
# CONFIG_CLK_SUN6I_A31 is not set
# CONFIG_CLK_SUN8I_A23 is not set
# CONFIG_CLK_SUN8I_A83T is not set
# CONFIG_CLK_SUN8I_R40 is not set
CONFIG_CLK_SUN8I_V3S=y
# CONFIG_CLK_SUN9I_A80 is not set
# CONFIG_CLK_SUN8I_H3 is not set
# CONFIG_CLK_SUN50I_H6 is not set
# CONFIG_CLK_SUN50I_A64 is not set
# CONFIG_CLK_SIFIVE is not set
# CONFIG_ICS8N3QV01 is not set
# CONFIG_CLK_MPC83XX is not set
# CONFIG_CPU is not set

#
# Hardware crypto devices
#
# CONFIG_FSL_CAAM is not set
# CONFIG_SYS_FSL_SEC_BE is not set
# CONFIG_SYS_FSL_SEC_LE is not set

#
# Demo for driver model
#
# CONFIG_DM_DEMO is not set
# CONFIG_BOARD is not set

#
# DFU support
#

#
# DMA Support
#
# CONFIG_DMA is not set
# CONFIG_TI_EDMA3 is not set

#
# Fastboot support
#
# CONFIG_USB_FUNCTION_FASTBOOT is not set
# CONFIG_UDP_FUNCTION_FASTBOOT is not set
# CONFIG_FIRMWARE is not set
# CONFIG_ZYNQMP_FIRMWARE is not set

#
# FPGA support
#
# CONFIG_FPGA_ALTERA is not set
# CONFIG_FPGA_SOCFPGA is not set
# CONFIG_FPGA_XILINX is not set

#
# GPIO Support
#
# CONFIG_GPIO_HOG is not set
# CONFIG_ALTERA_PIO is not set
# CONFIG_DWAPB_GPIO is not set
# CONFIG_AT91_GPIO is not set
# CONFIG_ATMEL_PIO4 is not set
# CONFIG_DA8XX_GPIO is not set
# CONFIG_INTEL_BROADWELL_GPIO is not set
# CONFIG_INTEL_GPIO is not set
# CONFIG_INTEL_ICH6_GPIO is not set
# CONFIG_IMX_RGPIO2P is not set
# CONFIG_HSDK_CREG_GPIO is not set
# CONFIG_LPC32XX_GPIO is not set
# CONFIG_MSM_GPIO is not set
# CONFIG_MXC_GPIO is not set
# CONFIG_MXS_GPIO is not set
# CONFIG_CMD_PCA953X is not set
# CONFIG_ROCKCHIP_GPIO is not set
CONFIG_SUNXI_GPIO=y
# CONFIG_XILINX_GPIO is not set
# CONFIG_CMD_TCA642X is not set
# CONFIG_TEGRA_GPIO is not set
# CONFIG_TEGRA186_GPIO is not set
# CONFIG_VYBRID_GPIO is not set
# CONFIG_SIFIVE_GPIO is not set
# CONFIG_DM_74X164 is not set
# CONFIG_DM_PCA953X is not set
# CONFIG_SPL_DM_PCA953X is not set
# CONFIG_MPC8XXX_GPIO is not set

#
# Hardware Spinlock Support
#
# CONFIG_DM_HWSPINLOCK is not set

#
# I2C support
#
# CONFIG_DM_I2C is not set
# CONFIG_SYS_I2C_DW is not set
# CONFIG_SYS_I2C_IMX_LPI2C is not set
# CONFIG_SYS_I2C_MXC is not set
CONFIG_INPUT=y
CONFIG_DM_KEYBOARD=y
# CONFIG_CROS_EC_KEYB is not set
# CONFIG_I8042_KEYB is not set
# CONFIG_TEGRA_KEYBOARD is not set
# CONFIG_TWL4030_INPUT is not set

#
# LED Support
#
# CONFIG_LED is not set
# CONFIG_LED_STATUS is not set

#
# Mailbox Controller Support
#
# CONFIG_DM_MAILBOX is not set

#
# Memory Controller drivers
#

#
# Multifunction device drivers
#
# CONFIG_MISC is not set
# CONFIG_CROS_EC is not set
# CONFIG_SPL_CROS_EC is not set
# CONFIG_DS4510 is not set
# CONFIG_FSL_SEC_MON is not set
# CONFIG_NUVOTON_NCT6102D is not set
# CONFIG_PWRSEQ is not set
# CONFIG_PCA9551_LED is not set
# CONFIG_TWL4030_LED is not set
# CONFIG_WINBOND_W83627 is not set
# CONFIG_FS_LOADER is not set

#
# MMC Host controller Support
#
# CONFIG_MMC is not set
# CONFIG_MMC_BROKEN_CD is not set
# CONFIG_DM_MMC is not set
# CONFIG_FSL_ESDHC is not set
# CONFIG_FSL_ESDHC_IMX is not set

#
# MTD Support
#
# CONFIG_MTD is not set
# CONFIG_DM_MTD is not set
# CONFIG_MTD_NOR_FLASH is not set
# CONFIG_FLASH_CFI_DRIVER is not set
# CONFIG_MTD_RAW_NAND is not set

#
# SPI Flash Support
#
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=0
CONFIG_SF_DEFAULT_CS=0
CONFIG_SF_DEFAULT_MODE=3
CONFIG_SF_DEFAULT_SPEED=1000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SF_DUAL_FLASH=y
# CONFIG_SPI_FLASH_ATMEL is not set
# CONFIG_SPI_FLASH_EON is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
# CONFIG_SPI_FLASH_ISSI is not set
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
# CONFIG_SPI_FLASH_DATAFLASH is not set
# CONFIG_SPL_SPI_FLASH_MTD is not set

#
# UBI support
#
# CONFIG_UBI_SILENCE_MSG is not set
# CONFIG_MTD_UBI is not set
# CONFIG_BITBANGMII is not set
# CONFIG_MV88E6352_SWITCH is not set
# CONFIG_PHYLIB is not set
# CONFIG_FSL_PFE is not set
CONFIG_DM_ETH=y
# CONFIG_NETDEVICES is not set
# CONFIG_PCI is not set

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_X86_PCH7 is not set
# CONFIG_X86_PCH9 is not set

#
# PHY Subsystem
#
# CONFIG_PHY is not set
# CONFIG_SPL_PHY is not set
# CONFIG_PHY_SUN4I_USB is not set
# CONFIG_MVEBU_COMPHY_SUPPORT is not set

#
# Pin controllers
#
# CONFIG_PINCTRL is not set

#
# Power
#
# CONFIG_ACPI_PMC is not set
# CONFIG_SPL_ACPI_PMC is not set
# CONFIG_TPL_ACPI_PMC is not set

#
# Power Domain Support
#
# CONFIG_POWER_DOMAIN is not set
# CONFIG_DM_PMIC is not set
# CONFIG_PMIC_AS3722 is not set
# CONFIG_POWER_MC34VR500 is not set
# CONFIG_DM_REGULATOR is not set
CONFIG_SUNXI_NO_PMIC=y
# CONFIG_POWER_MT6323 is not set
# CONFIG_DM_PWM is not set
# CONFIG_PWM_IMX is not set
# CONFIG_PWM_SANDBOX is not set
# CONFIG_U_QE is not set
# CONFIG_RAM is not set

#
# Remote Processor drivers
#

#
# Reset Controller Support
#
CONFIG_DM_RESET=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_HISILICON is not set
# CONFIG_DM_RNG is not set

#
# Real Time Clock
#
# CONFIG_DM_RTC is not set
# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
# CONFIG_RTC_RX8025 is not set
# CONFIG_RTC_PL031 is not set
# CONFIG_RTC_S35392A is not set
# CONFIG_RTC_MC146818 is not set
# CONFIG_RTC_M41T62 is not set
# CONFIG_SCSI is not set
# CONFIG_DM_SCSI is not set

#
# Serial drivers
#
CONFIG_BAUDRATE=115200
CONFIG_REQUIRE_SERIAL_CONSOLE=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SERIAL_PRESENT=y
CONFIG_SPL_SERIAL_PRESENT=y
CONFIG_CONS_INDEX=1
CONFIG_DM_SERIAL=y
# CONFIG_SERIAL_RX_BUFFER is not set
# CONFIG_SERIAL_SEARCH_ALL is not set
# CONFIG_ALTERA_JTAG_UART is not set
# CONFIG_ALTERA_UART is not set
# CONFIG_ARC_SERIAL is not set
# CONFIG_ATMEL_USART is not set
# CONFIG_BCM6345_SERIAL is not set
# CONFIG_COREBOOT_SERIAL is not set
# CONFIG_CORTINA_UART is not set
# CONFIG_FSL_LINFLEXUART is not set
# CONFIG_FSL_LPUART is not set
# CONFIG_MVEBU_A3700_UART is not set
# CONFIG_MCFUART is not set
# CONFIG_NULLDEV_SERIAL is not set
CONFIG_SYS_NS16550=y
# CONFIG_NS16550_DYNAMIC is not set
# CONFIG_PL01X_SERIAL is not set
# CONFIG_MSM_SERIAL is not set
# CONFIG_OMAP_SERIAL is not set
# CONFIG_PXA_SERIAL is not set
# CONFIG_SIFIVE_SERIAL is not set
# CONFIG_MTK_SERIAL is not set
# CONFIG_SMEM is not set

#
# Sound support
#
# CONFIG_SOUND is not set

#
# SOC (System On Chip) specific Drivers
#
# CONFIG_SOC_TI is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_MEM=y
# CONFIG_ALTERA_SPI is not set
# CONFIG_ATCSPI200_SPI is not set
# CONFIG_ATMEL_SPI is not set
# CONFIG_BCMSTB_SPI is not set
# CONFIG_CADENCE_QSPI is not set
# CONFIG_CF_SPI is not set
# CONFIG_DESIGNWARE_SPI is not set
# CONFIG_EXYNOS_SPI is not set
# CONFIG_FSL_DSPI is not set
# CONFIG_ICH_SPI is not set
# CONFIG_MPC8XXX_SPI is not set
# CONFIG_MTK_SNFI_SPI is not set
# CONFIG_MVEBU_A3700_SPI is not set
# CONFIG_NXP_FSPI is not set
# CONFIG_PL022_SPI is not set
# CONFIG_ROCKCHIP_SPI is not set
# CONFIG_SPI_SIFIVE is not set
CONFIG_SPI_SUNXI=y
# CONFIG_TEGRA114_SPI is not set
# CONFIG_TEGRA20_SFLASH is not set
# CONFIG_TEGRA20_SLINK is not set
# CONFIG_TEGRA210_QSPI is not set
# CONFIG_TI_QSPI is not set
# CONFIG_XILINX_SPI is not set
# CONFIG_SOFT_SPI is not set
# CONFIG_FSL_ESPI is not set
# CONFIG_FSL_QSPI is not set
# CONFIG_SH_QSPI is not set
# CONFIG_KIRKWOOD_SPI is not set
# CONFIG_MXC_SPI is not set
# CONFIG_MXS_SPI is not set
# CONFIG_OMAP3_SPI is not set

#
# SPMI support
#
# CONFIG_SPMI is not set

#
# System reset device drivers
#
# CONFIG_SYSRESET is not set
# CONFIG_SYSRESET_SYSCON is not set
# CONFIG_SYSRESET_WATCHDOG is not set
# CONFIG_SYSRESET_MPC83XX is not set
# CONFIG_TEE is not set
# CONFIG_OPTEE is not set
# CONFIG_DM_THERMAL is not set

#
# Timer Support
#
# CONFIG_TIMER is not set

#
# TPM support
#
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_DM_USB_GADGET is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_XHCI_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_OHCI_PCI is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_CDNS3 is not set
# CONFIG_USB_DWC3 is not set

#
# Legacy MUSB Support
#
# CONFIG_USB_MUSB_HCD is not set
# CONFIG_USB_MUSB_UDC is not set

#
# MUSB Controller Driver
#
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
# CONFIG_USB_MUSB_DA8XX is not set
# CONFIG_USB_MUSB_TI is not set
# CONFIG_USB_MUSB_AM35X is not set
# CONFIG_USB_MUSB_DSPS is not set
# CONFIG_USB_MUSB_PIO_ONLY is not set

#
# USB Phy
#
# CONFIG_TWL4030_USB is not set
# CONFIG_OMAP_USB_PHY is not set
# CONFIG_ROCKCHIP_USB2_PHY is not set

#
# ULPI drivers
#

#
# USB peripherals
#
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_KEYBOARD_FN_KEYS=y
# CONFIG_SYS_USB_EVENT_POLL is not set
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
# CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Allwinner Technology"
CONFIG_USB_GADGET_VENDOR_NUM=0x1f3a
CONFIG_USB_GADGET_PRODUCT_NUM=0x1010
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set
# CONFIG_USB_GADGET_DWC2_OTG is not set
# CONFIG_CI_UDC is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
# CONFIG_USB_GADGET_DOWNLOAD is not set
# CONFIG_USB_ETHER is not set
# CONFIG_USB_HOST_ETHER is not set

#
# UFS Host Controller Support
#
# CONFIG_TI_J721E_UFS is not set

#
# Graphics support
#
# CONFIG_DM_VIDEO is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_NO_FB_CLEAR is not set

#
# TrueType Fonts
#
# CONFIG_VIDEO_VESA is not set
# CONFIG_VIDEO_LCD_ANX9804 is not set
# CONFIG_VIDEO_LCD_SSD2828 is not set
# CONFIG_VIDEO_MVEBU is not set
# CONFIG_I2C_EDID is not set
# CONFIG_DISPLAY is not set
# CONFIG_VIDEO_TEGRA20 is not set
# CONFIG_VIDEO_BRIDGE is not set
# CONFIG_VIDEO is not set
# CONFIG_LCD is not set
# CONFIG_VIDEO_SIMPLE is not set
# CONFIG_VIDEO_DT_SIMPLEFB is not set
# CONFIG_OSD is not set

#
# VirtIO Drivers
#
# CONFIG_VIRTIO_MMIO is not set

#
# 1-Wire support
#
# CONFIG_W1 is not set

#
# 1-wire EEPROM support
#
# CONFIG_W1_EEPROM is not set

#
# Watchdog Timer Support
#
# CONFIG_WATCHDOG is not set
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
# CONFIG_WATCHDOG_RESET_DISABLE is not set
# CONFIG_IMX_WATCHDOG is not set
# CONFIG_ULP_WATCHDOG is not set
# CONFIG_DESIGNWARE_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_PHYS_TO_BUS is not set

#
# File systems
#
# CONFIG_FS_BTRFS is not set
# CONFIG_FS_CBFS is not set
# CONFIG_SPL_FS_CBFS is not set
CONFIG_FS_EXT4=y
# CONFIG_EXT4_WRITE is not set
CONFIG_FS_FAT=y
CONFIG_FAT_WRITE=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
# CONFIG_FS_JFFS2 is not set
# CONFIG_UBIFS_SILENCE_MSG is not set
# CONFIG_FS_CRAMFS is not set
# CONFIG_YAFFS2 is not set

#
# Library routines
#
# CONFIG_BCH is not set
CONFIG_BINMAN_FDT=y
# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
# CONFIG_DYNAMIC_CRC_TABLE is not set
CONFIG_HAVE_PRIVATE_LIBGCC=y
CONFIG_LIB_UUID=y
CONFIG_PRINTF=y
CONFIG_SPL_PRINTF=y
CONFIG_SPRINTF=y
CONFIG_SPL_SPRINTF=y
CONFIG_STRTO=y
CONFIG_SPL_STRTO=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_HZ=1000
CONFIG_SPL_USE_TINY_PRINTF=y
# CONFIG_PANIC_HANG is not set
CONFIG_REGEX=y
CONFIG_LIB_RAND=y
# CONFIG_LIB_HW_RAND is not set
# CONFIG_SPL_TINY_MEMSET is not set
# CONFIG_TPL_TINY_MEMSET is not set
# CONFIG_BITREVERSE is not set
# CONFIG_TRACE is not set
# CONFIG_CMD_DHRYSTONE is not set

#
# Security support
#
# CONFIG_AES is not set
# CONFIG_RSA is not set
# CONFIG_ASYMMETRIC_KEY_TYPE is not set
# CONFIG_TPM is not set

#
# Android Verified Boot
#

#
# Hashing Support
#
CONFIG_SHA1=y
CONFIG_SHA256=y
# CONFIG_SHA_HW_ACCEL is not set
CONFIG_MD5=y

#
# Compression Support
#
# CONFIG_LZ4 is not set
# CONFIG_LZMA is not set
# CONFIG_LZO is not set
CONFIG_GZIP=y
CONFIG_ZLIB=y
# CONFIG_ZSTD is not set
# CONFIG_SPL_LZ4 is not set
# CONFIG_SPL_LZO is not set
# CONFIG_SPL_GZIP is not set
# CONFIG_SPL_ZSTD is not set
# CONFIG_ERRNO_STR is not set
# CONFIG_HEXDUMP is not set
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_ASSUME_MASK=0
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0xff
# CONFIG_TPL_OF_LIBFDT is not set
CONFIG_TPL_OF_LIBFDT_ASSUME_MASK=0xff

#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLE=y
CONFIG_SMBIOS_MANUFACTURER=""
CONFIG_EFI_LOADER=y
CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
CONFIG_EFI_LOADER_HII=y
CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
CONFIG_EFI_UNICODE_CAPITALIZATION=y
# CONFIG_EFI_UNICODE_COLLATION_PROTOCOL is not set
CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
CONFIG_EFI_GRUB_ARM32_WORKAROUND=y
# CONFIG_EFI_LOAD_FILE2_INITRD is not set
# CONFIG_TEST_FDTDEC is not set
# CONFIG_UNIT_TEST is not set

diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
index 3d9168cbae..422b12420f 100644
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
@@ -50,6 +50,7 @@

        aliases {
                serial0 = &uart0;
+               spi0 = &spi0;
        };

        chosen {
@@ -63,11 +64,11 @@
        broken-cd;
        bus-width = <4>;
        vmmc-supply = <&reg_vcc3v3>;
-       status = "okay";
+       status = "disabled";
 };

 &uart0 {
-       pinctrl-0 = <&uart0_pins_a>;
+       pinctrl-0 = <&uart0_pins_b>;
        pinctrl-names = "default";
        status = "okay";
 };
@@ -81,3 +82,7 @@
        usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
+
+&spi0 {
+        status ="okay";
+};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index ebefc0fefe..331a276c57 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -208,12 +208,22 @@
                        interrupt-controller;
                        #interrupt-cells = <3>;

+spi0_pins: spi0 {
+        pins = "PC0", "PC1", "PC2", "PC3";
+        function = "spi0";
+};
                        uart0_pins_a: uart0@0 {
                                pins = "PB8", "PB9";
                                function = "uart0";
                                bias-pull-up;
                        };

+                       uart0_pins_b: uart0@1 {
+                               pins = "PF2", "PF4";
+                               function = "uart0";
+                               bias-pull-up;
+                       };
+
                        mmc0_pins_a: mmc0@0 {
                                pins = "PF0", "PF1", "PF2", "PF3",
                                       "PF4", "PF5";
@@ -223,6 +233,19 @@
                        };
                };

+spi0: spi@1c68000 {
+        compatible = "allwinner,sun8i-h3-spi";
+        reg = <0x01c68000 0x1000>;
+        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+        clock-names = "ahb", "mod";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+        resets = <&ccu RST_BUS_SPI0>;
+        status = "disabled";
+        #address-cells = <1>;
+        #size-cells = <0>;
+};
                timer@01c20c00 {
                        compatible = "allwinner,sun4i-a10-timer";
                        reg = <0x01c20c00 0xa0>;

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index be0822bfb7..0dfd527e34 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR

 config SPL_SPI_SUNXI
        bool "Support for SPI Flash on Allwinner SoCs in SPL"
-       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
+       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUN8I_V3S
        help
          Enable support for SPI Flash. This option allows SPL to read from
          sunxi SPI Flash. It uses the same method as the boot ROM, so does

U-Boot SPL 2020.04-dirty (Apr 28 2021 - 22:50:41 +0800)
DRAM: 64 MiB
Trying to boot from sunxi SPI


U-Boot 2020.04-dirty (Apr 28 2021 - 22:50:41 +0800) Allwinner Technology

CPU:   Allwinner V3s (SUN8I 1681)
Model: Lichee Pi Zero
DRAM:  64 MiB
Loading Environment from FAT... In:    serial@01c28000
Out:   serial@01c28000
Err:   serial@01c28000
Net:   No ethernet found.
starting USB...
No working controllers found
Hit any key to stop autoboot:  0
starting USB...
No working controllers found
USB is stopped. Please issue 'usb start' first.
starting USB...
No working controllers found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/00000000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/0000000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/000000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/00000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/0000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/000
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/00
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/0
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/default-arm-sunxi-sunxi
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/default-arm-sunxi
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/default-arm
No ethernet found.
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/default
No ethernet found.
Config file not found
starting USB...
No working controllers found
No ethernet found.
No ethernet found.
=>

=> md.l 0x01c23800 4
01c23800: 12c0000f 44104620 5033c810 5c1d130d    .... F.D..3P...\
=>

\0\0HELLO! BOOT0 is starting!
get_ifm reg_val=7

===i2c gpio === 22777722 
axp read fail, maybe no pmu 
set pmu vol failed,maybe no pmu 
DRAM DRIVE INFO: V0.7
DRAM Type = 2 (2:DDR2,3:DDR3,6:LPDDR2,7:LPDDR3)
DRAM CLK = 408 MHz
DRAM zq value: 000039bb
DRAM size = 64 MB
Succeed in reading Boot1 file head.
Jump to secend Boot.
[      0.092]

U-Boot 2011.09-rc1-00001-g09357ae (Mar 18 2016 - 20:22:11) Allwinner Technology 

[      0.101]version: 1.1.0
[      0.107]pmbus:   
===i2c gpio === 22777722 
ready
pmu_type = 5
[      0.218]PMU: AXP152
[      0.220]PMU: AXP15x found
the set_vol is 1800 
set power on vol to default
axp_set_power_supply_output dcdc1_vol = 3300
the reg_vlaue is ffaxp_set_power_supply_output dcdc2_vol = 1100
the vol is 1250
the vol is 1225
the vol is 1200
the vol is 1175
the vol is 1150
the vol is 1125
the vol is 1100
axp_set_power_supply_output dcdc3_vol = 1800
the set_vol is 1800 
axp_set_power_supply_output dcdc4_vol = 1800
axp_set_power_supply_output aldo1_vol = 3000
axp_set_power_supply_output aldo2_vol = 3000
axp_set_power_supply_output dldo1_vol = 3000
fel key new mode
run key detect
no key found
[      0.490]DRAM:  64 MiB
save config for small mem_size 
[debug_jaosn]:use the clock in sys_config 
OK
[      0.514]sunxi flash init ok
hello @flash_speed=1
env_relocate_spec storage_type = 3
In:    serial
Out:   serial
Err:   serial
bootcmd set setargs_nor
WORK_MODE_BOOT
read bootlogo partition fail,start_block=0x0,rblock=0x0 ,ret=0
Not a JPG file ?
parse_header failed

Use decode 2x1 sampling
sunxi_read_bootlogo: jpg convert argb  
[      0.550]Hit any key to stop autoboot:  0 
read boot or recovery all
[      0.732]sunxi flash read :offset 4000, 2621951 bytes OK
[      0.737]ready to boot
reload config to 0x43000000 
[      0.740]
Starting kernel ...

# i2cdump -y 0 0x30
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 31 00 05 00 00 00 00 00 00 00 00 00 00 00 00    .1.?............
10: 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
20: 00 00 00 16 00 00 0d 16 c0 15 0b 16 00 00 00 00    ...?..??????....
30: 00 07 00 00 00 00 9d 08 00 00 00 00 00 00 00 00    .?....??........
40: 00 03 00 00 00 00 00 00 48 00 00 00 00 00 00 00    .?......H.......
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: f0 fd 00 00 00 00 00 00 00 00 00 00 00 00 00 01    ??.............?
90: 07 07 07 07 00 00 0a 00 00 16 0b 00 16 0b 00 00    ????..?..??.??..
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00    ?.?.............

#初始化摄像头:

#PE17 GC0403 PWR
echo 145 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio145/direction
#低电平正常工作
echo 0 > /sys/class/gpio/gpio145/value

#PE16 GC0403 RESET
echo 144 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio144/direction
echo 0 > /sys/class/gpio/gpio144/value
sleep 0.1
echo 1 > /sys/class/gpio/gpio144/value

# i2cdetect -y 1
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: UU -- -- -- -- -- -- -- -- -- -- -- 3c -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --

&csi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&csi1_8bit_pins>;
	status = "okay";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		csi1_ep: endpoint {
			remote-endpoint = <&gc0403_ep>;
			bus-width = <8>;                              // number of data lines actively used, valid for the parallel busses.
			hsync-active = <1>;                           // active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
			vsync-active = <0>;                           // active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
			data-active = <1>;                            // similar to HSYNC and VSYNC, specifies data line polarity.
			pclk-sample = <1>;                            // sample data on rising (1) or falling (0) edge of the pixel clock signal.
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pe_pins>;
	status = "okay";
		
	gc0403: camera@78 {
		compatible = "galaxycore,gc0403";
		reg = <0x78>;
		pinctrl-names = "default";
		pinctrl-0 = <&csi1_mclk_pin>;
		clocks = <&ccu CLK_CSI1_MCLK>;
		clock-names = "xvclk";
		pwdn-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */
		
		port {mm
			gc0403_ep: endpoint {
				remote-endpoint = <&csi1_ep>;
				bus-width = <8>;                              // number of data lines actively used, valid for the parallel busses.
				hsync-active = <1>;                           // active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
				vsync-active = <0>;                           // active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
				data-active = <1>;                            // similar to HSYNC and VSYNC, specifies data line polarity.
				pclk-sample = <1>;                            // sample data on rising (1) or falling (0) edge of the pixel clock signal.
			};
		};
	};

			csi1_8bit_pins: csi1-8bit-pins {
				pins = "PE0", "PE2", "PE3", "PE8", "PE9",                      // PCLK, HSYNK, VSYNK, D4, D5, 
				       "PE10", "PE11", "PE12", "PE13", "PE14",                 // D6, D7, D8, D9, D10
				       "PE15";                                                 // D11
				function = "csi";
			};

			csi1_mclk_pin: csi1-mclk-pin {
				pins = "PE20";                                                   // MCLK
				function = "csi";
			};

sd->entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV;

sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;

 [    0.854870][    T1] gc0403 0-003c: Detected GC0403 sensor