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楼主 # 2021-11-01 17:41:21

xboot
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XFEL已支持spi nand flash烧写

xfel工具很早就支持了spi nor flash的读写,但spi nand flash的支持一直没提上日程,考虑到F133,D1s的玩家越来越多,这个spi nand flash的支持就迫在眉睫了。经过几天的开发设计,spi nand flash的支持基本完成了。下面是支持的spi nand芯片列表,已经算是尽我所能,找到最全的芯片列表了。当然现在仅测试过MX35LF2GE4AD这颗,其他芯片的验证在遇到具体问题后,再进行调试了。

	/* Gigadevice */
	{ "GD5F1GQ4UAWxx",   0xc810, 2048,  64,  64, 1024, 1, 1 },
	{ "GD5F1GQ4UExIG",   0xc8d1, 2048, 128,  64, 1024, 1, 1 },
	{ "GD5F1GQ4UExxH",   0xc8d9, 2048,  64,  64, 1024, 1, 1 },
	{ "GD5F1GQ4xAYIG",   0xc8f1, 2048,  64,  64, 1024, 1, 1 },
	{ "GD5F2GQ4UExIG",   0xc8d2, 2048, 128,  64, 2048, 1, 1 },
	{ "GD5F2GQ5UExxH",   0xc832, 2048,  64,  64, 2048, 1, 1 },
	{ "GD5F2GQ4xAYIG",   0xc8f2, 2048,  64,  64, 2048, 1, 1 },
	{ "GD5F4GQ4UBxIG",   0xc8d4, 4096, 256,  64, 2048, 1, 1 },
	{ "GD5F4GQ4xAYIG",   0xc8f4, 2048,  64,  64, 4096, 1, 1 },
	{ "GD5F2GQ5UExxG",   0xc852, 2048, 128,  64, 2048, 1, 1 },
	{ "GD5F4GQ4UCxIG",   0xc8b4, 4096, 256,  64, 2048, 1, 1 },

	/* Macronix */
	{ "MX35LF1GE4AB",    0xc212, 2048,  64,  64, 1024, 1, 1 },
	{ "MX35LF1G24AD",    0xc214, 2048, 128,  64, 1024, 1, 1 },
	{ "MX31LF1GE4BC",    0xc21e, 2048,  64,  64, 1024, 1, 1 },
	{ "MX35LF2GE4AB",    0xc222, 2048,  64,  64, 2048, 1, 1 },
	{ "MX35LF2G24AD",    0xc224, 2048, 128,  64, 2048, 1, 1 },
	{ "MX35LF2GE4AD",    0xc226, 2048, 128,  64, 2048, 1, 1 },
	{ "MX35LF2G14AC",    0xc220, 2048,  64,  64, 2048, 1, 1 },
	{ "MX35LF4G24AD",    0xc235, 4096, 256,  64, 2048, 1, 1 },
	{ "MX35LF4GE4AD",    0xc237, 4096, 256,  64, 2048, 1, 1 },

	/* Micron */
	{ "MT29F1G01AAADD",  0x2c12, 2048,  64,  64, 1024, 1, 1 },
	{ "MT29F1G01ABAFD",  0x2c14, 2048, 128,  64, 1024, 1, 1 },
	{ "MT29F2G01AAAED",  0x2c9f, 2048,  64,  64, 2048, 2, 1 },
	{ "MT29F2G01ABAGD",  0x2c24, 2048, 128,  64, 2048, 2, 1 },
	{ "MT29F4G01AAADD",  0x2c32, 2048,  64,  64, 4096, 2, 1 },
	{ "MT29F4G01ABAFD",  0x2c34, 4096, 256,  64, 2048, 1, 1 },
	{ "MT29F4G01ADAGD",  0x2c36, 2048, 128,  64, 2048, 2, 2 },
	{ "MT29F8G01ADAFD",  0x2c46, 4096, 256,  64, 2048, 1, 2 },

	/* Toshiba */
	{ "TC58CVG0S3HRAIG", 0x98c2, 2048, 128,  64, 1024, 1, 1 },
	{ "TC58CVG1S3HRAIG", 0x98cb, 2048, 128,  64, 2048, 1, 1 },
	{ "TC58CVG2S0HRAIG", 0x98cd, 4096, 256,  64, 2048, 1, 1 },
	{ "TC58CVG0S3HRAIJ", 0x98e2, 2048, 128,  64, 1024, 1, 1 },
	{ "TC58CVG1S3HRAIJ", 0x98eb, 2048, 128,  64, 2048, 1, 1 },
	{ "TC58CVG2S0HRAIJ", 0x98ed, 4096, 256,  64, 2048, 1, 1 },
	{ "TH58CVG3S0HRAIJ", 0x98e4, 4096, 256,  64, 4096, 1, 1 },

	/* Esmt */
	{ "F50L512M41A",     0xc820, 2048,  64,  64,  512, 1, 1 },
	{ "F50L1G41A",       0xc821, 2048,  64,  64, 1024, 1, 1 },
	{ "F50L1G41LB",      0xc801, 2048,  64,  64, 1024, 1, 1 },
	{ "F50L2G41LB",      0xc80a, 2048,  64,  64, 1024, 1, 2 },

	/* Fison */
	{ "CS11G0T0A0AA",    0x6b00, 2048, 128,  64, 1024, 1, 1 },
	{ "CS11G0G0A0AA",    0x6b10, 2048, 128,  64, 1024, 1, 1 },
	{ "CS11G0S0A0AA",    0x6b20, 2048,  64,  64, 1024, 1, 1 },
	{ "CS11G1T0A0AA",    0x6b01, 2048, 128,  64, 2048, 1, 1 },
	{ "CS11G1S0A0AA",    0x6b21, 2048,  64,  64, 2048, 1, 1 },
	{ "CS11G2T0A0AA",    0x6b02, 2048, 128,  64, 4096, 1, 1 },
	{ "CS11G2S0A0AA",    0x6b22, 2048,  64,  64, 4096, 1, 1 },

	/* Etron */
	{ "EM73B044VCA",     0xd501, 2048,  64,  64,  512, 1, 1 },
	{ "EM73C044SNB",     0xd511, 2048, 120,  64, 1024, 1, 1 },
	{ "EM73C044SNF",     0xd509, 2048, 128,  64, 1024, 1, 1 },
	{ "EM73C044VCA",     0xd518, 2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SNA",     0xd519, 2048,  64, 128,  512, 1, 1 },
	{ "EM73C044VCD",     0xd51c, 2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SND",     0xd51d, 2048,  64,  64, 1024, 1, 1 },
	{ "EM73D044SND",     0xd51e, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73C044VCC",     0xd522, 2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044VCF",     0xd525, 2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SNC",     0xd531, 2048, 128,  64, 1024, 1, 1 },
	{ "EM73D044SNC",     0xd50a, 2048, 120,  64, 2048, 1, 1 },
	{ "EM73D044SNA",     0xd512, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044SNF",     0xd510, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCA",     0xd513, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCB",     0xd514, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCD",     0xd517, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCH",     0xd51b, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044SND",     0xd51d, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCG",     0xd51f, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCE",     0xd520, 2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCL",     0xd52e, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044SNB",     0xd532, 2048, 128,  64, 2048, 1, 1 },
	{ "EM73E044SNA",     0xd503, 4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044SND",     0xd50b, 4096, 240,  64, 2048, 1, 1 },
	{ "EM73E044SNB",     0xd523, 4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044VCA",     0xd52c, 4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044VCB",     0xd52f, 2048, 128,  64, 4096, 1, 1 },
	{ "EM73F044SNA",     0xd524, 4096, 256,  64, 4096, 1, 1 },
	{ "EM73F044VCA",     0xd52d, 4096, 256,  64, 4096, 1, 1 },
	{ "EM73E044SNE",     0xd50e, 4096, 256,  64, 4096, 1, 1 },
	{ "EM73C044SNG",     0xd50c, 2048, 120,  64, 1024, 1, 1 },
	{ "EM73D044VCN",     0xd50f, 2048,  64,  64, 2048, 1, 1 },

	/* Elnec */
	{ "FM35Q1GA",        0xe571, 2048,  64,  64, 1024, 1, 1 },

	/* Paragon */
	{ "PN26G01A",        0xa1e1, 2048, 128,  64, 1024, 1, 1 },
	{ "PN26G02A",        0xa1e2, 2048, 128,  64, 2048, 1, 1 },

	/* Ato */
	{ "ATO25D1GA",       0x9b12, 2048,  64,  64, 1024, 1, 1 },

	/* Heyang */
	{ "HYF1GQ4U",        0xc951, 2048, 128,  64, 1024, 1, 1 },
	{ "HYF2GQ4U",        0xc952, 2048, 128,  64, 2048, 1, 1 },

https://github.com/xboot/xfel

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#1 2021-11-01 21:23:10

mango
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Re: XFEL已支持spi nand flash烧写

大佬v5,我尽快测试MQ

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#2 2021-11-02 09:21:19

微凉VeiLiang
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Re: XFEL已支持spi nand flash烧写

感谢大佬又解决了一个问题,越来越方便了

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#3 2021-11-02 09:50:24

armstrong
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Re: XFEL已支持spi nand flash烧写

感谢xman

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#4 2021-11-02 10:10:02

aozima
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Re: XFEL已支持spi nand flash烧写

大佬一个人顶一个团队!

想让xfel支持SD卡读写,可行不?从哪下手?想尝试下!

最近编辑记录 aozima (2021-11-03 08:49:21)

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#5 2021-11-03 10:09:20

小王子&木头人
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Re: XFEL已支持spi nand flash烧写

支持一个 再做一回spi nand伸手党

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#6 2021-11-03 10:54:59

armstrong
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Re: XFEL已支持spi nand flash烧写

aozima 说:

大佬一个人顶一个团队!

想让xfel支持SD卡读写,可行不?从哪下手?想尝试下!

从xfel源码入手,是电脑和MCU沟通的桥梁。

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楼主 #7 2021-11-03 11:07:16

xboot
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Re: XFEL已支持spi nand flash烧写

写sd卡,貌似直接用读卡器插在电脑上更方便点。如果是Emmc的话,那还是有意义的,思路就是写个sdio的payload,然后通过xfel传输到ram中执行,有了sdio的读写,你就可以基于读写接口操作EMMC了,具体例子可以查看xfel的payload目录,参考里面的spi payload实现,模仿就可以了。

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#8 2021-11-03 11:45:27

aozima
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Re: XFEL已支持spi nand flash烧写

对的,焊在板子上面不方便拔下来,虽然慢些,但能用还是方便。

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楼主 #9 2021-11-03 13:51:13

xboot
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Re: XFEL已支持spi nand flash烧写

对于贴在板子上的SD卡,还有一种方案,就是用xfel运行一个小系统,可以是uboot或者linux之类的,然后在里面开启ums功能,这样PC上就可以刷SD卡了,而且速度还快。

最近编辑记录 xboot (2021-11-03 13:51:26)

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#10 2021-11-03 22:59:08

哇酷小二
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Re: XFEL已支持spi nand flash烧写

armstrong 说:

感谢xman

嗯,xman,笑出声 ^_^


xboot 说:

对于贴在板子上的SD卡,还有一种方案,就是用xfel运行一个小系统,可以是uboot或者linux之类的,然后在里面开启ums功能,这样PC上就可以刷SD卡了,而且速度还快。

这个方案好!

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#11 2021-11-08 16:45:43

memory
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Re: XFEL已支持spi nand flash烧写

测试了一下, 目前还不支持A33 FLASH 读写?

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楼主 #12 2021-11-08 18:32:41

xboot
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Re: XFEL已支持spi nand flash烧写

A33还没有payload代码,如果有硬件的话,模仿个V3S的payload就差不多了。

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楼主 #13 2021-11-08 18:33:00

xboot
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Re: XFEL已支持spi nand flash烧写

A33应该就是R16

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#14 2021-11-08 18:36:23

memory
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Re: XFEL已支持spi nand flash烧写

xboot 说:

A33应该就是R16

对,A33 == R16 == X3(SIP 128M)

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楼主 #15 2021-11-09 09:23:36

xboot
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Re: XFEL已支持spi nand flash烧写

因为华邦的spi nand id是3个字节,而绝大部分spi nand id是两个字节,这里扩展了ID的匹配策略,现在支持华邦的spi nand flash了,最新的支持列表如下:

	/* Winbond */
	{ "W25N512GV",       SPINAND_ID(0xef, 0xaa, 0x20), 2048,  64,  64,  512, 1, 1 },
	{ "W25N01GV",        SPINAND_ID(0xef, 0xaa, 0x21), 2048,  64,  64, 1024, 1, 1 },
	{ "W25M02GV",        SPINAND_ID(0xef, 0xab, 0x21), 2048,  64,  64, 1024, 1, 2 },
	{ "W25N02KV",        SPINAND_ID(0xef, 0xaa, 0x22), 2048, 128,  64, 2048, 1, 1 },

	/* Gigadevice */
	{ "GD5F1GQ4UAWxx",   SPINAND_ID(0xc8, 0x10),       2048,  64,  64, 1024, 1, 1 },
	{ "GD5F1GQ4UExIG",   SPINAND_ID(0xc8, 0xd1),       2048, 128,  64, 1024, 1, 1 },
	{ "GD5F1GQ4UExxH",   SPINAND_ID(0xc8, 0xd9),       2048,  64,  64, 1024, 1, 1 },
	{ "GD5F1GQ4xAYIG",   SPINAND_ID(0xc8, 0xf1),       2048,  64,  64, 1024, 1, 1 },
	{ "GD5F2GQ4UExIG",   SPINAND_ID(0xc8, 0xd2),       2048, 128,  64, 2048, 1, 1 },
	{ "GD5F2GQ5UExxH",   SPINAND_ID(0xc8, 0x32),       2048,  64,  64, 2048, 1, 1 },
	{ "GD5F2GQ4xAYIG",   SPINAND_ID(0xc8, 0xf2),       2048,  64,  64, 2048, 1, 1 },
	{ "GD5F4GQ4UBxIG",   SPINAND_ID(0xc8, 0xd4),       4096, 256,  64, 2048, 1, 1 },
	{ "GD5F4GQ4xAYIG",   SPINAND_ID(0xc8, 0xf4),       2048,  64,  64, 4096, 1, 1 },
	{ "GD5F2GQ5UExxG",   SPINAND_ID(0xc8, 0x52),       2048, 128,  64, 2048, 1, 1 },
	{ "GD5F4GQ4UCxIG",   SPINAND_ID(0xc8, 0xb4),       4096, 256,  64, 2048, 1, 1 },

	/* Macronix */
	{ "MX35LF1GE4AB",    SPINAND_ID(0xc2, 0x12),       2048,  64,  64, 1024, 1, 1 },
	{ "MX35LF1G24AD",    SPINAND_ID(0xc2, 0x14),       2048, 128,  64, 1024, 1, 1 },
	{ "MX31LF1GE4BC",    SPINAND_ID(0xc2, 0x1e),       2048,  64,  64, 1024, 1, 1 },
	{ "MX35LF2GE4AB",    SPINAND_ID(0xc2, 0x22),       2048,  64,  64, 2048, 1, 1 },
	{ "MX35LF2G24AD",    SPINAND_ID(0xc2, 0x24),       2048, 128,  64, 2048, 1, 1 },
	{ "MX35LF2GE4AD",    SPINAND_ID(0xc2, 0x26),       2048, 128,  64, 2048, 1, 1 },
	{ "MX35LF2G14AC",    SPINAND_ID(0xc2, 0x20),       2048,  64,  64, 2048, 1, 1 },
	{ "MX35LF4G24AD",    SPINAND_ID(0xc2, 0x35),       4096, 256,  64, 2048, 1, 1 },
	{ "MX35LF4GE4AD",    SPINAND_ID(0xc2, 0x37),       4096, 256,  64, 2048, 1, 1 },

	/* Micron */
	{ "MT29F1G01AAADD",  SPINAND_ID(0x2c, 0x12),       2048,  64,  64, 1024, 1, 1 },
	{ "MT29F1G01ABAFD",  SPINAND_ID(0x2c, 0x14),       2048, 128,  64, 1024, 1, 1 },
	{ "MT29F2G01AAAED",  SPINAND_ID(0x2c, 0x9f),       2048,  64,  64, 2048, 2, 1 },
	{ "MT29F2G01ABAGD",  SPINAND_ID(0x2c, 0x24),       2048, 128,  64, 2048, 2, 1 },
	{ "MT29F4G01AAADD",  SPINAND_ID(0x2c, 0x32),       2048,  64,  64, 4096, 2, 1 },
	{ "MT29F4G01ABAFD",  SPINAND_ID(0x2c, 0x34),       4096, 256,  64, 2048, 1, 1 },
	{ "MT29F4G01ADAGD",  SPINAND_ID(0x2c, 0x36),       2048, 128,  64, 2048, 2, 2 },
	{ "MT29F8G01ADAFD",  SPINAND_ID(0x2c, 0x46),       4096, 256,  64, 2048, 1, 2 },

	/* Toshiba */
	{ "TC58CVG0S3HRAIG", SPINAND_ID(0x98, 0xc2),       2048, 128,  64, 1024, 1, 1 },
	{ "TC58CVG1S3HRAIG", SPINAND_ID(0x98, 0xcb),       2048, 128,  64, 2048, 1, 1 },
	{ "TC58CVG2S0HRAIG", SPINAND_ID(0x98, 0xcd),       4096, 256,  64, 2048, 1, 1 },
	{ "TC58CVG0S3HRAIJ", SPINAND_ID(0x98, 0xe2),       2048, 128,  64, 1024, 1, 1 },
	{ "TC58CVG1S3HRAIJ", SPINAND_ID(0x98, 0xeb),       2048, 128,  64, 2048, 1, 1 },
	{ "TC58CVG2S0HRAIJ", SPINAND_ID(0x98, 0xed),       4096, 256,  64, 2048, 1, 1 },
	{ "TH58CVG3S0HRAIJ", SPINAND_ID(0x98, 0xe4),       4096, 256,  64, 4096, 1, 1 },

	/* Esmt */
	{ "F50L512M41A",     SPINAND_ID(0xc8, 0x20),       2048,  64,  64,  512, 1, 1 },
	{ "F50L1G41A",       SPINAND_ID(0xc8, 0x21),       2048,  64,  64, 1024, 1, 1 },
	{ "F50L1G41LB",      SPINAND_ID(0xc8, 0x01),       2048,  64,  64, 1024, 1, 1 },
	{ "F50L2G41LB",      SPINAND_ID(0xc8, 0x0a),       2048,  64,  64, 1024, 1, 2 },

	/* Fison */
	{ "CS11G0T0A0AA",    SPINAND_ID(0x6b, 0x00),       2048, 128,  64, 1024, 1, 1 },
	{ "CS11G0G0A0AA",    SPINAND_ID(0x6b, 0x10),       2048, 128,  64, 1024, 1, 1 },
	{ "CS11G0S0A0AA",    SPINAND_ID(0x6b, 0x20),       2048,  64,  64, 1024, 1, 1 },
	{ "CS11G1T0A0AA",    SPINAND_ID(0x6b, 0x01),       2048, 128,  64, 2048, 1, 1 },
	{ "CS11G1S0A0AA",    SPINAND_ID(0x6b, 0x21),       2048,  64,  64, 2048, 1, 1 },
	{ "CS11G2T0A0AA",    SPINAND_ID(0x6b, 0x02),       2048, 128,  64, 4096, 1, 1 },
	{ "CS11G2S0A0AA",    SPINAND_ID(0x6b, 0x22),       2048,  64,  64, 4096, 1, 1 },

	/* Etron */
	{ "EM73B044VCA",     SPINAND_ID(0xd5, 0x01),       2048,  64,  64,  512, 1, 1 },
	{ "EM73C044SNB",     SPINAND_ID(0xd5, 0x11),       2048, 120,  64, 1024, 1, 1 },
	{ "EM73C044SNF",     SPINAND_ID(0xd5, 0x09),       2048, 128,  64, 1024, 1, 1 },
	{ "EM73C044VCA",     SPINAND_ID(0xd5, 0x18),       2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SNA",     SPINAND_ID(0xd5, 0x19),       2048,  64, 128,  512, 1, 1 },
	{ "EM73C044VCD",     SPINAND_ID(0xd5, 0x1c),       2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SND",     SPINAND_ID(0xd5, 0x1d),       2048,  64,  64, 1024, 1, 1 },
	{ "EM73D044SND",     SPINAND_ID(0xd5, 0x1e),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73C044VCC",     SPINAND_ID(0xd5, 0x22),       2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044VCF",     SPINAND_ID(0xd5, 0x25),       2048,  64,  64, 1024, 1, 1 },
	{ "EM73C044SNC",     SPINAND_ID(0xd5, 0x31),       2048, 128,  64, 1024, 1, 1 },
	{ "EM73D044SNC",     SPINAND_ID(0xd5, 0x0a),       2048, 120,  64, 2048, 1, 1 },
	{ "EM73D044SNA",     SPINAND_ID(0xd5, 0x12),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044SNF",     SPINAND_ID(0xd5, 0x10),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCA",     SPINAND_ID(0xd5, 0x13),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCB",     SPINAND_ID(0xd5, 0x14),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCD",     SPINAND_ID(0xd5, 0x17),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044VCH",     SPINAND_ID(0xd5, 0x1b),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044SND",     SPINAND_ID(0xd5, 0x1d),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCG",     SPINAND_ID(0xd5, 0x1f),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCE",     SPINAND_ID(0xd5, 0x20),       2048,  64,  64, 2048, 1, 1 },
	{ "EM73D044VCL",     SPINAND_ID(0xd5, 0x2e),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73D044SNB",     SPINAND_ID(0xd5, 0x32),       2048, 128,  64, 2048, 1, 1 },
	{ "EM73E044SNA",     SPINAND_ID(0xd5, 0x03),       4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044SND",     SPINAND_ID(0xd5, 0x0b),       4096, 240,  64, 2048, 1, 1 },
	{ "EM73E044SNB",     SPINAND_ID(0xd5, 0x23),       4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044VCA",     SPINAND_ID(0xd5, 0x2c),       4096, 256,  64, 2048, 1, 1 },
	{ "EM73E044VCB",     SPINAND_ID(0xd5, 0x2f),       2048, 128,  64, 4096, 1, 1 },
	{ "EM73F044SNA",     SPINAND_ID(0xd5, 0x24),       4096, 256,  64, 4096, 1, 1 },
	{ "EM73F044VCA",     SPINAND_ID(0xd5, 0x2d),       4096, 256,  64, 4096, 1, 1 },
	{ "EM73E044SNE",     SPINAND_ID(0xd5, 0x0e),       4096, 256,  64, 4096, 1, 1 },
	{ "EM73C044SNG",     SPINAND_ID(0xd5, 0x0c),       2048, 120,  64, 1024, 1, 1 },
	{ "EM73D044VCN",     SPINAND_ID(0xd5, 0x0f),       2048,  64,  64, 2048, 1, 1 },

	/* Elnec */
	{ "FM35Q1GA",        SPINAND_ID(0xe5, 0x71),       2048,  64,  64, 1024, 1, 1 },

	/* Paragon */
	{ "PN26G01A",        SPINAND_ID(0xa1, 0xe1),       2048, 128,  64, 1024, 1, 1 },
	{ "PN26G02A",        SPINAND_ID(0xa1, 0xe2),       2048, 128,  64, 2048, 1, 1 },

	/* Ato */
	{ "ATO25D1GA",       SPINAND_ID(0x9b, 0x12),       2048,  64,  64, 1024, 1, 1 },

	/* Heyang */
	{ "HYF1GQ4U",        SPINAND_ID(0xc9, 0x51),       2048, 128,  64, 1024, 1, 1 },
	{ "HYF2GQ4U",        SPINAND_ID(0xc9, 0x52),       2048, 128,  64, 2048, 1, 1 },

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#16 2021-11-14 04:24:49

sunxiang
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Re: XFEL已支持spi nand flash烧写

@xboot
大佬,我在使用F1C200S烧写SPI-NAND-FLASH的过程中出现了,一开始是2MB的速度烧写,到百分之一百的时候突然就又跳到百分之0,这个时候烧写速度就变成了33.33kb/s,后面显示需要大约60分钟。
出现这个问题的原因大概是什么,好困惑。

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#17 2021-11-14 04:29:44

sunxiang
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Re: XFEL已支持spi nand flash烧写

一开始是
2MB/s       ETA 0:32
然后烧到100%就又回到0%
33.33KB/s ETA  62:03

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楼主 #18 2021-11-14 08:34:27

xboot
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Re: XFEL已支持spi nand flash烧写

flash 写入时现在分为两个部分,第一个进度条是擦除进度条,第二个进度条是写入进度条,做了分离处理。注意擦除区域会按最小擦除块来擦,会覆盖到所有待写区域。

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楼主 #19 2021-11-14 08:40:16

xboot
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Re: XFEL已支持spi nand flash烧写

你通过spi 直接写入128M,按照33KB/s,差不多就是一个小时,现象都是正常的。

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#20 2021-11-14 09:36:28

sunxiang
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Re: XFEL已支持spi nand flash烧写

xboot 说:

你通过spi 直接写入128M,按照33KB/s,差不多就是一个小时,现象都是正常的。

我知道了,大佬。那个全志官方的烧写,就是那个phoenixSuit烧V3S的BSP,和xfel都是usb,不知道官方那个为什么那么快,还是说官方有什么捷径没有告诉我们,嘻嘻?

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#21 2021-11-14 09:44:48

tigger
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Re: XFEL已支持spi nand flash烧写

@sunxiang
官方那个是先下载一个uboot进去烧吧,可以利用整片DDR?

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楼主 #22 2021-11-14 11:35:57

xboot
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Re: XFEL已支持spi nand flash烧写

phoenixSuit具体有没有使用整片DDR,这个是不清楚的,但可以肯定phoenixSuit一定是加载了一个小loader,可能就是利用uboot,然后再去烧录的,肯定不是纯粹的fel模式烧录的,这个跟你在uboot里启动一个fastboot,然后用fastboot来烧录是类似的。效率肯定高很多。

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#23 2021-12-19 08:54:58

yang_AE86
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Re: XFEL已支持spi nand flash烧写

@xboot
xboot大佬,请问有xfel支持贴片TF卡烧写的计划吗

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楼主 #24 2021-12-20 12:14:40

xboot
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Re: XFEL已支持spi nand flash烧写

烧录tf这个就没有计划支持了,主要原因还是通过fel协议写入大镜像效率不会太高,很有可能是无法忍受的,所以意义也不大。当然真有这种需求也是可以通过用xfel烧录一个特制的uboot到ram中来实现,比如ums,fastoot,dfu等,这个难度不大,基本研究一下uboot就能搞出来.

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#25 2021-12-28 19:23:14

byron1784
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Re: XFEL已支持spi nand flash烧写

V3s  SPI-NAND   两个问题:
1. 烧入失败率极高,5次,只有一次成功
usb bulk send error=================                  ] 49.975 KB/s, ETA 03:56

2. 烧入后运行不起来。
    U-BOOT  2021版的
    设置了SPI-NAND Boot
    bootcmd 用过 mtd  sf   nand   都不行

有大佬救命么

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#26 2021-12-28 20:59:00

忘忘大礼包
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Re: XFEL已支持spi nand flash烧写

该评论内容与本帖子无关,鼓励各位坑友积极发言讨论与帖子有关的内容!

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楼主 #27 2021-12-29 09:05:07

xboot
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Re: XFEL已支持spi nand flash烧写

@byron1784

估计是你USB线缆相关问题,换好点的线材。

spi nand flash 引导对于xboot用如下命令:

烧写普通镜像到SPI Nand Flash

sudo xfel spinand splwrite 2048 1048576 xboot.bin

烧写压缩镜像到SPI Nand Flash

sudo xfel spinand splwrite 2048 1048576 xboot.bin.z

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#28 2022-01-10 23:28:46

aozima
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Re: XFEL已支持spi nand flash烧写

F133上面调fel直接加载linux,费了几天是调好了。但linux运行并起U盘费了几天也没好。

所以继续回来折腾fel sd,搞了2天终于是通了,虽然速度只有45KB。
明天整理下发个PR,欢迎入坑。

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楼主 #29 2022-01-12 11:37:13

xboot
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Re: XFEL已支持spi nand flash烧写

看到pull request了,统筹考虑一下,再合并进去。再探讨一个问题,xfel是否需要增加一个命令,在fel模式下,通过otg口,将芯片变成一个U盘呢,就是xfel内置U盘Payload,这种需求有必要考虑吗?

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#30 2022-01-12 12:10:29

aozima
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Re: XFEL已支持spi nand flash烧写

>xfel内置U盘Payload

可以啊,有这个好像SD命令可以不要了。
最好能支持高速USB,现在USB只跑12M太慢了。
FLASH因写写入擦除速度的原因,12M是够用了,但用来接SD或EMMC就不够用了。

或也可以保留。
因为win下面无法访问物理扇区,用win32diskimage,在没分区的时候,是可以访问物理0地址的。
但分了区,就会因分区的原因,无法访问高地址的内容。把分区删除掉,就能又访问物理0地址了。

还是linux dd爽。

最近编辑记录 aozima (2022-01-12 12:11:54)

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楼主 #31 2022-01-12 13:37:06

xboot
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Re: XFEL已支持spi nand flash烧写

我先研究下ums功能,看带宽能有多快,对于45KB的SD命令,总觉得是个残缺,实用性有限。

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楼主 #32 2022-01-12 16:54:22

xboot
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Re: XFEL已支持spi nand flash烧写

发现了一个机关,全志烧录工具,本质上是利用FES模式,FES模式是uboot提供的一个命令,叫做sprite_test,当你手动执行这个命令时,就可以进入FES模式,或者改变get_boot_work_mode函数的返回值为WORK_MODE_USB_PRODUCT,则uboot启动时会自动运行sprite_test命令进入FES模式。FES模式下的USB传输协议与FEL基本一致,一些命令的ID做了改变,并扩展了FLASH相关的指令,也就是说,XFEL仅需增加对FES模式的支持后,就可以实现实现flash烧写了。而且,FES模式下FES_PLATFORM_HW_ID永远是0x00161000,不管是哪种芯片。

FES,FEL模式公共命令:

#define APP_LAYER_COMMEN_CMD_VERIFY_DEV			0x0001
#define APP_LAYER_COMMEN_CMD_SWITCH_ROLE		0x0002
#define APP_LAYER_COMMEN_CMD_IS_READY			0x0003
#define APP_LAYER_COMMEN_CMD_GET_CMD_SET_VER 	0x0004
#define APP_LAYER_COMMEN_CMD_DISCONNECT			0x0010

FES模式特有的命令:

#define	FEX_CMD_fes_trans						0x0201
#define	FEX_CMD_fes_run 						0x0202
#define FEX_CMD_fes_down						0x0206
#define FEX_CMD_fes_up	    					0x0207
#define FEX_CMD_fes_verify    					0x0208
#define FEX_CMD_fes_query_storage				0x0209
#define FEX_CMD_fes_probe_hardware  			0x020A
#define FEX_CMD_fes_flash_set_on				0x020A
#define FEX_CMD_fes_flash_set_off				0x020B
#define FEX_CMD_fes_verify_value    			0x020C
#define FEX_CMD_fes_verify_status   			0x020D
#define FEX_CMD_fes_flash_size_probe			0x020E
#define FEX_CMD_fes_tool_mode					0x020F
#define FEX_CMD_fes_memset                      0x0210
#define FEX_CMD_fes_pmu                         0x0211
#define FEX_CMD_fes_unseqmem_read   			0x0212
#define FEX_CMD_fes_unseqmem_write  			0x0213
#define FEX_CMD_fes_force_erase                 0x0220
#define FEX_CMD_fes_force_erase_key             0x0221
#define FEX_CMD_fes_reset_cpu					0x0214
#define FEX_CMD_fes_low_power_manger 			0x0215
#define FEX_CMD_fes_query_secure                0x0230
#define FEX_CMD_fes_query_info               0x0231

理论上是可以实现用xfel来烧录全志image的,也就是说可以代替全志的PhoenixSuit工具的,但这个工作有多大意义就得打个问号了。

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楼主 #33 2022-01-12 19:51:14

xboot
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Re: XFEL已支持spi nand flash烧写

UMS功能在D1上实验失败,不管是官方uboot还是社区的uboot,都没有能支持ums功能,也就是说,要想用uboot来让全志的芯片支持ums功能,还需要大量工作。看来引入uboot是不靠谱的,需要用tinyusb自己写个U盘的payload? 这工作量就大多了,还有一种思路,加载linux内核,由linux内核来实现UMS功能。

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#34 2022-01-12 20:39:55

aozima
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Re: XFEL已支持spi nand flash烧写

嗯,我这现在就是linux启动还有些问题,所以才搞fel了。

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#35 2022-01-14 17:14:40

岁月快快快
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Re: XFEL已支持spi nand flash烧写

@xboot
大佬,用sudo xfel spinand write 0 xboot.bin命令和sudo xfel spinand splwrite 2048 1048576 xboot.bin烧程序进nand flash,
烧成功了,但是都没有启动起来,都是直接进了fel下载模式,用sunxi-fel -p spiflash-write 0 xboot.bin命令也是一样的;用xfel spinand命令也检测到了nand flash的型号和容量,读bin数据出来对比也是完全一样,是还有哪里没操作对吗?
用的nand是华邦的W25N01GV,soc是f1c100s;

最近编辑记录 岁月快快快 (2022-01-14 20:06:16)

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#36 2022-01-14 17:17:29

岁月快快快
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Re: XFEL已支持spi nand flash烧写

编译bin文件出来的log提示:The bootloader head has been fixed, spl size is 16384 bytes, 我把split-size改成16384也还是不行:
sudo xfel spinand splwrite 16384 1048576 xboot.bin

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#37 2022-01-14 20:27:45

岁月快快快
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Re: XFEL已支持spi nand flash烧写

f1c100s目录里面没有sys-spinand.c,感觉可能跟这个有关,加上去再试一下
_20220114202506.png

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#38 2022-01-15 11:37:11

岁月快快快
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Re: XFEL已支持spi nand flash烧写

修改了sys-copyself.c

/*
 * sys-copyself.c
 *
 * Copyright(c) 2007-2022 Jianjun Jiang <8192542@qq.com>
 * Official site: http://xboot.org
 * Mobile phone: +86-18665388956
 * QQ: 8192542
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#include <xboot.h>

extern unsigned char __image_start[];
extern unsigned char __image_end[];
extern unsigned char __heap_start[];
extern void return_to_fel(void);
extern void sys_mmu_init(void);
extern void sys_uart_putc(char c);
extern void sys_decompress(char * src, int slen, char * dst, int dlen);
extern int sys_hash(char * buf, int len, char * sha256);
extern int sys_verify(char * public, char * sha256, char * signature);
extern void sys_spinor_init(void);
extern void sys_spinor_exit(void);
extern void sys_spinor_read(int addr, void * buf, int count);
extern void sys_spinand_init(void);
extern void sys_spinand_exit(void);
extern void sys_spinand_read(int addr, void * buf, int count);

struct zdesc_t {			/* Total 256 bytes */
	uint8_t magic[4];		/* ZBL! */
	uint8_t signature[64];	/* Ecdsa256 signature of sha256 */
	uint8_t sha256[32];		/* Sha256 hash */
	uint8_t majoy;			/* Majoy version */
	uint8_t minior;			/* Minior version */
	uint8_t patch;			/* Patch version */
	uint8_t csize[4];		/* Compress size of image */
	uint8_t dsize[4];		/* Decompress size of image */
	uint8_t pubkey[33];		/* Ecdsa256 public key */
	uint8_t message[112];	/* Message additionally */
};

enum {
	BOOT_DEVICE_FEL	= 0,
	BOOT_DEVICE_SPINOR,
	BOOT_DEVICE_SPINAND,
	BOOT_DEVICE_SDCARD,
};

static int get_boot_device(void)
{
	u32_t * t = (void *)0x00000058;

	if(t[0] == 0x3)
		return BOOT_DEVICE_SPINOR;
	else if(t[0] == 0x4)
		return BOOT_DEVICE_SPINAND;
	else if(t[0] == 0x0)
		return BOOT_DEVICE_SDCARD;
	else if(t[0] == 0x1)
		return BOOT_DEVICE_FEL;
	return BOOT_DEVICE_SPINOR;

}

void sys_copyself(void)
{
	int d = get_boot_device();

	if(d == BOOT_DEVICE_FEL)
	{
		sys_uart_putc('B');
		sys_uart_putc('o');
		sys_uart_putc('o');
		sys_uart_putc('t');
		sys_uart_putc(' ');
		sys_uart_putc('t');
		sys_uart_putc('o');
		sys_uart_putc(' ');
		sys_uart_putc('F');
		sys_uart_putc('E');
		sys_uart_putc('L');
		sys_uart_putc(' ');
		sys_uart_putc('m');
		sys_uart_putc('o');
		sys_uart_putc('d');
		sys_uart_putc('e');
		sys_uart_putc('\r');
		sys_uart_putc('\n');
		return_to_fel();
	}
	else if(d == BOOT_DEVICE_SPINOR)
	{
		struct zdesc_t * z = (struct zdesc_t *)__heap_start;
		void * mem = (void *)__image_start;
		void * tmp = (void *)z + sizeof(struct zdesc_t);
		uint32_t size = __image_end - __image_start;

		sys_mmu_init();
		sys_spinor_init();
		sys_spinor_read(24576, z, sizeof(struct zdesc_t));
		sys_spinor_exit();
		if((z->magic[0] == 'Z') && (z->magic[1] == 'B') && (z->magic[2] == 'L') && (z->magic[3] == '!'))
		{
			//if(sys_verify((char *)z->pubkey, (char *)z->sha256, (char *)z->signature))
			{
				uint32_t csize = (z->csize[0] << 24) | (z->csize[1] << 16) | (z->csize[2] << 8) | (z->csize[3] << 0);
				uint32_t dsize = (z->dsize[0] << 24) | (z->dsize[1] << 16) | (z->dsize[2] << 8) | (z->dsize[3] << 0);
				sys_spinor_init();
				sys_spinor_read(24576 + sizeof(struct zdesc_t), tmp, csize);
				sys_spinor_exit();
				//if(sys_hash((char *)(&z->majoy), (sizeof(struct zdesc_t) - 100) + csize, (char *)z->sha256))
				{
					sys_decompress(tmp, csize, mem, dsize);
				}
			}
		}
		else
		{
			sys_spinor_init();
			sys_spinor_read(0, mem, size);
			sys_spinor_exit();
		}
	}
	else if(d == BOOT_DEVICE_SPINAND)
	{
		struct zdesc_t * z = (struct zdesc_t *)__heap_start;
		void * mem = (void *)__image_start;
		void * tmp = (void *)z + sizeof(struct zdesc_t);
		uint32_t size = __image_end - __image_start;

		sys_spinand_init();
		sys_spinand_read(1048576 + 65536, z, sizeof(struct zdesc_t));
		sys_spinand_exit();
		if((z->magic[0] == 'Z') && (z->magic[1] == 'B') && (z->magic[2] == 'L') && (z->magic[3] == '!'))
		{
			//if(sys_verify((char *)z->pubkey, (char *)z->sha256, (char *)z->signature))
			{
				uint32_t csize = (z->csize[0] << 24) | (z->csize[1] << 16) | (z->csize[2] << 8) | (z->csize[3] << 0);
				uint32_t dsize = (z->dsize[0] << 24) | (z->dsize[1] << 16) | (z->dsize[2] << 8) | (z->dsize[3] << 0);
				sys_spinand_init();
				sys_spinand_read(1048576 + 65536 + sizeof(struct zdesc_t), tmp, csize);
				sys_spinand_exit();
				//if(sys_hash((char *)(&z->majoy), (sizeof(struct zdesc_t) - 100) + csize, (char *)z->sha256))
				{
					sys_decompress(tmp, csize, mem, dsize);
				}
			}
		}
		else
		{
			sys_spinand_init();
			sys_spinand_read(1048576, mem, size);
			sys_spinand_exit();
		}
	}
	else if(d == BOOT_DEVICE_SDCARD)
	{
	}
}

修改并加入sys-spinand.c

/*
 * sys-spinand.c
 *
 * Copyright(c) 2007-2022 Jianjun Jiang <8192542@qq.com>
 * Official site: http://xboot.org
 * Mobile phone: +86-18665388956
 * QQ: 8192542
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#include <xboot.h>

/*
 * Default spi nand page size: 2048(11), 4096(12)
 */
#define SPINAND_PAGE_BITS	(11)
#define SPINAND_PAGE_MASK	((1 << SPINAND_PAGE_BITS) - 1)
#define SPINAND_PAGE_SIZE	(1 << SPINAND_PAGE_BITS)

enum {
	SPI_GCR	= 0x04,
	SPI_TCR	= 0x08,
	SPI_IER	= 0x10,
	SPI_ISR	= 0x14,
	SPI_FCR	= 0x18,
	SPI_FSR	= 0x1c,
	SPI_WCR	= 0x20,
	SPI_CCR	= 0x24,
	SPI_MBC	= 0x30,
	SPI_MTC	= 0x34,
	SPI_BCC	= 0x38,
	SPI_TXD	= 0x200,
	SPI_RXD	= 0x300,
};

void sys_spinand_init(void)
{
	virtual_addr_t addr;
	u32_t val;

	/* Config GPIOC0, GPIOC1, GPIOC2 and GPIOC3 */
	addr = 0x01c20848 + 0x00;
	val = read32(addr);
	val &= ~(0xf << ((0 & 0x7) << 2));
	val |= ((0x2 & 0x7) << ((0 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((1 & 0x7) << 2));
	val |= ((0x2 & 0x7) << ((1 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((2 & 0x7) << 2));
	val |= ((0x2 & 0x7) << ((2 & 0x7) << 2));
	write32(addr, val);

	val = read32(addr);
	val &= ~(0xf << ((3 & 0x7) << 2));
	val |= ((0x2 & 0x7) << ((3 & 0x7) << 2));
	write32(addr, val);

	/* Deassert spi0 reset */
	addr = 0x01c202c0;
	val = read32(addr);
	val |= (1 << 20);
	write32(addr, val);


	/* Open the spi0 bus gate */
	addr = 0x01c20000 + 0x60;
	val = read32(addr);
	val |= (1 << 20);
	write32(addr, val);



	/* Set spi clock rate control register, divided by 4 */
	addr = 0x01c05000;
	write32(addr + SPI_CCR, 0x00001001);

	/* Enable spi0 and do a soft reset */
	addr = 0x01c05000;
	val = read32(addr + SPI_GCR);
	val |= (1 << 31) | (1 << 7) | (1 << 1) | (1 << 0);
	write32(addr + SPI_GCR, val);
	while(read32(addr + SPI_GCR) & (1 << 31));

	val = read32(addr + SPI_TCR);
	val &= ~(0x3 << 0);
	val |= (1 << 6) | (1 << 2);
	write32(addr + SPI_TCR, val);

	val = read32(addr + SPI_FCR);
	val |= (1 << 31) | (1 << 15);
	write32(addr + SPI_FCR, val);
}

void sys_spinand_exit(void)
{
	virtual_addr_t addr = 0x01c05000;
	u32_t val;

	/* Disable the spi0 controller */
	val = read32(addr + SPI_GCR);
	val &= ~((1 << 1) | (1 << 0));
	write32(addr + SPI_GCR, val);
}

static void sys_spi_select(void)
{
	virtual_addr_t addr = 0x01c05000;
	u32_t val;

	val = read32(addr + SPI_TCR);
	val &= ~((0x3 << 4) | (0x1 << 7));
	val |= ((0 & 0x3) << 4) | (0x0 << 7);
	write32(addr + SPI_TCR, val);
}

static void sys_spi_deselect(void)
{
	virtual_addr_t addr = 0x01c05000;
	u32_t val;

	val = read32(addr + SPI_TCR);
	val &= ~((0x3 << 4) | (0x1 << 7));
	val |= ((0 & 0x3) << 4) | (0x1 << 7);
	write32(addr + SPI_TCR, val);
}

static void sys_spi_write_txbuf(u8_t * buf, int len)
{
	virtual_addr_t addr = 0x01c05000;
	int i;

	write32(addr + SPI_MTC, len & 0xffffff);
	write32(addr + SPI_BCC, len & 0xffffff);
	if(buf)
	{
		for(i = 0; i < len; i++)
			write8(addr + SPI_TXD, *buf++);
	}
	else
	{
		for(i = 0; i < len; i++)
			write8(addr + SPI_TXD, 0xff);
	}
}

static int sys_spi_transfer(void * txbuf, void * rxbuf, int len)
{
	virtual_addr_t addr = 0x01c05000;
	int count = len;
	u8_t * tx = txbuf;
	u8_t * rx = rxbuf;
	u8_t val;
	int n, i;

	while(count > 0)
	{
		n = (count <= 64) ? count : 64;
		write32(addr + SPI_MBC, n);
		sys_spi_write_txbuf(tx, n);
		write32(addr + SPI_TCR, read32(addr + SPI_TCR) | (1 << 31));

		while((read32(addr + SPI_FSR) & 0xff) < n);
		for(i = 0; i < n; i++)
		{
			val = read8(addr + SPI_RXD);
			if(rx)
				*rx++ = val;
		}

		if(tx)
			tx += n;
		count -= n;
	}
	return len;
}

static int sys_spi_write_then_read(void * txbuf, int txlen, void * rxbuf, int rxlen)
{
	if(sys_spi_transfer(txbuf, NULL, txlen) != txlen)
		return -1;
	if(sys_spi_transfer(NULL, rxbuf, rxlen) != rxlen)
		return -1;
	return 0;
}

static void sys_spinand_wait(void)
{
	u8_t tx[2];
	u8_t rx[1];

	tx[0] = 0x0f;
	tx[1] = 0xc0;
	do {
		sys_spi_select();
		sys_spi_write_then_read(tx, 2, rx, 1);
		sys_spi_deselect();
	} while((rx[0] & 0x1) == 0x1);
}

void sys_spinand_read(int addr, void * buf, int count)
{
	u8_t tx[4];
	u32_t pa, ca;
	int n;

	while(count > 0)
	{
		pa = addr >> SPINAND_PAGE_BITS;
		ca = addr & SPINAND_PAGE_MASK;
		n = count > (SPINAND_PAGE_SIZE - ca) ? (SPINAND_PAGE_SIZE - ca) : count;
		tx[0] = 0x13;
		tx[1] = (u8_t)(pa >> 16);
		tx[2] = (u8_t)(pa >> 8);
		tx[3] = (u8_t)(pa >> 0);
		sys_spi_select();
		sys_spi_write_then_read(tx, 4, 0, 0);
		sys_spi_deselect();
		sys_spinand_wait();
		tx[0] = 0x03;
		tx[1] = (u8_t)(ca >> 8);
		tx[2] = (u8_t)(ca >> 0);
		tx[3] = 0x0;
		sys_spi_select();
		sys_spi_write_then_read(tx, 4, buf, n);
		sys_spi_deselect();
		sys_spinand_wait();
		addr += n;
		buf += n;
		count -= n;
	}
}

还是起不来,start.S也要改么,还是漏掉了哪个文件没修改
mad

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楼主 #39 2022-01-15 17:31:37

xboot
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已发帖子: 485
积分: 310

Re: XFEL已支持spi nand flash烧写

你指令参数错误了,参考f133的烧录指令

sudo xfel spinand splwrite 2048 1048576 xboot.bin

这个意思是spi nand 每个扇区仅使用2KB,如果多余的话,就留空,然后完整镜像放置在1MB位置,splwrite,会在1MB之前复制尽可能多的spl备份,包括0地址也会放一个,存在多份,每个扇区使用2KB还是1KB这个由芯片的brom决定

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楼主 #40 2022-01-15 17:35:39

xboot
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Re: XFEL已支持spi nand flash烧写

F1C100S的话,貌似每个page仅使用1kB,还有一个细节需要注意,就是你spinand的page大小,sys-spinand.c文件里面有个define

/*
 * Default spi nand page size: 2048(11), 4096(12)
 */
#define SPINAND_PAGE_BITS	(11)
#define SPINAND_PAGE_MASK	((1 << SPINAND_PAGE_BITS) - 1)
#define SPINAND_PAGE_SIZE	(1 << SPINAND_PAGE_BITS)

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楼主 #41 2022-01-15 17:39:32

xboot
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已发帖子: 485
积分: 310

Re: XFEL已支持spi nand flash烧写

还有一个需要注意的地方自拷贝完整镜像放在1MB偏移的地方,只要注意这些细节,spi nand 就可以引导了。

	else if(d == BOOT_DEVICE_SPINAND)
	{
		struct zdesc_t * z = (struct zdesc_t *)__heap_start;
		void * mem = (void *)__image_start;
		void * tmp = (void *)z + sizeof(struct zdesc_t);
		uint32_t size = __image_end - __image_start;

		sys_spinand_init();
		sys_spinand_read(1048576 + 65536, z, sizeof(struct zdesc_t));
		sys_spinand_exit();
		if((z->magic[0] == 'Z') && (z->magic[1] == 'B') && (z->magic[2] == 'L') && (z->magic[3] == '!'))
		{
			//if(sys_verify((char *)z->pubkey, (char *)z->sha256, (char *)z->signature))
			{
				uint32_t csize = (z->csize[0] << 24) | (z->csize[1] << 16) | (z->csize[2] << 8) | (z->csize[3] << 0);
				uint32_t dsize = (z->dsize[0] << 24) | (z->dsize[1] << 16) | (z->dsize[2] << 8) | (z->dsize[3] << 0);
				sys_spinand_init();
				sys_spinand_read(1048576 + 65536 + sizeof(struct zdesc_t), tmp, csize);
				sys_spinand_exit();
				//if(sys_hash((char *)(&z->majoy), (sizeof(struct zdesc_t) - 100) + csize, (char *)z->sha256))
				{
					sys_decompress(tmp, csize, mem, dsize);
				}
			}
		}
		else
		{
			sys_spinand_init();
			sys_spinand_read(1048576, mem, size);
			sys_spinand_exit();
		}
	}

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#42 2022-01-17 15:14:54

HongSang
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已发帖子: 41
积分: 15.5

Re: XFEL已支持spi nand flash烧写

您好请问我如何使用xfel在f1c200s上烧写nand镜像 这里有u-boot.bin zImage dtb和rootfs

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#43 2022-01-17 16:06:38

岁月快快快
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积分: 21

Re: XFEL已支持spi nand flash烧写

2048 改成1024,就不进fel下载模式了,但是遇到了个奇怪的问题:

sys-copyself.c:

void test(void)
{
    sys_uart_putc('t');
    sys_uart_putc('e');
    sys_uart_putc('s');
    sys_uart_putc('t');
    sys_uart_putc(' ');
}

...
else if(d == BOOT_DEVICE_SPINAND)
{
	struct zdesc_t * z = (struct zdesc_t *)__heap_start;
	void * mem = (void *)__image_start;
	void * tmp = (void *)z + sizeof(struct zdesc_t);
	uint32_t size = __image_end - __image_start;

        //mprintf("enter BOOT_DEVICE_SPINAND !");
        sys_uart_putc('1');
        sys_uart_putc('6');
        sys_uart_putc('6');
        sys_uart_putc(' ');
        #if 0
	sys_spinand_init();
	sys_spinand_read(1048576 + 65536, z, sizeof(struct zdesc_t));
	sys_spinand_exit();
	if((z->magic[0] == 'Z') && (z->magic[1] == 'B') && (z->magic[2] == 'L') && (z->magic[3] == '!'))
	{
		//if(sys_verify((char *)z->pubkey, (char *)z->sha256, (char *)z->signature))
		{
			uint32_t csize = (z->csize[0] << 24) | (z->csize[1] << 16) | (z->csize[2] << 8) | (z->csize[3] << 0);
			uint32_t dsize = (z->dsize[0] << 24) | (z->dsize[1] << 16) | (z->dsize[2] << 8) | (z->dsize[3] << 0);
			sys_spinand_init();
			sys_spinand_read(1048576 + 65536 + sizeof(struct zdesc_t), tmp, csize);
			sys_spinand_exit();
			//if(sys_hash((char *)(&z->majoy), (sizeof(struct zdesc_t) - 100) + csize, (char *)z->sha256))
			{
				sys_decompress(tmp, csize, mem, dsize);
			}
		}
	}
	else
        #endif
	{
	    //mprintf("enter line180 !");
	    test();
            nandTest();
            sys_uart_putc('1');
            sys_uart_putc('9');
            sys_uart_putc('4');
            sys_uart_putc(' ');
            nandTest();
	    sys_spinand_init();
	    spinand_read(1048576, mem, size);
	    spinand_exit();
	}
}
else if(d == BOOT_DEVICE_SDCARD)
{
}
...

sys-spinand.c:

void nandTest(void)
{

}

sys-copyself.c自拷贝函数中如果调用了sys-spinand.c中的函数就会导致程序像挂掉一样;
测试代码中test()函数之后调用sys-spinand.c中的空函数nandTest(),后面的打印信息“194”就打不出来了,如果不调用nandTest(),就可以正常的打印出
“194”;把测试代码去掉,在sys_spinand_init()函数最开始的地方加上的打印信息,也没有打印出来,所以我推断调了sys-spinand.c中的函数之后程序就挂掉了,没有拷贝成功;
打印信息:
_16424046945692.png

把spi部分的代码全部搬到sys-copyself.c中,就可以正常启动了
lol

不过启动速度有点慢,用了将近5秒才起来,有什么优化办法吗,还是说nand启动就是这么慢的

最近编辑记录 岁月快快快 (2022-01-17 17:05:14)

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#44 2022-01-17 16:30:24

HongSang
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注册时间: 2021-08-12
已发帖子: 41
积分: 15.5

Re: XFEL已支持spi nand flash烧写

@岁月快快快
您好 烧写完能启动吗 可以分享下这两个文件吗

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#45 2022-01-17 16:55:43

岁月快快快
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积分: 21

Re: XFEL已支持spi nand flash烧写

HongSang 说:

@岁月快快快
您好 烧写完能启动吗 可以分享下这两个文件吗

sys-copyself.zip

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#46 2022-01-17 17:23:24

HongSang
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注册时间: 2021-08-12
已发帖子: 41
积分: 15.5

Re: XFEL已支持spi nand flash烧写

岁月快快快 说:
HongSang 说:

@岁月快快快
您好 烧写完能启动吗 可以分享下这两个文件吗

sys-copyself.zip

thank you very much

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楼主 #47 2022-01-17 18:11:50

xboot
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积分: 310

Re: XFEL已支持spi nand flash烧写

贴一段之前的总结:

不是对齐问题,这种sys-开头的文件,是需要用特别的编程手段的,因为这些程序的链接地址都是在DDR中,而实际运行地址是在SRAM中,需要实现成地址无关的程序,而系统刚启动,什么环境都不具备,C执行环境,更是不完整的,所以只能用特别编程手段。

一般有一下注意点:
1,不要使用已初始化数据段
2,不要使用未初始化数据段
3,不要使用switch case语句,可以用if elseif 代替
4,不要使用全局变量,仅使用局部变量
5,局部变量的初始化,用代码实现,会编译成立即数赋值
6,只能使用栈空间,其他什么都不可以使用
7,不要调用任何外部库,比如工具链里的C库等。

只要按这种要求,编程,编译出来的代码,都是地址无关的,SPL代码是很特殊的,谨记运行地址不是链接地址,就明白为何需要这样处理了。
当然,这种限制,也导致编程要求较高,如果不想挑战自己,就链接两次,做两个程序吧,BL1->BL2,这种,你看某些芯片的引导链,那么长,就是因为这种原因。

独立的一个程序,支持引导,自举,换到DDR空间,要求是很高的。这种编程技巧,算挑战性编程。

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楼主 #48 2022-01-17 18:17:20

xboot
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Re: XFEL已支持spi nand flash烧写

你的代码需要拷贝到sys-copyself.c里,大概率是链接脚本没修改正确。添加一下就可以解决你的问题了。

	.text :
	{
		PROVIDE(__image_start = .);
		PROVIDE(__text_start = .);
		PROVIDE(__spl_start = .);
		.obj/arch/arm32/mach-f1c100s/start.o (.text*)
		.obj/arch/arm32/lib/memcpy.o (.text*)
		.obj/arch/arm32/lib/memset.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-jtag.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-uart.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-clock.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-dram.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-mmu.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-decompress.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-hash.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-verify.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-spinor.o (.text*)
		.obj/arch/arm32/mach-f1c100s/sys-copyself.o (.text*)
		PROVIDE(__spl_end = .);
		*(.text*)
		*(.init.text)
		*(.exit.text)
		*(.glue*)
		*(.note.gnu.build-id)
		PROVIDE(__text_end = .);
	} > ram

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#49 2022-01-17 21:04:32

岁月快快快
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Re: XFEL已支持spi nand flash烧写

get 多谢大佬
lol

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