WhyCan Forum(哇酷开发者社区)

--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi	2019-08-29 14:30:28.000000000 +0800
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi	2020-01-21 19:26:46.466638364 +0800
@@ -4,6 +4,10 @@
  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -31,6 +35,12 @@
 			device_type = "cpu";
 		};
 	};
+	
+	de: display-engine {
+		compatible = "allwinner,suniv-f1c100s-display-engine";
+		allwinner,pipelines = <&fe0>;
+		status = "disabled";
+	};
 
 	soc {
 		compatible = "simple-bus";
@@ -62,6 +72,68 @@
 			};
 		};
 
+		spi0: spi@1c05000 {
+			compatible = "allwinner,suniv-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,suniv-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		tcon0: lcd-controller@1c0c000 {
+			compatible = "allwinner,suniv-f1c100s-tcon";
+			reg = <0x01c0c000 0x1000>;
+			interrupts = <29>;
+			clocks = <&ccu CLK_BUS_LCD>,
+				 <&ccu CLK_TCON>;
+			clock-names = "ahb",
+				      "tcon-ch0";
+			clock-output-names = "tcon-pixel-clock";
+			resets = <&ccu RST_BUS_LCD>;
+			reset-names = "lcd";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon0_in_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_out_tcon0>;
+					};
+				};
+
+				tcon0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+				};
+			};
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
@@ -71,6 +143,19 @@
 			#reset-cells = <1>;
 		};
 
+		i2c0: i2c@1C27000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01C27000 0x400>;
+			interrupts = <7>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		intc: interrupt-controller@1c20400 {
 			compatible = "allwinner,suniv-f1c100s-ic";
 			reg = <0x01c20400 0x400>;
@@ -82,17 +167,41 @@
 			compatible = "allwinner,suniv-f1c100s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <38>, <39>, <40>;
-			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			i2c0_pins: i2c0 {
+				pins = "PE11", "PE12";
+				function = "i2c0";
+            };
+
 			uart0_pe_pins: uart0-pe-pins {
 				pins = "PE0", "PE1";
 				function = "uart0";
 			};
+			
+			lcd_rgb666_pins: lcd-rgb666-pins {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+				       "PD5", "PD6", "PD7", "PD8", "PD9",
+				       "PD10", "PD11", "PD12", "PD13", "PD14",
+				       "PD15", "PD16", "PD17", "PD18", "PD19",
+				       "PD20", "PD21";
+				function = "lcd";
+			};
+			
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "mmc0";
+			};
+
+			spi0_pins_a: spi0-pins-pc {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
 		};
 
 		timer@1c20c00 {
@@ -102,20 +211,49 @@
 			clocks = <&osc24M>;
 		};
 
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,suniv-f1c100s-mmc",
+				     "allwinner,sun7i-a20-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>,
+				 <&ccu CLK_MMC0>,
+				 <&ccu CLK_MMC0_OUTPUT>,
+				 <&ccu CLK_MMC0_SAMPLE>;
+			clock-names = "ahb",
+					      "mmc",
+					      "output",
+				    	  "sample";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <23>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		wdt: watchdog@1c20ca0 {
 			compatible = "allwinner,suniv-f1c100s-wdt",
 				     "allwinner,sun4i-a10-wdt";
 			reg = <0x01c20ca0 0x20>;
 		};
 
+		lradc: lradc@1C23400 {
+			compatible = "allwinner,sun4i-a10-lradc-keys";
+			reg = <0x01C23400 0x400>;
+			interrupts = <22>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
 			interrupts = <1>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 38>;
-			resets = <&ccu 24>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
@@ -125,8 +263,8 @@
 			interrupts = <2>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 39>;
-			resets = <&ccu 25>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};
 
@@ -136,9 +274,107 @@
 			interrupts = <3>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 40>;
-			resets = <&ccu 26>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			status = "disabled";
+		};
+
+		usb_otg: usb@1c13000 {
+			compatible = "allwinner,suniv-musb";
+			reg = <0x01c13000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <26>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			allwinner,sram = <&otg_sram 1>;
+			status = "disabled";
+		};
+
+		usbphy: phy@1c13400 {
+			compatible = "allwinner,suniv-usb-phy";
+			reg = <0x01c13400 0x10>;
+			reg-names = "phy_ctrl";
+			clocks = <&ccu CLK_USB_PHY0>;
+			clock-names = "usb0_phy";
+			resets = <&ccu RST_USB_PHY0>;
+			reset-names = "usb0_reset";
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		fe0: display-frontend@1e00000 {
+			compatible = "allwinner,suniv-f1c100s-display-frontend";
+			reg = <0x01e00000 0x20000>;
+			interrupts = <30>;
+			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
+				 <&ccu CLK_DRAM_DE_FE>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&ccu RST_BUS_DE_FE>;
 			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				fe0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					fe0_out_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_in_fe0>;
+					};
+				};
+			};
+		};
+
+		be0: display-backend@1e60000 {
+			compatible = "allwinner,suniv-f1c100s-display-backend";
+			reg = <0x01e60000 0x10000>;
+			reg-names = "be";
+			interrupts = <31>;
+			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+				 <&ccu CLK_DRAM_DE_BE>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&ccu RST_BUS_DE_BE>;
+			reset-names = "be";
+			assigned-clocks = <&ccu CLK_DE_BE>;
+			assigned-clock-rates = <300000000>;
+		    rgb-channel-swap = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				be0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					be0_in_fe0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&fe0_out_be0>;
+					};
+				};
+
+				be0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					be0_out_tcon0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon0_in_be0>;
+					};
+				};
+			};
 		};
 	};
 };
+
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts	2019-08-29 14:30:28.000000000 +0800
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts	2020-01-21 19:26:46.470638361 +0800
@@ -1,10 +1,14 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
 /*
  * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
  */
 
 /dts-v1/;
+
 #include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "sunxi-common-regulators.dtsi"
 
 / {
 	model = "Lichee Pi Nano";
@@ -12,11 +16,142 @@
 
 	aliases {
 		serial0 = &uart0;
+		spi0 = &spi0;
 	};
 
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	panel: panel {
+		compatible = "ampire,am-480272h3tmqw-t01h";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_vcc3v3>;
+
+ 		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+ 			panel_input: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&tcon0_out_lcd>;
+			};
+		};
+	};
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+	status = "okay";
+};
+
+&pio {
+	vcc-pc-supply = <&reg_vcc3v3>;
+	vcc-pd-supply = <&reg_vcc3v3>;
+	vcc-pe-supply = <&reg_vcc3v3>;
+	vcc-pf-supply = <&reg_vcc3v3>;
+};
+
+&be0 {
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&tcon0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&lcd_rgb666_pins>;
+	status = "okay";
+};
+
+&tcon0_out {
+	tcon0_out_lcd: endpoint@0 {
+		reg = <0>;
+		remote-endpoint = <&panel_input>;
+	};
+};
+
+&i2c0 {
+    pinctrl-0 = <&i2c0_pins>;
+    pinctrl-names = "default";
+    status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	broken-cd;
+	status = "okay";
+};
+
+&pio {
+    ts_reset_pin: ts_reset_pin@0 {
+        pins = "PE9";
+        function = "gpio_out";
+    };
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins_a>;
+	status = "okay";
+
+	flash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x000000 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "dtb";
+				reg = <0x100000 0x10000>;
+				read-only;
+			};
+
+			partition@110000 {
+				label = "kernel";
+				reg = <0x110000 0x400000>;
+				read-only;
+			};
+
+			partition@520000 {
+				label = "rootfs";
+				reg = <0x510000 0xAF0000>;
+			};
+		};
+	};
 };
 
 &uart0 {
--- a/drivers/mtd/spi-nor/spi-nor.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/mtd/spi-nor/spi-nor.c	2020-01-21 19:26:46.470638361 +0800
@@ -2118,7 +2118,7 @@
 	},
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
-	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
+	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, 0) },
 	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c	2020-01-21 19:26:46.470638361 +0800
@@ -1419,6 +1419,15 @@
 	return 0;
 }
 
+static const struct sun4i_tcon_quirks suniv_f1c100s_quirks = {
+	/*
+	 * The F1C100s SoC has a second channel in TCON, but the clock input of
+	 * it is not documented.
+	 */
+	.has_channel_0		= true,
+	/* .has_channel_1	= true, */
+};
+
 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
 	.has_channel_0		= true,
 	.has_channel_1		= true,
@@ -1487,6 +1496,7 @@
 
 /* sun4i_drv uses this list to check if a device node is a TCON */
 const struct of_device_id sun4i_tcon_of_table[] = {
+	{ .compatible = "allwinner,suniv-f1c100s-tcon", .data = &suniv_f1c100s_quirks },
 	{ .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
 	{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
 	{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c	2020-01-21 19:26:46.470638361 +0800
@@ -164,7 +164,8 @@
 
 static bool sun4i_drv_node_is_frontend(struct device_node *node)
 {
-	return of_device_is_compatible(node, "allwinner,sun4i-a10-display-frontend") ||
+	return of_device_is_compatible(node, "allwinner,suniv-f1c100s-display-frontend") ||
+		of_device_is_compatible(node, "allwinner,sun4i-a10-display-frontend") ||
 		of_device_is_compatible(node, "allwinner,sun5i-a13-display-frontend") ||
 		of_device_is_compatible(node, "allwinner,sun6i-a31-display-frontend") ||
 		of_device_is_compatible(node, "allwinner,sun7i-a20-display-frontend") ||
@@ -404,6 +405,7 @@
 }
 
 static const struct of_device_id sun4i_drv_of_table[] = {
+	{ .compatible = "allwinner,suniv-f1c100s-display-engine" },
 	{ .compatible = "allwinner,sun4i-a10-display-engine" },
 	{ .compatible = "allwinner,sun5i-a10s-display-engine" },
 	{ .compatible = "allwinner,sun5i-a13-display-engine" },
--- a/drivers/gpu/drm/sun4i/sunxi_engine.h	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/gpu/drm/sun4i/sunxi_engine.h	2020-01-21 19:26:46.470638361 +0800
@@ -124,6 +124,7 @@
 	struct regmap			*regs;
 
 	int id;
+	int rgb_swap;
 
 	/* Engine list management */
 	struct list_head		list;
--- a/drivers/gpu/drm/sun4i/sun4i_backend.h	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.h	2020-01-21 19:30:43.086543111 +0800
@@ -92,6 +92,7 @@
 #define SUN4I_BACKEND_LAY_FBFMT_RGB888				(11 << 8)
 #define SUN4I_BACKEND_LAY_FBFMT_ARGB4444			(12 << 8)
 #define SUN4I_BACKEND_LAY_FBFMT_RGBA4444			(13 << 8)
+#define SUN4I_BACKEND_LAY_RGB_SWAP                  (1 << 2)
 
 #define SUN4I_BACKEND_DLCDPCTL_REG		0x8b0
 #define SUN4I_BACKEND_DLCDPFRMBUF_ADDRCTL_REG	0x8b4
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c	2020-01-21 19:26:46.542638322 +0800
@@ -293,9 +293,16 @@
 		return ret;
 	}
 
-	regmap_update_bits(backend->engine.regs,
-			   SUN4I_BACKEND_ATTCTL_REG1(layer),
-			   SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
+	if (backend->engine.rgb_swap) {
+	    regmap_update_bits(backend->engine.regs,
+			       SUN4I_BACKEND_ATTCTL_REG1(layer),
+			       SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT | SUN4I_BACKEND_LAY_RGB_SWAP, 
+			       val | SUN4I_BACKEND_LAY_RGB_SWAP);
+	} else {
+	    regmap_update_bits(backend->engine.regs,
+			       SUN4I_BACKEND_ATTCTL_REG1(layer),
+			       SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
+	}
 
 	return 0;
 }
@@ -316,10 +323,17 @@
 			   SUN4I_BACKEND_ATTCTL_REG0(layer),
 			   SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 			   SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
-
-	regmap_update_bits(backend->engine.regs,
-			   SUN4I_BACKEND_ATTCTL_REG1(layer),
-			   SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
+			   
+	if (backend->engine.rgb_swap) {
+	    regmap_update_bits(backend->engine.regs,
+			       SUN4I_BACKEND_ATTCTL_REG1(layer),
+			       SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT | SUN4I_BACKEND_LAY_RGB_SWAP, 
+			       val | SUN4I_BACKEND_LAY_RGB_SWAP);
+	} else {
+	    regmap_update_bits(backend->engine.regs,
+			       SUN4I_BACKEND_ATTCTL_REG1(layer),
+			       SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
+	}
 
 	return 0;
 }
@@ -818,6 +832,12 @@
 	backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 	if (backend->engine.id < 0)
 		return backend->engine.id;
+	
+	backend->engine.rgb_swap = 0;
+    if (of_find_property(dev->of_node, "rgb-channel-swap", NULL)) {
+        of_property_read_u32(dev->of_node, "rgb-channel-swap", &backend->engine.rgb_swap);
+        dev_warn(dev, "backend rgb channel swap(%d)\n", backend->engine.rgb_swap);
+    }
 
 	backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 	if (IS_ERR(backend->frontend))
@@ -972,6 +992,9 @@
 	return 0;
 }
 
+static const struct sun4i_backend_quirks suniv_backend_quirks = {
+};
+
 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 	.needs_output_muxing = true,
 };
@@ -996,6 +1019,10 @@
 
 static const struct of_device_id sun4i_backend_of_table[] = {
 	{
+		.compatible = "allwinner,suniv-f1c100s-display-backend",
+		.data = &suniv_backend_quirks,
+	},
+	{
 		.compatible = "allwinner,sun4i-a10-display-backend",
 		.data = &sun4i_backend_quirks,
 	},
--- a/drivers/phy/allwinner/phy-sun4i-usb.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c	2020-01-21 19:26:46.542638322 +0800
@@ -98,6 +98,7 @@
 #define POLL_TIME			msecs_to_jiffies(250)
 
 enum sun4i_usb_phy_type {
+	suniv_phy,
 	sun4i_a10_phy,
 	sun6i_a31_phy,
 	sun8i_a33_phy,
@@ -859,6 +860,14 @@
 	return 0;
 }
 
+static const struct sun4i_usb_phy_cfg suniv_cfg = {
+	.num_phys = 1,
+	.type = suniv_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.num_phys = 3,
 	.type = sun4i_a10_phy,
@@ -973,6 +982,7 @@
 };
 
 static const struct of_device_id sun4i_usb_phy_of_match[] = {
+	{ .compatible = "allwinner,suniv-usb-phy", .data = &suniv_cfg },
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
--- a/drivers/usb/musb/sunxi.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/usb/musb/sunxi.c	2020-01-21 19:26:46.542638322 +0800
@@ -714,14 +714,16 @@
 	INIT_WORK(&glue->work, sunxi_musb_work);
 	glue->host_nb.notifier_call = sunxi_musb_host_notifier;
 
-	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+	if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+		of_device_is_compatible(np, "allwinner,suniv-musb"))
 		set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
 
 	if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 
 	if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
-	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+		of_device_is_compatible(np, "allwinner,suniv-musb")) {
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 		set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
 	}
@@ -812,6 +814,7 @@
 }
 
 static const struct of_device_id sunxi_musb_match[] = {
+	{ .compatible = "allwinner,suniv-musb", },
 	{ .compatible = "allwinner,sun4i-a10-musb", },
 	{ .compatible = "allwinner,sun6i-a31-musb", },
 	{ .compatible = "allwinner,sun8i-a33-musb", },
--- a/drivers/video/fbdev/core/fbcon.c	2019-08-29 14:30:28.000000000 +0800
+++ b/drivers/video/fbdev/core/fbcon.c	2020-01-21 19:26:46.542638322 +0800
@@ -368,6 +368,7 @@
 
 static void fb_flashcursor(struct work_struct *work)
 {
+#if 0
 	struct fb_info *info = container_of(work, struct fb_info, queue);
 	struct fbcon_ops *ops = info->fbcon_par;
 	struct vc_data *vc = NULL;
@@ -398,6 +399,7 @@
 	ops->cursor(vc, info, mode, softback_lines, get_color(vc, info, c, 1),
 		    get_color(vc, info, c, 0));
 	console_unlock();
+#endif
 }
 
 static void cursor_timer_handler(struct timer_list *t)