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	{
		//	The Hotplug Flag Register is 0x070005DC.
		//	The Soft Entry Address Register is 0x070005E0.

		//	la	a0, 0x02500000
		//	la	a1, 0x23
		//	sb	a1, 0 (a0)
		//	xxx:	j	xxx
		// Test: write byte to 0x02500000 = UART0 data tegister
		static const uint32_t code [] = {
				0x02500537, // 37 05 50 02
				0x0230059B,	// 9B 05 30 02 │
				0x00B50023, // 23 00 B5 00
				0x0000006F, // 6F 00 00 00,
		};

		* (volatile uint32_t *) 0x070005DC = 0*0xFA50392Fu;	// Hotplug Flag Register
		* (volatile uint32_t *) 0x070005E0 = (uintptr_t) code;	// Soft Entry Address Register

		dcache_clean_all();

		printhex(0x06000000, (void *) 0x06000000, 0x10000);
		//CCU->RISC_GATING_REG
		CCU->RISC_CFG_BGR_REG |= (1u << 16) | (1u << 0);
		(void) CCU->RISC_CFG_BGR_REG;
		PRINTF("CCU->RISC_CFG_BGR_REG=%08" PRIX32 "\n", CCU->RISC_CFG_BGR_REG);

		RISC_CFG->RISC_STA_ADD0_REG = (uintptr_t) code;
		RISC_CFG->RISC_STA_ADD1_REG = 0;//(uint32_t) (uintptr_t) code >> 32;
		//memset(RISC_CFG, ~ 0u, sizeof * RISC_CFG);
		PRINTF("CCU->RISC_GATING_REG=%08" PRIX32 ", CCU->RISC_CFG_BGR_REG=%08" PRIX32 "\n", CCU->RISC_GATING_REG, CCU->RISC_CFG_BGR_REG);
		PRINTF("RISC_CFG->RISC_STA_ADD0_REG=%08" PRIX32 ", RISC_CFG->RISC_STA_ADD1_REG=%08" PRIX32 "\n", RISC_CFG->RISC_STA_ADD0_REG, RISC_CFG->RISC_STA_ADD1_REG);
		//printhex32(RISC_CFG_BASE, RISC_CFG, sizeof * RISC_CFG);
		local_delay_ms(3000);
		//PRINTF("CCU->RISC_RST_REG=%08" PRIX32 "\n", CCU->RISC_RST_REG);
		CCU->RISC_RST_REG = 0x16AA0001u;
		(void) CCU->RISC_RST_REG;
		//PRINTF("CCU->RISC_RST_REG=%08" PRIX32 "\n", CCU->RISC_RST_REG);
		//ASSERT(CCU->RISC_RST_REG & 0x01u);
		for (;;)
			;
	}

xtensa-hifi4-elf-gcc.exe (crosstool-NG 1.25.0) 10.3.0
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