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#1 2021-02-15 22:13:38

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

购买链接: https://item.taobao.com/item.htm?id=631665290641


IPL g5da0ceb
D-1e
HW Reset
miupll_233MHz
MIU0 zq=0x003c
miu_bw_set
utmi_1_init done
utmi_2_init done
utmi_3_init done
usbpll init done......
cpupll init done
SPI 54M
clk_init done
P1 USB_rterm trim=0x0000
P1 USB_HS_TX_CURRENT trim=0x0001
P2 USB_rterm trim=0x0000
P2 USB_HS_TX_CURRENT trim=0x0001
P3 USB_rterm trim=0x0000
P3 USB_HS_TX_CURRENT trim=0x0001
PM_vol_bgap trim=0x0005
GCR_SAR_DATA trim=0x018f
ETH 10T output swing trim=0x0000
ETH 100T output swing trim=0x0010
ETH RX input impedance trim=0x0000
ETH TX output impedance trim=0x0001
MIPI_HS_RTERM trim=0x0001
MIPI_LP_RTERM trim=0x0000
128MB
BIST0_0001-OK
Enable MMU and CACHE
Load IPL_CUST from SPINAND
QUAD MODE ENABLE
Checksum OK

IPL_CUST g5da0ceb
runUBOOT()
runUBOOT()
[SPINAND]
SPI 54M
Load UBOOT from SPINAND
 -Verify UBOOT CRC32 passed!
 -Decompress UBOOT XZ
  decomp_size=0x000a12a4
Disable MMU and D-cache before jump to UBOOT▒

U-Boot 2015.01 (Dec 14 2020 - 17:22:37)

Version: I2g#######
       Watchdog enabled
I2C:   ready
DRAM:
WARNING: Caches not enabled
SPINAND: _MDrv_SPINAND_GET_INFO: Found SPINAND INFO
(0xCD) (0xEB) (0x11)
SPINAND: board_nand_init: CIS contains part info
256 MiB
MMC:   MStar SD/MMC: 0
In:    serial
Out:   serial
Err:   serial
Net:   MAC Address 00:30:1B:BA:02:DB
Auto-Negotiation...
Link Status Speed:10 Full-duplex:0
Status Error!
sstar_emac
bootcheck start
fore uup u8KeyPad_KeyVal [0xffff]
BootMode 0
Saving Environment to NAND...
Erasing NAND...
Erasing at 0x440000 -- 100% complete.
Writing to NAND... OK

NAND read: device 0 offset 0x4c0000, size 0x60000
Time:39991 us, speed:9832 KB/s
 393216 bytes read: OK
gpio debug MHal_GPIO_Pad_Set: pin=8
gpio[8] is 1

NAND read: device 0 offset 0x520000, size 0x500000
Time:521749 us, speed:10048 KB/s
 5242880 bytes read: OK
gpio debug MHal_GPIO_Pad_Set: pin=8
gpio[8] is 1
##  Booting kernel from Legacy Image at 22000000 ...
   Image Name:   MVX4##I2M#g#######KL_LX409##[BR:
   Image Type:   ARM Linux Kernel Image (lzma compressed)
   Data Size:    2437200 Bytes = 2.3 MiB
   Load Address: 20008000
   Entry Point:  20008000
   Verifying Checksum ... OK
-usb_stop(USB_PORT0)
-usb_stop(USB_PORT1)
-usb_stop(USB_PORT2)
   Uncompressing Kernel Image ...
[XZ] !!!reserved 0x21000000 length=0x 1000000 for xz!!
   XZ: uncompressed size=0x4da000, ret=7
OK
atags:0x20000000

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.9.84 (ronnie@wt_rd_server) (gcc version 8.2.1 20180802 (GNU Toolchain for the A-profile Architecture 8.2-2018-08 (arm-rel-8.23)) ) #61 SMP PREEMPT Mon Dec 14 17:22:44 CST 2020
CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
CPU: div instructions available: patching division code
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
early_atags_to_fdt() success
OF: fdt:Machine model: INFINITY2M SSC011A-S01A-S
LXmem is 0x7f00000 PHYS_OFFSET is 0x20000000
Add mem start 0x20000000 size 0x7f00000!!!!

LX_MEM  = 0x20000000, 0x7f00000
LX_MEM2 = 0x0, 0x0
LX_MEM3 = 0x0, 0x0
EMAC_LEN= 0x0
DRAM_LEN= 0x0
deal_with_reserved_mmap memblock_reserve success mmap_reserved_config[0].reserved_start=
0x27c00000

deal_with_reserve_mma_heap memblock_reserve success mma_config[0].reserved_start=
0x26c00000

cma: Reserved 2 MiB at 0x26a00000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @c68bc000 s25112 r8192 d24040 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 28162
Kernel command line: console=ttyS0,115200 ubi.mtd=UBI,2048 root=ubi:rootfs rw rootfstype=ubifs init=/linuxrc rootwait=1 LX_MEM=0x7f00000 mma_heap=mma_heap_name0,miu=0,sz=0x1000000 mma_memblock_remove=1 highres=off mmap_reserved=fb,miu=0,sz=0x300000,max_start_off=0x7C00000,max_end_off=0x7F00000 mtdparts=nand0:384k@1280k(IPL0),384k(IPL1),384k(IPL_CUST0),384k(IPL_CUST1),768k(UBOOT0),768k(UBOOT1),384k(ENV0),0x20000(KEY_CUST),0x60000(LOGO),0x500000(KERNEL),0x500000(RECOVERY),-(UBI)
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 102132K/113664K available (2894K kernel code, 249K rwdata, 1488K rodata, 172K init, 171K bss, 9484K reserved, 2048K cma-reserved)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xc8000000 - 0xff800000   ( 888 MB)
    lowmem  : 0xc0000000 - 0xc7f00000   ( 127 MB)
    modules : 0xbf800000 - 0xc0000000   (   8 MB)
      .text : 0xc0008000 - 0xc02dba90   (2895 kB)
      .init : 0xc0477000 - 0xc04a2000   ( 172 kB)
      .data : 0xc04a2000 - 0xc04e05e8   ( 250 kB)
       .bss : 0xc04e2000 - 0xc050cc98   ( 172 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
ms_init_main_intc: np->name=ms_main_intc, parent=gic
ms_init_pm_intc: np->name=ms_pm_intc, parent=ms_main_intc
ss_init_gpi_intc: np->name=ms_gpi_intc, parent=ms_main_intc
Find CLK_cpupll_clk, hook ms_cpuclk_ops
arm_arch_timer: Architected cp15 timer(s) running at 6.00MHz (virt).
clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 440795202238 ns
sched_clock: 56 bits at 6MHz, resolution 166ns, wraps every 4398046511055ns
Switching to timer-based delay loop, resolution 166ns
Console: colour dummy device 80x30
console [ttyS0] enabled
Calibrating delay loop (skipped), value calculated using timer frequency.. 12.00 BogoMIPS (lpj=60000)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: update cpu_capacity 1024
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x20008240 - 0x20008270
CPU1: update cpu_capacity 1024
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (24.00 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 5
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 16 (order: -2, 1024 bytes)
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations


Version : MVX4##I2M#g#######KL_LX409##[BR:g]#XVM

GPIO: probe end[ss_gpi_intc_domain_alloc] hw:42 -> v:43
[MS_PM_INTC] hw:20 -> v:51
[Padmux]reset Pad_87(reg 0x101e09; mask0x7) to DMIC_MODE_2(org: I2C0_MODE_1)
hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 8 bytes.
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Linux video capture interface: v2.00
clocksource: Switched to clocksource arch_sys_counter
NET: Registered protocol family 2
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 1024 (order: 2, 20480 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
UDP hash table entries: 128 (order: 0, 6144 bytes)
UDP-Lite hash table entries: 128 (order: 0, 6144 bytes)
NET: Registered protocol family 1
hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
workingset: timestamp_bits=30 max_order=15 bucket_order=0
squashfs: version 4.0 (2009/01/31) Phillip Lougher
jffs2: version 2.2. © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered (default)
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-bz0
[Padmux]reset Pad_47(reg 0x101e03; mask0x70) to GPIO(org: UART0_MODE_1)
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-usb-en
sd_pwr init ok
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-rs485-ctrl
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-y1
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-y2
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-zero
cust-io-ctrl soc:ido_io_ctrl: Device tree not define of gpio-wifi-reset
cust_io_ctrl complete!
libphy: Fixed MDIO Bus: probed
CAN device driver interface
PPP generic driver version 2.4.2
PPP BSD Compression module registered
PPP Deflate Compression module registered
PPP MPPE Compression module registered
NET: Registered protocol family 24
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver option
usbserial: USB Serial support registered for GSM modem (1-port)
mousedev: PS/2 mouse device common for all mice
[ss_gpi_intc_domain_alloc] hw:58 -> v:58
i2c /dev entries driver
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
1f221000.uart0: ttyS0 at MMIO 0x0 (irq = 30, base_baud = 10800000) is a unknown
1f221200.uart1: ttyS1 at MMIO 0x0 (irq = 31, base_baud = 10800000) is a unknown
1f220400.uart2: ttyS2 at MMIO 0x0 (irq = 32, base_baud = 10800000) is a unknown
1f221400.uart2: ttyS3 at MMIO 0x0 (irq = 33, base_baud = 10800000) is a unknown
[Core Voltage] check_voltage_valid: Not support 0mV, use 900mV
>> [sdmmc] ms_sdmmc_probe
[Padmux]reset Pad_51(reg 0x101e08; mask0x300) to GPIO(org: SDIO_MODE_1)
>> [sdmmc_0] Probe Platform Devices
MSYS: DMEM request: [emac0_buff]:0x00000812
MSYS: DMEM request: [emac0_buff]:0x00000812 success, CPU phy:@0x26A43000, virt:@0xC6A43000
libphy: mdio: probed
mdio_bus mdio-bus@emac0: /soc/emac0/mdio-bus@emac0/ethernet-phy@0 has invalid PHY address
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 0
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 1
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 2
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 3
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 4
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 5
Goodix-TS 1-005d: ID 911, version: 1060
Goodix-TS 1-005d: Direct firmware load for goodix_911_cfg.bin failed with error -2
input: Goodix Capacitive TouchScreen as /devices/soc0/soc/1f223200.i2c1/i2c-1/1-005d/input/input0
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 6
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 7
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 8
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 9
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 10
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 11
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 12
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 13
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 14
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 15
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 16
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 17
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 18
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 19
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 20
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 21
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 22
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 23
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 24
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 25
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 26
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 27
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 28
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 29
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 30
mdio_bus mdio-bus@emac0: scan phy ethernet-phy at address 31
[emac_phy_connect][3204] connected mac emac0 to PHY at mdio-bus@emac0:00 [uid=11112222, driver=SStar 10/100 Ethernet Phy]
MSYS: DMEM request: [emac1_buff]:0x00060812
MSYS: DMEM request: [emac1_buff]:0x00060812 success, CPU phy:@0x26A50000, virt:@0xC6A50000
libphy: mdio: probed
mdio_bus mdio-bus@emac1: /soc/emac1/mdio-bus@emac1/ethernet-phy@1 has invalid PHY address
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 0
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 1
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 2
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 3
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 4
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 5
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 6
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 7
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 8
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 9
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 10
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 11
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 12
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 13
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 14
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 15
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 16
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 17
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 18
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 19
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 20
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 21
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 22
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 23
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 24
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 25
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 26
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 27
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 28
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 29
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 30
mdio_bus mdio-bus@emac1: scan phy ethernet-phy at address 31
[emac_phy_connect][3204] connected mac emac1 to PHY at mdio-bus@emac1:00 [uid=00000000, driver=Generic PHY]
ms_rtcpwc 1f006800.rtcpwc: rtc core: registered 1f006800.rtcpwc as rtc0
[ms_cpufreq_init] Current clk=1005326304
mstar_spinand_probe: mstar_spinand enableClock
MSYS: DMEM request: [BDMA]:0x00000840
MSYS: DMEM request: [BDMA]:0x00000840 success, CPU phy:@0x26A44000, virt:@0xC6A44000
MDrv_SPINAND_Init: Detected ID: MID =cd, DID =eb
_dumpNandInformation:warning, Bytes / Page :  2048
_dumpNandInformation:warning, Pages / Block:  64
_dumpNandInformation:warning, Sector/ Page :  512
_dumpNandInformation:warning, Spare / Page :  64
_dumpNandInformation:warning, Current config r:4 w:4 drv:1
mstar_spinand_probe: Magic memcmp pass
mstar_spinand_probe: Get partition (Block 0 : page 1)
mstar_spinand_probe: CIS contains part info
mstar_spinand_probe: Before nand_scan()...
12 cmdlinepart partitions found on MTD device nand0
mstar_spinand_probe: Mtd parts parse
Creating 12 MTD partitions on "nand0":
0x000000140000-0x0000001a0000 : "IPL0"
0x0000001a0000-0x000000200000 : "IPL1"
0x000000200000-0x000000260000 : "IPL_CUST0"
0x000000260000-0x0000002c0000 : "IPL_CUST1"
0x0000002c0000-0x000000380000 : "UBOOT0"
0x000000380000-0x000000440000 : "UBOOT1"
0x000000440000-0x0000004a0000 : "ENV0"
0x0000004a0000-0x0000004c0000 : "KEY_CUST"
0x0000004c0000-0x000000520000 : "LOGO"
0x000000520000-0x000000a20000 : "KERNEL"
0x000000a20000-0x000000f20000 : "RECOVERY"
0x000000f20000-0x000010000000 : "UBI"
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20161123 t)
can: netlink gateway (rev 20130117) max_hops=1
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
ubi0: attaching mtd11
ubi0: scanning is finished
ubi0: attached mtd11 (name "UBI", size 240 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
ubi0: good PEBs: 1927, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 4, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
ubi0: available PEBs: 23, total reserved PEBs: 1904, PEBs reserved for bad PEB handling: 40
ubi0: background thread "ubi_bgt0d" started, PID 684
Please set rtc timer (hwclock -w)
ms_rtcpwc 1f006800.rtcpwc: setting system clock to 1970-01-01 00:00:01 UTC (1)
OF: fdt:not creating '/sys/firmware/fdt': CRC check failed
UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 687
UBIFS (ubi0:0): recovery needed
UBIFS (ubi0:0): recovery completed
UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "rootfs"
UBIFS (ubi0:0): LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
UBIFS (ubi0:0): FS size: 205320192 bytes (195 MiB, 1617 LEBs), journal size 9023488 bytes (8 MiB, 72 LEBs)
UBIFS (ubi0:0): reserved for root: 0 bytes (0 KiB)
UBIFS (ubi0:0): media format: w4/r0 (latest is w4/r0), UUID BB60053E-265F-489A-BBA2-E23FCCB53856, small LPT model
VFS: Mounted root (ubifs filesystem) on device 0:13.
devtmpfs: mounted
This architecture does not have kernel memory protection.
mount: can't find devpts in /etc/fstab
mount: mounting none on /sys failed: Device or resource busy
mount: mounting none on /sys/kernel/debug/ failed: Device or resource busy
UBIFS (ubi0:1): background thread "ubifs_bgt0_1" started, PID 708
UBIFS (ubi0:1): recovery needed
UBIFS (ubi0:1): recovery completed
UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name "miservice"
UBIFS (ubi0:1): LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
UBIFS (ubi0:1): FS size: 9269248 bytes (8 MiB, 73 LEBs), journal size 1650688 bytes (1 MiB, 13 LEBs)
UBIFS (ubi0:1): reserved for root: 0 bytes (0 KiB)
UBIFS (ubi0:1): media format: w4/r0 (latest is w4/r0), UUID 31366479-B49E-485F-80FE-DFCB66B51986, small LPT model
UBIFS (ubi0:2): background thread "ubifs_bgt0_2" started, PID 711
UBIFS (ubi0:2): recovery needed
UBIFS (ubi0:2): recovery completed
UBIFS (ubi0:2): UBIFS: mounted UBI device 0, volume 2, name "customer"
UBIFS (ubi0:2): LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
UBIFS (ubi0:2): FS size: 4063232 bytes (3 MiB, 32 LEBs), journal size 1142785 bytes (1 MiB, 8 LEBs)
UBIFS (ubi0:2): reserved for root: 0 bytes (0 KiB)
UBIFS (ubi0:2): media format: w4/r0 (latest is w4/r0), UUID 0BABC81B-8AEC-4DA9-BE30-EC9F477955A0, small LPT model
UBIFS (ubi0:3): background thread "ubifs_bgt0_3" started, PID 714
UBIFS (ubi0:3): recovery needed
UBIFS (ubi0:3): recovery completed
UBIFS (ubi0:3): UBIFS: mounted UBI device 0, volume 3, name "appconfigs"
UBIFS (ubi0:3): LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
UBIFS (ubi0:3): FS size: 4063232 bytes (3 MiB, 32 LEBs), journal size 1142785 bytes (1 MiB, 8 LEBs)
UBIFS (ubi0:3): reserved for root: 0 bytes (0 KiB)
UBIFS (ubi0:3): media format: w4/r0 (latest is w4/r0), UUID 962D6689-38D7-4433-B862-005B5E537CBD, small LPT model
[1]+  Done                       busybox telnetd
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
ntfs: driver 2.1.32 [Flags: R/O MODULE].
insmod: can't read '/config/modules/4.9.84/usb-common.ko': No such file or directory
insmod: can't read '/config/modules/4.9.84/usbcore.ko': Noehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
 such file or diehci monitor start running
Mstar_ehc_init version:20180309
rectory
Sstar-ehci-2 H.W init
Titania3_series_start_ehc start
[USB] config miu select [70] [e8] [ef] [ef]
[USB] enable miu lower bound address subtraction
[USB] init squelch level 0x2
[USB] no platform_data, device tree coming
[USB][EHC] dma coherent_mask 0xffffffffffffffff mask 0xffffffffffffffff
BC disable
[USB] soc:Sstar-ehci-2 irq --> 38
Sstar-ehci-2 soc:Sstar-ehci-2: EHCI Host Controller
Sstar-ehci-2 soc:Sstar-ehci-2: new USB bus registered, assigned bus number 1
Sstar-ehci-2 soc:Sstar-ehci-2: irq 38, io mem 0xfd285000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
usb usb1: Manufacturer: Linux 4.9.84 ehci_hcd
usb usb1: SerialNumber: mstar
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
Sstar-ehci-1 H.W init
Titania3_series_start_ehc start
[USB] config miu select [70] [e8] [ef] [ef]
[USB] enable miu lower bound address subtraction
[USB] init squelch level 0x2
[USB] no platform_data, device tree coming
[USB][EHC] dma coherent_mask 0xffffffffffffffff mask 0xffffffffffffffff
BC disable
[USB] soc:Sstar-ehci-1 irq --> 37
Sstar-ehci-1 soc:Sstar-ehci-1: EHCI Host Controller
Sstar-ehci-1 soc:Sstar-ehci-1: new USB bus registered, assigned bus number 2
Sstar-ehci-1 soc:Sstar-ehci-1: irq 37, io mem 0xfd284800
usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: EHCI Host Controller
usb usb2: Manufacturer: Linux 4.9.84 ehci_hcd
usb usb2: SerialNumber: mstar
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
insmod: can't read '/config/modules/4.9.84/usb-storage.ko': No such file or directory
insmod: can't read '/confMSYS: DMEM request: [AESDMA_ENG]:0x00001000
ig/modules/4.9.8MSYS: DMEM request: [AESDMA_ENG]:0x00001000 success, CPU phy:@0x26A4B000, virt:@0xC6A4B000
4/usbhid.ko': NoMSYS: DMEM request: [AESDMA_ENG1]:0x00001000
 such file or diMSYS: DMEM request: [AESDMA_ENG1]:0x00001000 success, CPU phy:@0x26A4C000, virt:@0xC6A4C000
rectory
mhal: loading out-of-tree module taints kernel.
mhal: module license 'PROPRIETARY' taints kernel.
Disabling lock debugging due to kernel taint
==20180309==> hub_port_init 1 #0
Plug in USB Port2
mhal driver init
jpe driver probed
DivpProcInit 515
module [sys] init
MI_SYSCFG_SetupMmapLoader default_config_path:/config/config_tool, argv1:/config/load_mmap,argv2:/config/mmap.ini
==20180309==> hub_port_init 1 #0
Plug in USB Port1
Function = init_glob_miu_kranges, Line = 604, Insert KProtect for LX @ MIU: 0
Function = init_glob_miu_kranges, Line = 613, [INIT] for LX0 kprotect: from 0x20000000 to 0x27F00000, using block 0
config...... strPath:/config/config_tool, argv0:/config/load_config
function:parese_Cmdline,pCmd_Section:0x7f00000
mm
a_
he
ap
_n
am
e0
    miu=0,sz=1000000  reserved_start=26c00000
r_front->miuBlockIndex:0,r_front->start_cpu_bus_pa:0x20000000,r_front->start_cpu_bus_pa+r_front->length:0x26c00000
r_back->miuBlockIndex:1,r_back->start_cpu_bus_pa:0x27c00000,r_back->start_cpu_bus_pa+r_back->length:0x27f00000
mi_sys_mma_allocator_create success, heap_base_addr=26c00000 length=1000000
Kernel CONFIG_HZ = 100
Sigmastar Module version: project_commit.866b490 sdk_commit.341badc build_time.20200714212826
usb 1-1: new high-speed USB device number 2 using Sstar-ehci-2
module [gfx] init
module [divp] init
module [vdec] init
module [ao] init
module [disp] init
usb 2-1: new high-speed USB device number 2 using Sstar-ehci-1
drv_ccif_cpu_init :c8580000
 request_irq failed
module [ai] init
module [venc] init Jul 14 2020 21:29:05
module [panel] init
[GOP]HalGopUpdateGwinParam 720: GOP_id=011 not support
[GOP]HalGopSetArgb1555Alpha 1208: GOPId=0x11 not support
[GOP]HalGopSetArgb1555Alpha 1208: GOPId=0x11 not support
usb 1-1: New USB device found, idVendor=1782, idProduct=4e00
usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-1: Product: UNISOC-8910
usb 1-1: Manufacturer: UNISOC
option 1-1:1.2: GSM modem (1-port) converter detected
usb 1-1: GSM modem (1-port) converter now attached to ttyUSB0
option 1-1:1.3: GSM modem (1-port) converter detected
usb 1-1: GSM modem (1-port) converter now attached to ttyUSB1
option 1-1:1.4: GSM modem (1-port) converter detected
/ # usb 1-1: GSM modem (1-port) converter now attached to ttyUSB2
usb 2-1: New USB device found, idVendor=1b20, idProduct=8888
usb 2-1: New USB device strings: Mfr=16, Product=32, SerialNumber=0
usb 2-1: Product: SigmaStarWIFI
usb 2-1: Manufacturer: SigmaStar inc
client [848] connected, module:sys
DISP width: 1024client [848] connected, module:disp
,height: 600
[MI_SYSCFG_GetPanelInfo 50] eTiming = 4, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 2, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 8, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 9, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 10, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 6, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 7, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 11, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 13, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 12, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 14, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 5, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 3, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 38, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 50, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 40, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 43, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 41, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 44, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 42, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 46, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 50, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 45, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 50, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 22, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 23, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 30, hdmiTx = 1  Not Fund!!!
[MI_SYSCFG_GetPanelInfo 50] eTiming = 32, hdmiTx = 1  Not Fund!!!
client [848] connected, module:panel
[MI_PANEL_Init][332]LCD environment is Invalid
Freeing fb memory: 3072K
sstar_FB_SetBlending 416 u8GOP=1,u8win=0 aType=1 u8constAlpha=255
The framebuffer device was opened successfulrandom: fast init done
ly.
1024x600, 32bpp
The framebuffer device was mapped to memory successfully.
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited
Menu inited

bootargs 传入mtd分区参数:

mtdparts=nand0:384k@1280k(IPL0),384k(IPL1),384k(IPL_CUST0),384k(IPL_CUST1),768k(UBOOT0),768k(UBOOT1),384k(ENV0),0x20000(KEY_CUST),0x60000(LOGO),0x500000(KERNEL),0x500000(RECOVERY),-(UBI)

查看分区:

# cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00060000 00020000 "IPL0"
mtd1: 00060000 00020000 "IPL1"
mtd2: 00060000 00020000 "IPL_CUST0"
mtd3: 00060000 00020000 "IPL_CUST1"
mtd4: 000c0000 00020000 "UBOOT0"
mtd5: 000c0000 00020000 "UBOOT1"
mtd6: 00060000 00020000 "ENV0"
mtd7: 00020000 00020000 "KEY_CUST"
mtd8: 00060000 00020000 "LOGO"
mtd9: 00500000 00020000 "KERNEL"
mtd10: 00500000 00020000 "RECOVERY"
mtd11: 0f0e0000 00020000 "UBI"



感谢 深圳市启明云端科技 友情赠送的7寸电容 4G & WIFI SSD202 开发板
http://whycan.com/t_5891.html

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#2 2021-02-15 22:17:02

SigmaStarStudy
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注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

文件系统没有gt911固件:

/lib/firmware/goodix_911_cfg.bin

但是触摸屏正常实用

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#3 2021-02-15 22:41:33

SigmaStarStudy
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注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

ssd20x_burn_ipl.png
ssd_burn_ipl_cust.png
ssd_burn_uboot.png

http://doc.industio.com/docs/ssd20x-system/page_3-1

Creating 12 MTD partitions on "nand0":
0x000000140000-0x0000001a0000 : "IPL0"
0x0000001a0000-0x000000200000 : "IPL1"
0x000000200000-0x000000260000 : "IPL_CUST0"
0x000000260000-0x0000002c0000 : "IPL_CUST1"
0x0000002c0000-0x000000380000 : "UBOOT0"
0x000000380000-0x000000440000 : "UBOOT1"
0x000000440000-0x0000004a0000 : "ENV0"
0x0000004a0000-0x0000004c0000 : "KEY_CUST"
0x0000004c0000-0x000000520000 : "LOGO"
0x000000520000-0x000000a20000 : "KERNEL"
0x000000a20000-0x000000f20000 : "RECOVERY"
0x000000f20000-0x000010000000 : "UBI"

IPL, IPL_CUST, UBOOT的烧录地址和kenerl log刚好能对应起来.

现在问题来了, 为什么 IPL, IPL_CUST, UBOOT 这三个都有两份一模一样的?

是备份? 考虑 NAND 不稳定?

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#4 2021-02-15 22:48:38

SigmaStarStudy
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注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

/ # md5sum /dev/mtd?
08ace1d6f8478a7ac01d2220f92a9e13  /dev/mtd0
08ace1d6f8478a7ac01d2220f92a9e13  /dev/mtd1
9f0f2a94ce8c49a0508332cc293d2ac1  /dev/mtd2
9f0f2a94ce8c49a0508332cc293d2ac1  /dev/mtd3
be23156a61bf9e56f8f076a7ad04b79f  /dev/mtd4
be23156a61bf9e56f8f076a7ad04b79f  /dev/mtd5
9e614c5a18d012b32033c1d809371110  /dev/mtd6
41d2e2c0c0edfccf76fa1c3e38bc1cf2  /dev/mtd7
e63040f23d8a2f4a6ef1d448f519d1d5  /dev/mtd8
96af93c2d08e63f63ab92643d536156a  /dev/mtd9
/ # md5sum /dev/mtd??
96af93c2d08e63f63ab92643d536156a  /dev/mtd10
d8dc4e69bffcd9dae5d09ce5279b9214  /dev/mtd11

直接用md5sum获取分区的校验码, 果然备份分区与原分区数据一模一样.

好奇, 怎么判断原分区数据出错呢?

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#5 2021-02-15 22:52:11

SigmaStarStudy
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累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

/ # mount
ubi:rootfs on / type ubifs (rw,relatime)
devtmpfs on /dev type devtmpfs (rw,relatime,size=51064k,nr_inodes=12766,mode=755)
proc on /proc type proc (rw,relatime)
sysfs on /sys type sysfs (rw,relatime)
tmpfs on /tmp type tmpfs (rw,relatime,size=52088k,nr_inodes=13022)
var on /var type tmpfs (rw,relatime,size=52088k,nr_inodes=13022)
vendor on /vendor type tmpfs (rw,relatime,size=52088k,nr_inodes=13022)
none on /sys/kernel/debug type debugfs (rw,relatime)
mdev on /dev type tmpfs (rw,relatime,size=52088k,nr_inodes=13022)
ubi0:miservice on /config type ubifs (rw,relatime)
ubi0:customer on /customer type ubifs (rw,relatime)
ubi0:appconfigs on /appconfigs type ubifs (rw,relatime)
devpts on /dev/pts type devpts (rw,relatime,mode=600,ptmxmode=000)
/ #
/ #
/ #
/ # df
Filesystem           1K-blocks      Used Available Use% Mounted on
ubi:rootfs              184756     33404    151352  18% /
devtmpfs                 52088         0     52088   0% /dev
tmpfs                    52088         0     52088   0% /tmp
var                      52088         0     52088   0% /var
vendor                   52088         0     52088   0% /vendor
mdev                     52088         0     52088   0% /dev
ubi0:miservice            7680      5652      2028  74% /config
ubi0:customer             2980       164      2816   6% /customer
ubi0:appconfigs           2980        24      2956   1% /appconfigs
/ #

对 ubifs 文件系统还是不熟, 慢慢学吧.

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#6 2021-02-15 22:56:41

SigmaStarStudy
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累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

http://doc.industio.com/docs/ssd201-sbc2d07/ssd201-sbc2d07-1ck3kjs5io40s

# cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00060000 00020000 "IPL0"
mtd1: 00060000 00020000 "IPL1"

大概知道 为什么第一个分区不是 地址0 开始了, 因为前面还有一个 cis.bin

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#7 2021-02-15 23:22:24

SigmaStarStudy
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Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

SSD20x 大部分驱动程序在这个目录: drivers/sstar/

$ tree drivers/sstar/
drivers/sstar/
├── adaptor
│   ├── linux-rtos-adaptor.c
│   └── Makefile
├── bdma
│   ├── built-in.o
│   ├── infinity2
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── infinity2m
│   │   ├── built-in.o
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── hal_bdma.o
│   │   ├── kernel_bdma.h
│   │   ├── Makefile
│   │   ├── modules.builtin
│   │   └── modules.order
│   ├── infinity3
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── infinity5
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── infinity6
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── infinity6b0
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── infinity6e
│   │   ├── hal_bdma.c
│   │   ├── hal_bdma.h
│   │   ├── kernel_bdma.h
│   │   └── Makefile
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── built-in.o
├── cambricon
│   ├── Kconfig
│   └── Makefile
├── cam_clkgen
│   ├── built-in.o
│   ├── cam_clkgen.c
│   ├── cam_clkgen.o
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── camdriver
│   ├── Kconfig
│   └── Makefile
├── cam_drv_buffer
│   ├── built-in.o
│   ├── cam_drv_buffer.mak
│   ├── HISTORY
│   ├── Makefile
│   ├── Makefile_Linux_user
│   ├── modules.builtin
│   ├── modules.order
│   ├── pub
│   │   └── cam_drv_buffer.h
│   └── src
│       ├── cam_drv_buffer.c
│       ├── cam_drv_buffer.o
│       ├── cam_drv_export.c
│       └── cam_drv_export.o
├── cam_drv_poll
│   ├── built-in.o
│   ├── cam_drv_poll.mak
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── pub
│   │   └── cam_drv_poll.h
│   ├── sample_driver
│   │   ├── inc
│   │   │   └── mdrv_pollsample_module.h
│   │   ├── Makefile
│   │   ├── pub
│   │   │   └── mdrv_pollsample_io.h
│   │   ├── src
│   │   │   └── drv
│   │   │       ├── common
│   │   │       │   └── drv_pollsample_dev.c
│   │   │       ├── linux
│   │   │       │   ├── drv_pollsample_export.c
│   │   │       │   └── drv_pollsample_module.c
│   │   │       └── rtk
│   │   │           └── drv_pollsample_module.c
│   │   └── test
│   │       └── camdrvpolltest
│   │           ├── cam_drv_poll_test.c
│   │           └── Makefile
│   └── src
│       ├── cam_drv_poll.c
│       └── cam_drv_poll.o
├── cam_fs_wrapper
│   ├── built-in.o
│   ├── cam_fs_wrapper.mak
│   ├── HISTORY
│   ├── Makefile
│   ├── Makefile_lib
│   ├── modules.builtin
│   ├── modules.order
│   ├── pub
│   │   └── cam_fs_wrapper.h
│   ├── src
│   │   ├── cam_fs_export.c
│   │   ├── cam_fs_export.o
│   │   ├── cam_fs_wrapper.c
│   │   └── cam_fs_wrapper.o
│   └── test
│       ├── cam_fs_linux_kernel_test.c
│       ├── cam_fs_linux_user_test.c
│       └── Makefile
├── cam_os_wrapper
│   ├── built-in.o
│   ├── cam_os_wrapper.mak
│   ├── HISTORY
│   ├── Makefile
│   ├── Makefile_lib
│   ├── modules.builtin
│   ├── modules.order
│   ├── pub
│   │   ├── cam_os_util_bitmap.h
│   │   ├── cam_os_util_bug.h
│   │   ├── cam_os_util.h
│   │   ├── cam_os_util_hash.h
│   │   ├── cam_os_util_ioctl.h
│   │   ├── cam_os_util_list.h
│   │   ├── cam_os_util_string.h
│   │   └── cam_os_wrapper.h
│   ├── src
│   │   ├── cam_os_export.c
│   │   ├── cam_os_export.o
│   │   ├── cam_os_informal_idr.c
│   │   ├── cam_os_informal_idr.o
│   │   ├── cam_os_wrapper.c
│   │   └── cam_os_wrapper.o
│   └── test
│       ├── cam_os_wrapper_linux_kernel_test.c
│       ├── cam_os_wrapper_test.c
│       ├── cam_os_wrapper_test.h
│       └── Makefile
├── cam_sysfs
│   ├── built-in.o
│   ├── cam_sysfs.c
│   ├── cam_sysfs.o
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── ceva_link
│   ├── boot_loader.c
│   ├── boot_loader.h
│   ├── ceva_linkdrv.c
│   ├── ceva_linkdrv-generic.h
│   ├── ceva_linkdrv.h
│   ├── ceva_linkdrv_proc.c
│   ├── ceva_linkdrv_proc.h
│   ├── ceva_linkdrv_shared_process_protected_db_def_copy.h
│   ├── ceva_linkdrv_xm6.c
│   ├── ceva_linkdrv_xm6.h
│   ├── drv_debug.h
│   ├── file_access.c
│   ├── file_access.h
│   ├── hal_ceva.c
│   ├── hal_ceva.h
│   ├── hal_ceva_reg.h
│   ├── hal_cpm.c
│   ├── hal_cpm.h
│   ├── hal_debug.h
│   ├── hal_intr_ctrl.c
│   ├── hal_intr_ctrl.h
│   ├── hal_intr_ctrl_reg.h
│   ├── hal_timer.c
│   ├── hal_timer.h
│   ├── jni
│   │   └── test.c
│   ├── Kconfig
│   ├── Makefile
│   ├── protected_mem_db.c
│   └── protected_mem_db.h
├── clk
│   ├── built-in.o
│   ├── cedric
│   │   ├── clk.c
│   │   └── Makefile
│   ├── infinity
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity2
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity2m
│   │   ├── built-in.o
│   │   ├── Makefile
│   │   ├── modules.builtin
│   │   ├── modules.order
│   │   ├── ms_complex_clk.c
│   │   └── ms_complex_clk.o
│   ├── infinity3
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity5
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity6
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity6b0
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── infinity6e
│   │   ├── Makefile
│   │   └── ms_complex_clk.c
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_composite_clk.c
│   ├── ms_composite_clk.o
│   └── ms_usclk.c
├── clocksource
│   ├── built-in.o
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_arm_gt_clocksource.c
│   └── ms_piu_timer.c
├── cpu
│   ├── built-in.o
│   ├── Makefile
│   ├── memory.c
│   ├── mem-ory.o
│   ├── memory.o
│   ├── modules.builtin
│   └── modules.order
├── cpufreq
│   ├── built-in.o
│   ├── infinity
│   │   └── cpufreq.c
│   ├── infinity2m
│   │   ├── cpufreq.c
│   │   └── cpufreq.o
│   ├── infinity3
│   │   └── cpufreq.c
│   ├── infinity5
│   │   └── cpufreq.c
│   ├── infinity6
│   │   └── cpufreq.c
│   ├── infinity6b0
│   │   └── cpufreq.c
│   ├── infinity6e
│   │   └── cpufreq.c
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── crypto
│   ├── built-in.o
│   ├── cryptodev
│   │   ├── authenc.c
│   │   ├── authenc.o
│   │   ├── AUTHORS
│   │   ├── built-in.o
│   │   ├── cipherapi.h
│   │   ├── COPYING
│   │   ├── cryptlib.c
│   │   ├── cryptlib.h
│   │   ├── cryptlib.o
│   │   ├── crypto
│   │   │   └── cryptodev.h
│   │   ├── cryptodev_int.h
│   │   ├── cryptodev.ko
│   │   ├── cryptodev.mod.c
│   │   ├── cryptodev.mod.o
│   │   ├── cryptodev.o
│   │   ├── examples
│   │   │   ├── aes.c
│   │   │   ├── aes-gcm.c
│   │   │   ├── aes-gcm.h
│   │   │   ├── aes.h
│   │   │   ├── aes-sha1.c
│   │   │   ├── aes-sha1.h
│   │   │   ├── readme
│   │   │   ├── sha.c
│   │   │   ├── sha-copy.c
│   │   │   ├── sha-copy.h
│   │   │   └── sha.h
│   │   ├── INSTALL
│   │   ├── ioctl.c
│   │   ├── ioctl.o
│   │   ├── main.c
│   │   ├── main.o
│   │   ├── Makefile
│   │   ├── modules.order
│   │   ├── NEWS
│   │   ├── README
│   │   ├── util.c
│   │   ├── util.h
│   │   ├── util.o
│   │   ├── version.h
│   │   ├── zc.c
│   │   ├── zc.h
│   │   └── zc.o
│   ├── hal
│   │   ├── infinity2m
│   │   │   └── halAESDMA.h
│   │   ├── infinity3
│   │   │   └── halAESDMA.h
│   │   ├── infinity5
│   │   │   └── halAESDMA.h
│   │   ├── infinity6
│   │   │   └── halAESDMA.h
│   │   ├── infinity6b0
│   │   │   └── halAESDMA.h
│   │   └── infinity6e
│   │       └── halAESDMA.h
│   ├── halAESDMA.c
│   ├── halAESDMA.o
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_aes.c
│   ├── mdrv_aes.h
│   ├── mdrv_aes.o
│   ├── mdrv_cipher.c
│   ├── mdrv_cipher.o
│   ├── mdrv_crypto.ko
│   ├── mdrv_crypto.mod.c
│   ├── mdrv_crypto.mod.o
│   ├── mdrv_crypto.o
│   ├── mdrv_rsa.c
│   ├── mdrv_rsa.h
│   ├── mdrv_rsa.o
│   ├── mdrv_sha.c
│   ├── mdrv_sha.o
│   └── modules.order
├── dualos
│   ├── drv_dualos.c
│   ├── interos_call.h
│   ├── lock.h
│   ├── Makefile
│   ├── rlink.h
│   ├── rsq.c
│   ├── rsq.h
│   ├── sw_sem.c
│   └── sw_sem.h
├── emac
│   ├── built-in.o
│   ├── hal
│   │   ├── infinity2
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   └── mhal_rng_reg.h
│   │   ├── infinity2m
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   ├── mhal_emac.o
│   │   │   └── mhal_rng_reg.h
│   │   ├── infinity3
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   └── mhal_rng_reg.h
│   │   ├── infinity5
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   └── mhal_rng_reg.h
│   │   ├── infinity6
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   └── mhal_rng_reg.h
│   │   ├── infinity6b0
│   │   │   ├── mhal_emac.c
│   │   │   ├── mhal_emac.h
│   │   │   └── mhal_rng_reg.h
│   │   └── infinity6e
│   │       ├── mhal_emac.c
│   │       ├── mhal_emac.h
│   │       └── mhal_rng_reg.h
│   ├── Kconfig
│   ├── kdrv_emac.o
│   ├── Makefile
│   ├── mdrv_emac.c
│   ├── mdrv_emac.h
│   ├── mdrv_emac.o
│   ├── modules.builtin
│   ├── modules.order
│   ├── Mstar_emac_problem_shooting_v0 .doc
│   └── policy.txt
├── emmc
│   ├── cedric
│   │   ├── eMMCDrv
│   │   │   ├── inc
│   │   │   │   ├── api
│   │   │   │   │   └── drv_eMMC.h
│   │   │   │   ├── common
│   │   │   │   │   ├── eMMC_err_codes.h
│   │   │   │   │   ├── eMMC.h
│   │   │   │   │   ├── eMMC_hal.h
│   │   │   │   │   └── eMMC_utl.h
│   │   │   │   └── config
│   │   │   │       ├── eMMC_cedric_linux.h
│   │   │   │       ├── eMMC_chicago_linux.h
│   │   │   │       ├── eMMC_config.h
│   │   │   │       ├── eMMC_eagle_linux.h
│   │   │   │       ├── eMMC_edison_linux.h
│   │   │   │       ├── eMMC_eiffel_linux.h
│   │   │   │       ├── eMMC_einstein_linux.h
│   │   │   │       └── eMMC_reg.h
│   │   │   └── src
│   │   │       ├── api
│   │   │       │   └── eMMC_prg.c
│   │   │       ├── common
│   │   │       │   ├── cmd_mstar_emmc_bootloader.txt
│   │   │       │   ├── eMMC_hal.c
│   │   │       │   ├── eMMC_ip_verify.c
│   │   │       │   └── eMMC_utl.c
│   │   │       └── config
│   │   │           └── eMMC_platform.c
│   │   ├── Makefile
│   │   ├── mstar_mci.c
│   │   └── mstar_mci.h
│   ├── chicago
│   │   ├── eMMCDrv
│   │   │   ├── inc
│   │   │   │   ├── api
│   │   │   │   │   └── drv_eMMC.h
│   │   │   │   ├── common
│   │   │   │   │   ├── eMMC_err_codes.h
│   │   │   │   │   ├── eMMC.h
│   │   │   │   │   ├── eMMC_hal.h
│   │   │   │   │   └── eMMC_utl.h
│   │   │   │   └── config
│   │   │   │       ├── eMMC_cedric_linux.h
│   │   │   │       ├── eMMC_chicago_linux.h
│   │   │   │       ├── eMMC_config.h
│   │   │   │       ├── eMMC_eagle_linux.h
│   │   │   │       ├── eMMC_edison_linux.h
│   │   │   │       ├── eMMC_eiffel_linux.h
│   │   │   │       ├── eMMC_einstein_linux.h
│   │   │   │       └── eMMC_reg.h
│   │   │   └── src
│   │   │       ├── api
│   │   │       │   └── eMMC_prg.c
│   │   │       ├── common
│   │   │       │   ├── cmd_mstar_emmc_bootloader.txt
│   │   │       │   ├── eMMC_hal.c
│   │   │       │   ├── eMMC_ip_verify.c
│   │   │       │   └── eMMC_utl.c
│   │   │       └── config
│   │   │           └── eMMC_platform.c
│   │   ├── Makefile
│   │   ├── mstar_mci.c
│   │   └── mstar_mci.h
│   ├── Kconfig
│   ├── Makefile
│   └── unify_driver
│       ├── inc
│       │   ├── api
│       │   │   └── drv_eMMC.h
│       │   ├── common
│       │   │   ├── eMMC_err_codes.h
│       │   │   ├── eMMC.h
│       │   │   ├── eMMC_hal.h
│       │   │   └── eMMC_utl.h
│       │   ├── config
│       │   │   ├── eMMC_config.h
│       │   │   ├── eMMC_reg.h
│       │   │   └── eMMC_reg_v5.h
│       │   ├── infinity2m
│       │   │   └── eMMC_linux.h
│       │   ├── infinity3
│       │   │   └── eMMC_linux.h
│       │   ├── infinity5
│       │   │   └── eMMC_linux.h
│       │   ├── infinity6
│       │   │   └── eMMC_linux.h
│       │   └── infinity6e
│       │       └── eMMC_linux.h
│       ├── Makefile
│       ├── mmc.lds
│       ├── mstar_mci.c
│       ├── mstar_mci.h
│       ├── mstar_mci_v5.c
│       └── src
│           ├── api
│           │   └── eMMC_prg.c
│           ├── common
│           │   ├── eMMC_hal.c
│           │   ├── eMMC_hal_speed.c
│           │   ├── eMMC_hal_v5.c
│           │   ├── eMMC_ip_verify.c
│           │   └── eMMC_utl.c
│           └── config
│               └── eMMC_platform.c
├── flash_isp
│   ├── built-in.o
│   ├── drvDeviceInfo.c
│   ├── drvDeviceInfo.h
│   ├── drvDeviceInfo.o
│   ├── drvSERFLASH.c
│   ├── drvSERFLASH.h
│   ├── drvSERFLASH.o
│   ├── include
│   │   └── MsTypes.h
│   ├── infinity2
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── infinity2m
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   ├── halSERFLASH.o
│   │   └── regSERFLASH.h
│   ├── infinity3
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── infinity5
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── infinity6
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── infinity6b0
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── infinity6e
│   │   ├── halSERFLASH.c
│   │   ├── halSERFLASH.h
│   │   └── regSERFLASH.h
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── mtd_serflash.c
│   ├── mtd_serflash.o
│   ├── mxp_flash.c
│   ├── mxp_flash.o
│   ├── part_mxp.c
│   ├── part_mxp.h
│   └── part_mxp.o
├── gmac
│   ├── drv_mdio_sw.c
│   ├── hal
│   │   ├── infinity2
│   │   │   ├── mhal_gmac.c.old
│   │   │   ├── mhal_gmac.h.old
│   │   │   ├── mhal_gmac_v3.c
│   │   │   ├── mhal_gmac_v3.h
│   │   │   └── mhal_rng_reg.h
│   │   └── kano
│   │       ├── mhal_gmac.c
│   │       ├── mhal_gmac.h
│   │       ├── mhal_gmac_v3.c
│   │       ├── mhal_gmac_v3.h
│   │       └── mhal_rng_reg.h
│   ├── Kconfig
│   ├── Kconfig.old
│   ├── Makefile
│   ├── mdrv_gmac.c.old
│   ├── mdrv_gmac.h.old
│   ├── mdrv_gmac_v2.c.old
│   ├── mdrv_gmac_v3.c
│   └── mdrv_gmac_v3.h
├── gpio
│   ├── built-in.o
│   ├── cedric
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   └── mhal_gpio_reg.h
│   ├── infinity
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   └── mhal_gpio_reg.h
│   ├── infinity2
│   │   ├── GPIO_TABLE.h
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_gpio_reg.h
│   │   └── mhal_pinmux.c
│   ├── infinity2m
│   │   ├── built-in.o
│   │   ├── chiptop_reg.h
│   │   ├── gpio_table.c
│   │   ├── gpio_table.h
│   │   ├── gpio_table.o
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_gpio.o
│   │   ├── mhal_pinmux.c
│   │   ├── mhal_pinmux.h
│   │   ├── mhal_pinmux.o
│   │   ├── modules.builtin
│   │   ├── modules.order
│   │   ├── padmux_tables.c
│   │   ├── padmux_tables.h
│   │   ├── padmux_tables.o
│   │   └── pmsleep_reg.h
│   ├── infinity3
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_gpio_reg.h
│   │   └── mhal_pinmux.c
│   ├── infinity5
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_gpio_reg.h
│   │   └── mhal_pinmux.c
│   ├── infinity6
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_pinmux.c
│   │   └── mhal_pinmux.h
│   ├── infinity6b0
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_pinmux.c
│   │   └── mhal_pinmux.h
│   ├── infinity6e
│   │   ├── Makefile
│   │   ├── mhal_gpio.c
│   │   ├── mhal_gpio.h
│   │   ├── mhal_pinmux.c
│   │   └── mhal_pinmux.h
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_gpio.c
│   ├── mdrv_gpio_io.c
│   ├── mdrv_gpio_io.o
│   ├── mdrv_gpio.o
│   ├── mdrv_sw_iic.c
│   ├── mdrv_sw_iic.h
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_gpioi2c.c
│   └── test
│       ├── gpio_irq_test.c
│       └── Makefile
├── gpio_key_sample
│   ├── gpio_key_driver
│   │   ├── gpio_key_driver.c
│   │   └── Makefile
│   ├── kernel_gpio_key_patch
│   │   └── drivers
│   │       └── input
│   │           └── keyboard
│   │               └── gpio_keys.c
│   ├── key_test.c
│   └── readme.txt
├── GUIDELINE.doc
├── i2c
│   ├── built-in.o
│   ├── cedric
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity2
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity2m
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   ├── mhal_iic.o
│   │   └── mhal_iic_reg.h
│   ├── infinity3
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity5
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity6
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity6b0
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── infinity6e
│   │   ├── Makefile
│   │   ├── mhal_iic.c
│   │   ├── mhal_iic.h
│   │   └── mhal_iic_reg.h
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_iic.c
│   ├── ms_iic.h
│   └── ms_iic.o
├── include
│   ├── cam_clkgen.h
│   ├── cam_dev_wrapper.h
│   ├── cam_drv_buffer.h
│   ├── cam_drv_poll.h
│   ├── cam_fs_wrapper.h
│   ├── cam_os_util_bitmap.h
│   ├── cam_os_util_bug.h
│   ├── cam_os_util.h
│   ├── cam_os_util_hash.h
│   ├── cam_os_util_ioctl.h
│   ├── cam_os_util_list.h
│   ├── cam_os_util_string.h
│   ├── cam_os_wrapper.h
│   ├── cam_sysfs.h
│   ├── cam_sysfs.h.bak
│   ├── ceva_linkdrv-generic.h
│   ├── drvcmdq_io.h
│   ├── drv_dualos.h
│   ├── drv_isrcb.h
│   ├── infinity2
│   │   ├── gpi-irqs.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── powerDown
│   │   │   ├── AVDD3P3_USB_P0
│   │   │   │   ├── 1_Infinity2_usb20_p0_pd.h
│   │   │   │   ├── 2_Infinity2_upll_p0_pd.h
│   │   │   │   ├── 3_Infinity2_gmacpll_pd.h
│   │   │   │   ├── 4_Infinity2_cevapll_pd.h
│   │   │   │   ├── 5_Infinity2_extaupll_pd.h
│   │   │   │   └── 6_Infinity2_hdmi2txpll_pd.h
│   │   │   ├── AVDD3P3_USB_P1
│   │   │   │   ├── 1_Infinity2_usb20_p0_pd.h
│   │   │   │   ├── 2_Infinity2_upll_p0_pd.h
│   │   │   │   ├── 3_Infinity2_mipspll_pd.h
│   │   │   │   ├── 4_Infinity2_isppll_pd.h
│   │   │   │   ├── 5_Infinity2_hicodecpll_pd.h
│   │   │   │   └── 6_Infinity2_evdpll_pd.h
│   │   │   ├── AVDD3P3_USB_P2
│   │   │   │   ├── 1_Infinity2_usb20_p0_pd.h
│   │   │   │   ├── 2_Infinity2_upll_p2_pd.h
│   │   │   │   └── 3_Infinity2_miu128pll_pd.h
│   │   │   ├── AVDD3P3_USB_P3
│   │   │   │   └── 1_Infinity2_usb20_p3_pd.h
│   │   │   ├── AVDD_MIPI_TX
│   │   │   │   ├── 1_Infinity2_mipi_combotx_pd.h
│   │   │   │   ├── 2_Infinity2_mpll_pd.h
│   │   │   │   └── 3_Infinity2_lpll_pd.h
│   │   │   ├── ETH_TX_100T_RANDOM.h
│   │   │   ├── ETH_TX_10T_ALL_ONE.h
│   │   │   ├── ETH_TX_10T_LTP.h
│   │   │   ├── ETH_TX_10T_TP_IDL.h
│   │   │   ├── Infinity2_mipi_rx_pd
│   │   │   │   ├── Infinity2_mipi_rx_p0_pd.h
│   │   │   │   ├── Infinity2_mipi_rx_p1_pd.h
│   │   │   │   ├── Infinity2_mipi_rx_p2_pd.h
│   │   │   │   └── Infinity2_mipi_rx_p3_pd.h
│   │   │   ├── U3CP_CP0_CP7_pattern_p0.h
│   │   │   ├── U3CP_CP0_CP7_pattern_p1.h
│   │   │   ├── U3PCIE_CP0_CP7_pattern_m_PHY_p0.h
│   │   │   ├── U3PCIE_CP0_CP7_pattern_m_PHY_p1.h
│   │   │   ├── USB20_verification_pattern_TSTPG_FS_v2.h
│   │   │   └── USB20_verification_pattern_TSTPG_v2.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── vcore_dvfs.h
│   ├── infinity2m
│   │   ├── cpu_freq.h
│   │   ├── gpi-irqs.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── voltage_ctrl_demander.h
│   ├── infinity3
│   │   ├── cpu_freq.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── padmux.h
│   │   ├── reg_clks.h
│   │   └── registers.h
│   ├── infinity5
│   │   ├── cpu_freq.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── voltage_ctrl_demander.h
│   ├── infinity6
│   │   ├── cpu_freq.h
│   │   ├── gpi-irqs.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── pmsleep-irqs.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── voltage_ctrl_demander.h
│   ├── infinity6b0
│   │   ├── cpu_freq.h
│   │   ├── gpi-irqs.h
│   │   ├── gpio.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── pmsleep-irqs.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── voltage_ctrl_demander.h
│   ├── infinity6e
│   │   ├── cpu_freq.h
│   │   ├── gpi-irqs.h
│   │   ├── gpio.h
│   │   ├── iopow.h
│   │   ├── irqs.h
│   │   ├── Kconfig
│   │   ├── mcm_id.h
│   │   ├── mdrv_miu.h
│   │   ├── mhal_miu.h
│   │   ├── padmux.h
│   │   ├── pmsleep-irqs.h
│   │   ├── reg_clks.h
│   │   ├── registers.h
│   │   ├── regMIU.h
│   │   └── voltage_ctrl_demander.h
│   ├── mdrv_API_version.h
│   ├── mdrv_cipher.h
│   ├── mdrv_device_id.h
│   ├── mdrv_fb_io.h
│   ├── mdrv_fb_st.h
│   ├── mdrv_gpio.h
│   ├── mdrv_gpio_io.h
│   ├── mdrv_hvsp_io.h
│   ├── mdrv_hvsp_io_i3.h
│   ├── mdrv_hvsp_io_i3_st.h
│   ├── mdrv_hvsp_io_st.h
│   ├── mdrv_isp_io.h
│   ├── mdrv_isp_io_st.h
│   ├── mdrv_ive_io.h
│   ├── mdrv_ive_io_st.h
│   ├── mdrv_jpe_io.h
│   ├── mdrv_jpe_io_st.h
│   ├── mdrv_mfe_io.h
│   ├── mdrv_mma_heap.h
│   ├── mdrv_mmfe_io.h
│   ├── mdrv_mmfe_st.h
│   ├── mdrv_msys_io.h
│   ├── mdrv_msys_io_st.h
│   ├── mdrv_mvhe_io.h
│   ├── mdrv_mvhe_st.h
│   ├── mdrv_padmux.h
│   ├── mdrv_pnl_io.h
│   ├── mdrv_pnl_io_st.h
│   ├── mdrv_puse.h
│   ├── mdrv_rqct_io.h
│   ├── mdrv_rqct_st.h
│   ├── mdrv_sar_io.h
│   ├── mdrv_sca_io.h
│   ├── mdrv_sca_st.h
│   ├── mdrv_scldma_io.h
│   ├── mdrv_scldma_io_i3.h
│   ├── mdrv_scldma_io_i3_st.h
│   ├── mdrv_scldma_io_st.h
│   ├── mdrv_sound_io.h
│   ├── mdrv_system.h
│   ├── mdrv_system_st.h
│   ├── mdrv_types.h
│   ├── mdrv_verchk.h
│   ├── mdrv_video.h
│   ├── mdrv_vip_io.h
│   ├── mdrv_vip_io_i3.h
│   ├── mdrv_vip_io_i3_st.h
│   ├── mdrv_vip_io_st.h
│   ├── mdrv_warp_io.h
│   ├── mdrv_warp_io_st.h
│   ├── mdrv_xpm_io.h
│   ├── mdrv_xpm_io_st.h
│   ├── ms_msys.h
│   ├── ms_platform.h
│   ├── _ms_private.h
│   ├── mstar_chip.h
│   ├── mst_platform.h
│   ├── ms_types.h
│   ├── MsTypes.h
│   ├── ms_version.h
│   ├── prom.h
│   ├── region_substract.h
│   ├── vcore_defs.h
│   └── voltage_ctrl.h
├── iopower
│   ├── Kconfig
│   ├── Makefile
│   └── mdrv_iopower.c
├── ir
│   ├── include
│   │   ├── IR_CONFIG.h
│   │   └── IR_MSTAR_DTV.h
│   ├── Kconfig
│   ├── Makefile
│   ├── ms_ir.c
│   ├── ms_ir.h
│   └── reg_ir.h
├── ircut
│   ├── Kconfig
│   ├── Makefile
│   └── ms_ircut.c
├── irqchip
│   ├── built-in.o
│   ├── infinity2
│   │   ├── irqchip.c
│   │   ├── irqchip_i2.c
│   │   ├── irq-gpi.c
│   │   ├── irq-pmsleep.c
│   │   └── Makefile
│   ├── infinity2m
│   │   ├── built-in.o
│   │   ├── irqchip.c
│   │   ├── irqchip.o
│   │   ├── irq-gpi.c
│   │   ├── irq-gpi.o
│   │   ├── irq-pmsleep.c
│   │   ├── irq-pmsleep.o
│   │   ├── Makefile
│   │   ├── modules.builtin
│   │   └── modules.order
│   ├── infinity3
│   │   └── irqchip.c
│   ├── infinity5
│   │   ├── irqchip.c
│   │   └── Makefile
│   ├── infinity6
│   │   ├── irqchip.c
│   │   ├── irq-gpi.c
│   │   ├── irq-pmsleep.c
│   │   └── Makefile
│   ├── infinity6b0
│   │   ├── irqchip.c
│   │   ├── irq-gpi.c
│   │   ├── irq-pmsleep.c
│   │   └── Makefile
│   ├── infinity6e
│   │   ├── irqchip.c
│   │   ├── irq-gpi.c
│   │   ├── irq-pmsleep.c
│   │   └── Makefile
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── isrcb
│   ├── drv
│   │   ├── pub
│   │   │   └── drv_isrcb.h
│   │   └── src
│   │       ├── common
│   │       │   └── drv_isrcb.c
│   │       └── linux
│   │           └── drv_isrcb_module.c
│   ├── Kconfig
│   └── Makefile
├── ive
│   ├── drv_ive.c
│   ├── drv_ive.h
│   ├── hal_clk.c
│   ├── hal_clk.h
│   ├── hal_debug.h
│   ├── hal_ive.c
│   ├── hal_ive.h
│   ├── hal_ive_reg.h
│   ├── hal_ive_simulate.c
│   ├── hal_ive_simulate.h
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_ive.c
│   └── mdrv_ive.h
├── Kconfig
├── Makefile
├── miu
│   ├── built-in.o
│   ├── infinity2
│   │   ├── mdrv_miu.c
│   │   └── mhal_miu.c
│   ├── infinity2m
│   │   ├── mdrv_miu.c
│   │   ├── mdrv_miu.o
│   │   ├── mhal_miu.c
│   │   └── mhal_miu.o
│   ├── infinity5
│   │   ├── mdrv_miu.c
│   │   └── mhal_miu.c
│   ├── infinity6
│   │   ├── mdrv_miu.c
│   │   └── mhal_miu.c
│   ├── infinity6b0
│   │   ├── mdrv_miu.c
│   │   └── mhal_miu.c
│   ├── infinity6e
│   │   ├── mdrv_miu.c
│   │   └── mhal_miu.c
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv-miu.o
│   ├── modules.builtin
│   ├── modules.order
│   └── MsTypes.h
├── mma_heap
│   ├── built-in.o
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_mma_heap.c
│   ├── mdrv_mma_heap.o
│   ├── mdrv-mma_heap.o
│   ├── modules.builtin
│   ├── modules.order
│   ├── region_substract.c
│   └── region_substract.o
├── modules.builtin
├── modules.order
├── movedma
│   ├── built-in.o
│   ├── hal_movedma.c
│   ├── hal_movedma.h
│   ├── hal_movedma.o
│   ├── Kconfig
│   ├── kernel_movedma.h
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── msys
│   ├── arm.include
│   ├── built-in.o
│   ├── infinity2
│   │   └── platform_msys.c
│   ├── infinity2m
│   │   ├── platform_msys.c
│   │   └── platform_msys.o
│   ├── infinity5
│   │   └── platform_msys.c
│   ├── infinity6
│   │   └── platform_msys.c
│   ├── infinity6b0
│   │   └── platform_msys.c
│   ├── infinity6e
│   │   └── platform_msys.c
│   ├── Kconfig
│   ├── macro.include
│   ├── Makefile
│   ├── memcpy.S
│   ├── miu_monitor.c
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_msys.c
│   ├── ms_msys_dma_wrapper.c
│   ├── ms_msys_dma_wrapper.o
│   ├── ms_msys_irq_stat.c
│   ├── ms_msys_irq_stat.o
│   ├── ms_msys_log.c
│   ├── ms_msys_memory_bench.c
│   ├── ms_msys_miu_protect.c
│   ├── ms_msys.o
│   ├── ms_msys_perf_test.c
│   └── platform_msys.h
├── netphy
│   ├── built-in.o
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── sstar_100_phy.c
│   └── sstar_100_phy.o
├── noe
│   ├── drv
│   │   ├── eth
│   │   │   ├── Kconfig
│   │   │   ├── Makefile
│   │   │   ├── mdrv_noe.c
│   │   │   ├── mdrv_noe_config.h
│   │   │   ├── mdrv_noe_def.h
│   │   │   ├── mdrv_noe_dma.h
│   │   │   ├── mdrv_noe_ethtool.c
│   │   │   ├── mdrv_noe_ethtool.h
│   │   │   ├── mdrv_noe.h
│   │   │   ├── mdrv_noe_ioctl.h
│   │   │   ├── mdrv_noe_log.c
│   │   │   ├── mdrv_noe_log.h
│   │   │   ├── mdrv_noe_lro.c
│   │   │   ├── mdrv_noe_lro.h
│   │   │   ├── mdrv_noe_lro_proc.c
│   │   │   ├── mdrv_noe_mac.c
│   │   │   ├── mdrv_noe_mac.h
│   │   │   ├── mdrv_noe_nat.h
│   │   │   ├── mdrv_noe_pdma.c
│   │   │   ├── mdrv_noe_phy.c
│   │   │   ├── mdrv_noe_phy.h
│   │   │   ├── mdrv_noe_proc.c
│   │   │   ├── mdrv_noe_proc.h
│   │   │   ├── mdrv_noe_qdma.c
│   │   │   ├── mdrv_noe_utils.c
│   │   │   └── mdrv_noe_utils.h
│   │   └── nat
│   │       ├── hook
│   │       │   ├── Makefile
│   │       │   └── mdrv_hook.c
│   │       └── hw_nat
│   │           ├── Kconfig
│   │           ├── Makefile
│   │           ├── mdrv_hwnat_api.c
│   │           ├── mdrv_hwnat_api.h
│   │           ├── mdrv_hwnat.c
│   │           ├── mdrv_hwnat_config.h
│   │           ├── mdrv_hwnat_define.h
│   │           ├── mdrv_hwnat_fast_path.h
│   │           ├── mdrv_hwnat_foe.c
│   │           ├── mdrv_hwnat_foe.h
│   │           ├── mdrv_hwnat.h
│   │           ├── mdrv_hwnat_ioctl.c
│   │           ├── mdrv_hwnat_ioctl.h
│   │           ├── mdrv_hwnat_log.c
│   │           ├── mdrv_hwnat_log.h
│   │           ├── mdrv_hwnat_mcast.c
│   │           ├── mdrv_hwnat_mcast.h
│   │           ├── mdrv_hwnat_util.c
│   │           └── mdrv_hwnat_util.h
│   ├── hal
│   │   └── infinity2
│   │       ├── mhal_hwnat.c
│   │       ├── mhal_hwnat_cfg.h
│   │       ├── mhal_hwnat_entry.h
│   │       ├── mhal_hwnat.h
│   │       ├── mhal_noe.c
│   │       ├── mhal_noe.c.an
│   │       ├── mhal_noe_dma.h
│   │       ├── mhal_noe.h
│   │       ├── mhal_noe_lro.h
│   │       ├── mhal_noe_reg.h
│   │       └── mhal_porting.h
│   ├── Kconfig
│   └── Makefile
├── notify
│   ├── Kconfig
│   ├── Makefile
│   └── ms_notify.c
├── padmux
│   ├── built-in.o
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_padmux.c
│   ├── mdrv_padmux.o
│   ├── modules.builtin
│   └── modules.order
├── pwm
│   ├── infinity
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity2
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity2m
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity3
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity5
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity6
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity6b0
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── infinity6e
│   │   ├── mhal_pwm.c
│   │   └── mhal_pwm.h
│   ├── Kconfig
│   ├── Makefile
│   └── mdrv_pwm.c
├── rebootstate
│   ├── Kconfig
│   ├── Makefile
│   └── reboot_state.c
├── rtc
│   ├── Kconfig
│   ├── Makefile
│   ├── ms_rtc.c
│   ├── ms_rtcpwc.c
│   └── reg
│       └── reg_rtcpwc.h
├── samples
│   ├── ajtc.c
│   ├── ajts.c
│   ├── build_riu.sh
│   ├── dmem.c
│   ├── README
│   ├── regio.c
│   ├── regio.png
│   ├── riu.c
│   ├── unametest.c
│   └── us_ticks.c
├── sar
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_sar.c
│   └── mdrv_sar.h
├── sata_host
│   ├── bench
│   │   ├── Makefile
│   │   └── sata_bench.c
│   ├── bench_test
│   │   ├── drv
│   │   │   ├── mhal_sata_bench_test.c
│   │   │   └── mhal_sata_bench_test.h
│   │   ├── include
│   │   │   ├── mdrv_sata_io.h
│   │   │   └── mdrv_sata_io_st.h
│   │   ├── Makefile
│   │   ├── mdrv_sata.h
│   │   ├── mdrv_sata_io.c
│   │   └── verify
│   │       ├── Makefile
│   │       ├── sata_test
│   │       ├── sata_test.c
│   │       └── sata_test.h
│   ├── built-in.o
│   ├── infinity2
│   │   ├── mhal_sata_host_ahci.c
│   │   ├── mhal_sata_host_ahci.h
│   │   ├── mhal_sata_host.c
│   │   └── mhal_sata_host.h
│   ├── infinity2m
│   │   ├── mhal_sata_host_ahci.c
│   │   ├── mhal_sata_host_ahci.h
│   │   ├── mhal_sata_host_ahci.o
│   │   ├── mhal_sata_host.c
│   │   ├── mhal_sata_host.h
│   │   └── mhal_sata_host.o
│   ├── Kconfig
│   ├── Makefile
│   ├── mdr_sata_host_ahci_platform1.c
│   ├── mdr_sata_host_ahci_platform.c
│   ├── mdr_sata_host_ahci_platform.o
│   ├── mdrv_sata_host1.c
│   ├── mdrv_sata_host_ahci1.c
│   ├── mdrv_sata_host_ahci.c
│   ├── mdrv_sata_host_ahci.h
│   ├── mdrv_sata_host.c
│   ├── mdrv_sata_host.h
│   ├── mdrv-sata-host.ko
│   ├── mdrv-sata-host.mod.c
│   ├── mdrv-sata-host.mod.o
│   ├── mdrv-sata-host.o
│   ├── modules.builtin
│   └── modules.order
├── sdmmc
│   ├── built-in.o
│   ├── inc
│   │   ├── hal_card_base.h
│   │   ├── hal_card_intr_v5.h
│   │   ├── hal_card_platform.h
│   │   ├── hal_card_regs.h
│   │   ├── hal_card_regs_v5.h
│   │   ├── hal_card_timer.h
│   │   ├── hal_sdmmc_v5.h
│   │   ├── infinity2m
│   │   │   ├── hal_card_platform_config.h
│   │   │   ├── hal_card_platform_pri_config.h
│   │   │   └── hal_card_platform_regs.h
│   │   ├── infinity5
│   │   │   ├── hal_card_platform_config.h
│   │   │   ├── hal_card_platform_pri_config.h
│   │   │   └── hal_card_platform_regs.h
│   │   ├── infinity6
│   │   │   ├── hal_card_platform_config.h
│   │   │   ├── hal_card_platform_pri_config.h
│   │   │   └── hal_card_platform_regs.h
│   │   ├── infinity6b0
│   │   │   ├── hal_card_platform_config.h
│   │   │   ├── hal_card_platform_pri_config.h
│   │   │   └── hal_card_platform_regs.h
│   │   ├── infinity6e
│   │   │   ├── hal_card_platform_config.h
│   │   │   ├── hal_card_platform_pri_config.h
│   │   │   └── hal_card_platform_regs.h
│   │   └── ms_sdmmc_lnx.h
│   ├── Kconfig
│   ├── kdrv_sdmmc.o
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_sdmmc_lnx.c
│   ├── ms_sdmmc_lnx.o
│   └── src
│       ├── hal_card_intr_v5.c
│       ├── hal_card_intr_v5.o
│       ├── hal_card_regs.c
│       ├── hal_card_regs.o
│       ├── hal_card_timer.c
│       ├── hal_card_timer.o
│       ├── hal_sdmmc_v5.c
│       ├── hal_sdmmc_v5.o
│       ├── infinity2m
│       │   ├── hal_card_platform.c
│       │   └── hal_card_platform.o
│       ├── infinity5
│       │   └── hal_card_platform.c
│       ├── infinity6
│       │   └── hal_card_platform.c
│       ├── infinity6b0
│       │   └── hal_card_platform.c
│       └── infinity6e
│           └── hal_card_platform.c
├── serial
│   ├── built-in.o
│   ├── infinity2
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── infinity2m
│   │   ├── ms_uart.h
│   │   ├── uart_pads.c
│   │   └── uart_pads.o
│   ├── infinity3e
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── infinity5
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── infinity6
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── infinity6b0
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── infinity6e
│   │   ├── ms_uart.h
│   │   └── uart_pads.c
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── ms_uart.c
│   └── ms_uart.o
├── spi
│   ├── infinity2
│   │   ├── Makefile
│   │   ├── mdrv_spi.c
│   │   └── mdrv_spi.h
│   ├── infinity2m
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── infinity3
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── infinity5
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── infinity6
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── infinity6b0
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── infinity6e
│   │   ├── Makefile
│   │   └── mspi.c
│   ├── Kconfig
│   └── Makefile
├── spinand
│   ├── built-in.o
│   ├── drv
│   │   ├── inc
│   │   │   ├── mdrv_spinand_command.h
│   │   │   └── mdrv_spinand_common.h
│   │   ├── mdrv_spinand.c
│   │   ├── mdrv_spinand.h
│   │   ├── mdrv_spinand_hal.c
│   │   ├── mdrv_spinand_hal.h
│   │   ├── mdrv_spinand_hal.o
│   │   └── mdrv_spinand.o
│   ├── hal
│   │   ├── infinity2
│   │   │   ├── mhal_spinand.c
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity2m
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand_chip_config.o
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity3
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity5
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity6
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity6b0
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── infinity6e
│   │   │   ├── mhal_spinand_chip_config.c
│   │   │   ├── mhal_spinand.h
│   │   │   └── reg_spinand.h
│   │   ├── mhal_spinand.c
│   │   └── mhal_spinand.o
│   ├── Kconfig
│   ├── kdrv_spinand.o
│   ├── Makefile
│   ├── modules.builtin
│   └── modules.order
├── usb
│   ├── gadget
│   │   └── udc
│   │       └── usb20
│   │           ├── include
│   │           │   ├── infinity5
│   │           │   │   └── msb250x_udc_common.h
│   │           │   ├── infinity6
│   │           │   │   └── msb250x_udc_common.h
│   │           │   ├── infinity6b0
│   │           │   │   └── msb250x_udc_common.h
│   │           │   ├── infinity6e
│   │           │   │   └── msb250x_udc_common.h
│   │           │   ├── msb250x_dma.h
│   │           │   ├── msb250x_ep.h
│   │           │   ├── msb250x_gadget.h
│   │           │   ├── msb250x_udc.h
│   │           │   └── msb250x_udc_reg.h
│   │           ├── Kconfig
│   │           ├── Makefile
│   │           └── src
│   │               ├── msb250x_dma.c
│   │               ├── msb250x_ep.c
│   │               ├── msb250x_gadget.c
│   │               └── msb250x_udc.c
│   ├── host
│   │   ├── bc-mstar.c
│   │   ├── bc-mstar.h
│   │   ├── bc-mstar.o
│   │   ├── built-in.o
│   │   ├── ehci-mstar.c
│   │   ├── ehci-mstar.h
│   │   ├── infinity2
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   └── usb_patch_mstar.h
│   │   ├── infinity2m
│   │   │   ├── built-in.o
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── modules.builtin
│   │   │   ├── modules.order
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   ├── usb_pad.o
│   │   │   └── usb_patch_mstar.h
│   │   ├── infinity3
│   │   │   ├── Makefile
│   │   │   └── ms_usb.c
│   │   ├── infinity5
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   └── usb_patch_mstar.h
│   │   ├── infinity6
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   └── usb_patch_mstar.h
│   │   ├── infinity6b0
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   └── usb_patch_mstar.h
│   │   ├── infinity6e
│   │   │   ├── ehci-mstar-chip.h
│   │   │   ├── Makefile
│   │   │   ├── usb_pad.c
│   │   │   ├── usb_pad.h
│   │   │   └── usb_patch_mstar.h
│   │   ├── Makefile
│   │   ├── modules.builtin
│   │   ├── modules.order
│   │   ├── mstar-lib.c
│   │   ├── mstar-lib.h
│   │   ├── mstar-lib.o
│   │   ├── usb_common_sstar.h
│   │   ├── xhci-mstar-chip.h
│   │   └── xhci-mstar.h
│   └── Kconfig
├── vcore_dvfs
│   ├── Kconfig
│   ├── Makefile
│   └── vcore_dvfs.c
├── voltage
│   ├── built-in.o
│   ├── infinity2m
│   │   ├── built-in.o
│   │   ├── Makefile
│   │   ├── modules.builtin
│   │   ├── modules.order
│   │   ├── voltage_request_init.c
│   │   └── voltage_request_init.o
│   ├── infinity5
│   │   ├── Makefile
│   │   └── voltage_request_init.c
│   ├── infinity6
│   │   ├── Makefile
│   │   └── voltage_request_init.c
│   ├── infinity6b0
│   │   ├── Makefile
│   │   └── voltage_request_init.c
│   ├── infinity6e
│   │   ├── Makefile
│   │   └── voltage_request_init.c
│   ├── Kconfig
│   ├── Makefile
│   ├── modules.builtin
│   ├── modules.order
│   ├── voltage_ctrl.c
│   ├── voltage_ctrl.o
│   └── voltage_request_init.h
├── warp
│   ├── drv
│   │   ├── inc
│   │   │   ├── dev_debug.h
│   │   │   ├── dev_warp.h
│   │   │   ├── lxdrv_warp.h
│   │   │   └── mhal_common.h
│   │   ├── pub
│   │   │   └── mhal_warp.h
│   │   └── src
│   │       ├── common
│   │       │   ├── dev_warp.c
│   │       │   └── mhal_warp.c
│   │       └── linux
│   │           ├── lxdrv_warp.c
│   │           └── warp_sample.c
│   ├── hal
│   │   ├── inc
│   │   │   └── hal_debug.h
│   │   ├── pub
│   │   │   ├── hal_ceva.h
│   │   │   ├── hal_ceva_reg.h
│   │   │   ├── hal_clk.h
│   │   │   ├── hal_warp_data.h
│   │   │   ├── hal_warp.h
│   │   │   └── hal_warp_reg.h
│   │   └── src
│   │       ├── hal_ceva.c
│   │       ├── hal_clk.c
│   │       └── hal_warp.c
│   ├── Kconfig
│   └── Makefile
├── watchdog
│   ├── Kconfig
│   ├── Makefile
│   ├── mdrv_wdt.c
│   └── mdrv_wdt.h
└── xpm
    ├── Kconfig
    ├── Makefile
    └── ms_xpm.c

316 directories, 1317 files

串口驱动程序位于这里: drivers/sstar/serial/ms_uart.c

/*
* ms_uart.c- Sigmastar
*
* Copyright (c) [2019~2020] SigmaStar Technology.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License version 2 for more details.
*
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
//#include <linux/serial_reg.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/nmi.h>
#include <linux/mutex.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>

#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/gpio.h>
#include <linux/timer.h>

#include "ms_platform.h"
#include "mdrv_types.h"
#include "gpio.h"
#include "ms_uart.h"
#include "cam_os_wrapper.h"
#define CONSOLE_DMA             1
#define DEBUG_PAD_MUX           0

#define UART_DEBUG 0
#define MS_UART_8250_BUG_THRE 0
#define UART_BUG_THRE   (1 << 3)        /* UART has buggy THRE reassertion */

#if UART_DEBUG
#define UART_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg)
#else
#define UART_DBG(fmt, arg...)
#endif
#define UART_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg)

//#define REG_UART_MODE          0x1F203C0C
//#define REG_UART_SEL           0x1F203D4C
//#define REG_UART_SEL4          0x1F203D50
#define REG_FORCE_RX_DISABLE   0x1F203D5C

#define UART_TX_TASK        0    /* use tasklet to send TX char */
#define UART_USE_LOOPBACK   0    /* use UART loopback mode to avoid external input */
#define UART_USE_SPINLOCK   0    /* set IER use spinlock to ensure atomic */

#if CONSOLE_DMA
#define NR_CONSOLE_PORTS 4
#else
#define NR_CONSOLE_PORTS 1
#endif
#define MS_CONSOLE_DEV "ttyS"

#define REG_DLL_THR_RBR(p)       GET_REG_ADDR((u32)p->membase, (0x00))
#define REG_DLH_IER(p)           GET_REG_ADDR((u32)p->membase, (0x02))
#define REG_IIR_FCR(p)           GET_REG_ADDR((u32)p->membase, (0x04))
#define REG_LCR(p)               GET_REG_ADDR((u32)p->membase, (0x06))
#define REG_MCR(p)               GET_REG_ADDR((u32)p->membase, (0x08))
#define REG_LSR(p)               GET_REG_ADDR((u32)p->membase, (0x0A))
#define REG_MSR(p)               GET_REG_ADDR((u32)p->membase, (0x0C))
#define REG_USR(p)               GET_REG_ADDR((u32)p->membase, (0x0E))
#define REG_TFL(p)               GET_REG_ADDR((u32)p->membase, (0x10))
#define REG_RFL(p)               GET_REG_ADDR((u32)p->membase, (0x12))
#define REG_RST(p)               GET_REG_ADDR((u32)p->membase, (0x14))

/* Interrupt Enable Register (IER)*/
#define UART_IER_RDI            0x01    /* Received Data Available Interrupt */
#define UART_IER_THRI           0x02    /* Transmitter Holding Register Empty Interrupt */
#define UART_IER_RLSI           0x04    /* Receiver Line Status Interrupt */
#define UART_IER_MSI            0x08    /* Modem Status Interrupt */

/* Interrupt Identification Register (IIR) */
#define UART_IIR_MSI            0x00    /* 0000: Modem Status */
#define UART_IIR_NO_INT         0x01    /* 0001: No pending interrupts */
#define UART_IIR_THRI           0x02    /* 0010: Transmitter Holding Register Empty */
#define UART_IIR_RDI            0x04    /* 0100: Receiver Data Available */
#define UART_IIR_RLSI           0x06    /* 0110: Receiver Line Status */
#define UART_IIR_BUSY           0x07    /* 0111: Busy detect indication (try to write LCR while UART is busy) */
#define UART_IIR_RX_TIMEOUT     0x0C    /* 1100: Character timeout */
#define UART_IIR_ID_MASK        0x0F    /* Mask Bit[3:0] for IIR */

/* FIFO Control Register (FCR) */
#define UART_FCR_FIFO_ENABLE    0x01    /* Clear & Reset Rx FIFO buffer */
#define UART_FCR_CLEAR_RCVR     0x02    /* Clear & Reset Rx FIFO buffer */
#define UART_FCR_CLEAR_XMIT     0x04    /* Clear & Reset Tx FIFO buffer */
#define UART_FCR_TRIGGER_TX_L0  0x00    /* Trigger Write when emtpy */
#define UART_FCR_TRIGGER_TX_L1  0x10    /* Trigger Write when 2 characters */
#define UART_FCR_TRIGGER_TX_L2  0x20    /* Trigger Write when 1/4 full */
#define UART_FCR_TRIGGER_TX_L3  0x30    /* Trigger Write when 1/2 full */
#define UART_FCR_TRIGGER_RX_L0  0x00    /* Trigger Read when there is 1 char*/
#define UART_FCR_TRIGGER_RX_L1  0x40    /* Trigger Read when 1/4 full */
#define UART_FCR_TRIGGER_RX_L2  0x80    /* Trigger Read when 1/2 full */
#define UART_FCR_TRIGGER_RX_L3  0xC0    /* Trigger Read when 2 less then full  */

/* Line Control Register (LCR) */
#define UART_LCR_WL_MASK        0x03    /* Word length mask */
#define UART_LCR_WLEN5          0x00    /* Word length is 5 bits */
#define UART_LCR_WLEN6          0x01    /* Word length is 6 bits */
#define UART_LCR_WLEN7          0x02    /* Word length is 7 bits */
#define UART_LCR_WLEN8          0x03    /* Word length is 8 bits */
#define UART_LCR_STOP_MASK      0x04    /* Stop bit mask */
#define UART_LCR_STOP1          0x00    /* Stop length is 1 bit */
#define UART_LCR_STOP2          0x04    /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */
#define UART_LCR_PARITY_EN      0x08    /* Parity Enable */
#define UART_LCR_PARITY_SEL     0x10    /* Even Parity Select */
#define UART_LCR_SBC            0x40    /* Set break control */
#define UART_LCR_DLAB           0x80    /* Divisor Latch Access bit, 1=Divisor Latch, 0=Normal Register */

#define UART_MCR_DTR            0x01
#define UART_MCR_RTS            0x02
#define UART_MCR_OUT1           0x04
#define UART_MCR_OUT2           0x08
#define UART_MCR_LOOPBACK       0x10
#define UART_MCR_AFCE           0x20

/* Line Status Register */
#define UART_LSR_DR             0x01    /* Data Ready, at least one char in FIFO buffer*/
#define UART_LSR_OE             0x02    /* Overrun Error, FIFO buffer is full */
#define UART_LSR_PE             0x04    /* Parity Error */
#define UART_LSR_FE             0x08    /* Framing Error, no valid stop bit */
#define UART_LSR_BI             0x10    /* Break Interrupt */
#define UART_LSR_THRE           0x20    /* Tx FIFO buffer is empty*/
#define UART_LSR_TEMT           0x40    /* Both TX FIFO buffer & shift register are empty */
#define UART_LSR_TX_ERROR       0x80    /* Tx FIFO buffer is error */

#define UART_USR_BUSY             0x01
#define UART_USR_TXFIFO_NOT_FULL  0x02
#define UART_USR_TXFIFO_EMPTY     0x04


#define UR2DMA_TX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN
#define UR2DMA_TX_BUF_MASK   0x0FFF
#define UR2DMA_RX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN

#define URDMA_RX_TIMEOUT 0x0F
#define URDMA_TX_TIMEOUT 0x0F

#define URDMA_RX_INTR_LEVEL 0x500 //need to think

#define URDMA_RX_INTR_TYPE_TIMEOUT   1
#define URDMA_RX_INTR_TYPE_THRESHOLD 2

#define URDMA_INTR_STATUS_RX 1
#define URDMA_INTR_STATUS_TX 2

#define URDMA_LOU16(u32Val)   ((U16)(u32Val)&0xFFFF)
#define URDMA_HIU16(u32Val)   ((U16)((u32Val) >> 16)&0x0FFF)

#define URDMA_logical2bus(x) (x&0x0FFFFFFF)

/* Warning: Little Endian */
typedef struct reg_urdma
{
    union
    {
        volatile U16 reg00;
        struct
        {
            volatile U16 sw_rst          :   1;  /* BIT0 */
            volatile U16 urdma_mode      :   1;  /* BIT1 */
            volatile U16 tx_urdma_en     :   1;  /* BIT2 */
            volatile U16 rx_urdma_en     :   1;  /* BIT3 */
            volatile U16 tx_endian       :   1;  /* BIT4 */
            volatile U16 rx_endian       :   1;  /* BIT5 */
            volatile U16 tx_sw_rst       :   1;  /* BIT6 */
            volatile U16 rx_sw_rst       :   1;  /* BIT7 */
            volatile U16 reserve00       :   3;  /* BIT8 ~ BIT10 */
            volatile U16 rx_op_mode      :   1;  /* BIT11 */
            volatile U16 tx_busy         :   1;  /* BIT12 */
            volatile U16 rx_busy         :   1;  /* BIT13 */
            volatile U16 reserve01       :   2;  /* BIT14 ~ BIT15 */
        } ;
    } ;
    U16 space00;

    union
    {
        volatile U16 reg01;
        struct
        {
            volatile U16 intr_threshold  :   12; /* BIT0 ~ BIT11 */
            volatile U16 reserve02       :   4;  /* BIT12 ~ BIT15 */
        } ;
    } ;
    U16 space01;

    union
    {
        volatile U16 reg02;
        struct
        {
            volatile U16 tx_buf_base_h   :   16;  /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space02;

    union
    {
        volatile U16 reg03;
        struct
        {
            volatile U16 tx_buf_base_l   :   16;  /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space03;

    union
    {
        volatile U16 reg04;
        struct
        {
            volatile U16 tx_buf_size     :   13;  /* BIT0 ~ BIT12 */
            volatile U16 reserve04       :   3;   /* BIT13 ~ BIT15 */
        } ;
    } ;
    U16 space04;

    union
    {
        volatile U16 reg05;
        struct
        {
            volatile U16 tx_buf_rptr     :   16;  /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space05;

    union
    {
        volatile U16 reg06;
        struct
        {
            volatile U16 tx_buf_wptr     :   16;  /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space06;

    union
    {
        volatile U16 reg07;
        struct
        {
            volatile U16 tx_timeout      :   4;   /* BIT0 ~ BIT3 */
            volatile U16 reserve05       :   12;  /* BIT4 ~ BIT15 */
        } ;
    } ;
    U16 space07;

    union
    {
        volatile U16 reg08;
        struct
        {
            volatile U16 rx_buf_base_h   :   16;  /* BIT0 ~ BIT7 */
        } ;
    } ;
    U16 space08;

    union
    {
        volatile U16 reg09;
        struct
        {
            volatile U16 rx_buf_base_l   :   16; /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space09;

    union
    {
        volatile U16 reg0a;
        struct
        {
            volatile U16 rx_buf_size     :   13; /* BIT0 ~ BIT12 */
            volatile U16 reserve07       :   3;  /* BIT13 ~ BIT15 */
        } ;
    } ;
    U16 space0a;

    union
    {
        volatile U16 reg0b;
        struct
        {
            volatile U16 rx_buf_wptr     :   16; /* BIT0 ~ BIT15 */
        } ;
    } ;
    U16 space0b;

    union
    {
        volatile U16 reg0c;
        struct
        {
            volatile U16 rx_timeout      :   4;  /* BIT0 ~ BIT3 */
            volatile U16 reserve08       :   12; /* BIT4 ~ BIT15 */
        } ;
    } ;
    U16 space0c;

    union
    {
        volatile U16 reg0d;
        struct
        {
            volatile U16 rx_intr_clr     :   1; /* BIT0 */
            volatile U16 rx_intr1_en     :   1; /* BIT1 */
            volatile U16 rx_intr2_en     :   1; /* BIT2 */
            volatile U16 reserve09       :   1; /* BIT3 */
            volatile U16 rx_intr1        :   1; /* BIT4 */
            volatile U16 rx_intr2        :   1; /* BIT5 */
            volatile U16 reserve0a       :   1; /* BIT6 */
            volatile U16 rx_mcu_intr     :   1; /* BIT7 */
            volatile U16 tx_intr_clr     :   1; /* BIT8 */
            volatile U16 tx_intr_en      :   1; /* BIT9 */
            volatile U16 reserve0b       :   5; /* BIT10 ~ BIT14 */
            volatile U16 tx_mcu_intr     :   1; /* BIT15 */
        } ;
    } ;
} reg_urdma;

struct ms_urdma
{
    reg_urdma *reg_base;
    unsigned int urdma_irq;
    u8 *rx_buf;
    u8 *tx_buf;
    dma_addr_t rx_urdma_base;
    dma_addr_t tx_urdma_base;
    u32 rx_urdma_size;
    u32 tx_urdma_size;
    u16 sw_rx_rptr;
};


struct ms_uart_port {
    struct uart_port    port;
    struct ms_urdma    *urdma;
    struct device      *dev;
    struct clk         *clk;
    int use_dma;
#if UART_TX_TASK
    struct tasklet_struct xmit_tasklet;
#endif
    int rx_guard;
    u8 backupIER;
    u8 backupLCR;
    u8 backupMCR;
    u16 backupDivisor;
    u8 padmux;
    u8 pad_mode;
    u8 rs485_gpio_flag;
    struct timer_list   timer;          /* "no irq" timer */
    u16 bugs;           /* port bugs */
    CamOsThread urdma_task;
};

static u32 ms_uart_tx_empty(struct uart_port *p);
static void ms_uart_set_mctrl(struct uart_port *pPort_st, u32 mctrl);
static u32 ms_uart_get_mctrl(struct uart_port *pPort_st);
static void ms_uart_stop_tx(struct uart_port *p);
static void ms_uart_start_tx(struct uart_port *p);
static void ms_uart_stop_rx(struct uart_port *p);
static void ms_uart_enable_ms(struct uart_port *pPort_st);
static void ms_uart_break_ctl(struct uart_port *pPort_st, s32 break_state);
static s32 ms_uart_startup(struct uart_port *p);
static void ms_uart_shutdown(struct uart_port *p);
static void ms_uart_set_termios(struct uart_port *p, struct ktermios *pTermios_st, struct ktermios *pOld_st);
static const char * ms_uart_type(struct uart_port *pPort_st);
static void ms_uart_release_port(struct uart_port *pPort_st);
static void ms_uart_release_port(struct uart_port *pPort_st);
static s32 ms_uart_request_port(struct uart_port *pPort_st);
static void ms_uart_config_port(struct uart_port *pPort_st, s32 flags);
static s32 ms_uart_verify_port(struct uart_port *pPort_st, struct serial_struct *ser);

/* UART Operations */
static struct uart_ops ms_uart_ops =
{
    .tx_empty     = ms_uart_tx_empty,
    .set_mctrl    = ms_uart_set_mctrl,     /* Not supported in MSB2501 */
    .get_mctrl    = ms_uart_get_mctrl,     /* Not supported in MSB2501 */
    .stop_tx      = ms_uart_stop_tx,
    .start_tx     = ms_uart_start_tx,
    .stop_rx      = ms_uart_stop_rx,
    .enable_ms    = ms_uart_enable_ms,     /* Not supported in MSB2501 */
    .break_ctl    = ms_uart_break_ctl,     /* Not supported in MSB2501 */
    .startup      = ms_uart_startup,
    .shutdown     = ms_uart_shutdown,
    .set_termios  = ms_uart_set_termios,
    .type         = ms_uart_type,          /* Not supported in MSB2501 */
    .release_port = ms_uart_release_port,  /* Not supported in MSB2501 */
    .request_port = ms_uart_request_port,  /* Not supported in MSB2501 */
    .config_port  = ms_uart_config_port,   /* Not supported in MSB2501 */
    .verify_port  = ms_uart_verify_port,   /* Not supported in MSB2501 */
};

static void ms_uart_console_write(struct console *co, const char *str, u32 count);
static s32 ms_uart_console_setup(struct console *co, char *options);
#if CONSOLE_DMA
static s32 _ms_uart_console_prepare(int idx);
static int ms_uart_console_match(struct console *co, char *name, int idx, char *options);
static void *urdma_tx_thread(void * arg);
static int _urdma_tx(struct ms_uart_port *mp, unsigned char* buf, int buf_size);
static DEFINE_SPINLOCK(mutex_console_2_dma);
#else
static void ms_uart_add_console_port(struct ms_uart_port *ur);
static struct ms_uart_port *console_ports[NR_CONSOLE_PORTS];
#endif
static struct ms_uart_port  console_port;
static struct uart_driver ms_uart_driver;

/* Serial Console Structure Definition */
static struct console ms_uart_console =
{
    .name   = MS_CONSOLE_DEV,
    .write  = ms_uart_console_write,
    .setup  = ms_uart_console_setup,
    .flags  = CON_PRINTBUFFER,
        .device = uart_console_device,
        .data   = &ms_uart_driver,
    .index  = -1,
#if CONSOLE_DMA
    .match = ms_uart_console_match,
#endif
};


static struct uart_driver ms_uart_driver = {
    .owner        = THIS_MODULE,
    .driver_name    = "ms_uart",
    .dev_name    = "ttyS",
    .nr        = 8,
    .cons        = &ms_uart_console,
};

static DECLARE_WAIT_QUEUE_HEAD(urdma_wait);
static volatile int urdma_conditions = 0;

// extern void Chip_UART_Disable_Line(int line);
// extern void Chip_UART_Enable_Line(int line);

static void URDMA_Reset(struct uart_port *p);
static void URDMA_Activate(struct uart_port *p,BOOL bEnable);
static void URDMA_TxEnable(struct uart_port *p,BOOL bEnable);
static void URDMA_RxEnable(struct uart_port *p,BOOL bEnable);
static U8 URDMA_GetInterruptStatus(struct uart_port *p);
static void URDMA_TxInit(struct uart_port *p);
static void URDMA_RxInit(struct uart_port *p);
static void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable);
static void URDMA_TxClearInterrupt(struct uart_port *p);
static void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout);
static void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold);
static U8 URDMA_RxGetInterrupt(struct uart_port *p);
static void URDMA_RxClearInterrupt(struct uart_port *p);
static void URDMA_StartTx(struct uart_port *p);
static void URDMA_StartRx(struct uart_port *p);
static int ms_uart_rs485_gpio(struct serial_rs485 *rs485,bool send)
{
    UART_ERR("delay:%d,%d\n",rs485->delay_rts_before_send,rs485->delay_rts_before_send);
    if ((rs485->flags & SER_RS485_ENABLED) && send)
    {
        if(rs485->delay_rts_before_send)udelay(rs485->delay_rts_before_send);
        if(rs485->flags&SER_RS485_RTS_ON_SEND)
        {
            gpio_set_value(rs485->padding[0],1);UART_ERR("wend set higt\n");
        }
        else
        {
            gpio_set_value(rs485->padding[0],0);UART_ERR("send set low\n");
        }
    }
    else if ((rs485->flags & SER_RS485_ENABLED) && !send)
    {
        if(rs485->delay_rts_after_send)udelay(rs485->delay_rts_after_send);
        if(rs485->flags&SER_RS485_RTS_AFTER_SEND)
        {
            gpio_set_value(rs485->padding[0],1);UART_ERR("after set higt\n");
        }
        else
        {
            gpio_set_value(rs485->padding[0],0);UART_ERR("after set low\n");
        }
    }
    return 0;
}
static int ms_uart_rs485_config(struct uart_port *port,
                   struct serial_rs485 *rs485)
{
    if (rs485->flags & SER_RS485_ENABLED) {
        UART_ERR("uart %d set 485 on,pin RTS:%d\n", port->line,rs485->padding[0]);
        if(gpio_request(rs485->padding[0], "gpio_irq_test") < 0)
        {
            UART_ERR("request gpio[%d] failed...\n", rs485->padding[0]);
            return -EFAULT;
        }
        if(rs485->flags&SER_RS485_RTS_ON_SEND)
        {
            if(gpio_direction_output(rs485->padding[0],0) < 0)
            {
                UART_ERR("gpio_direction_output low[%d] failed...\n", rs485->padding[0]);
                return -EFAULT;
            }
        }
        else
        {
            if(gpio_direction_output(rs485->padding[0],1) < 0)
            {
                UART_ERR("gpio_direction_output high[%d] failed...\n", rs485->padding[0]);
                return -EFAULT;
            }
        }
        UART_ERR("rs485->flags=0x%x\n",rs485->flags);
    }
    else {
        UART_ERR("uart %d set 485 off\n", port->line);
        gpio_free(rs485->padding[0]);
    }
    memcpy(&port->rs485, rs485, sizeof(*rs485));
    return 0;
}
void inline ms_uart_clear_fifos(struct uart_port *p)
{
    unsigned int timeout=0;

    while( ((INREG8(REG_USR(p)) & UART_USR_BUSY)) && timeout < 2000)
        timeout++;
    OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE);
    OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
    OUTREG8(REG_IIR_FCR(p), 0);
}

static u8 u8SelectPad[] = { 2, 3, 1, 4 };
void ms_select_pad(struct uart_port *p, u8 padmux, u8 pad_mode)
{
#if 0
    u8 select=0;

    if(p->line == 0)
        select=2;
    else if(p->line == 1)
        select=3;
    else if(p->line == 2)
        select=1;
    else if(p->line == 3)
        select=4;
    else
    {
        // UART_ERR("[%s] port line %d is not supported\n", __func__, p->line);
        return;
    }

    ms_uart_select_pad(select, padmux, pad_mode);
#else
    ms_uart_select_pad(u8SelectPad[p->line], padmux, pad_mode);
#endif
}

void ms_force_rx_disable(u8 padmux, BOOL status)
{
    switch(padmux)  //set 0 for disable, 1 for enable
    {
        case MUX_PM_UART:
            OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 2, 1 << 2);
            break;
        case MUX_FUART:
            OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 0, 1 << 0);
            break;
        case MUX_UART0:
            OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 1, 1 << 1);
            break;
        case MUX_UART1:
            OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 3, 1 << 3);
            break;
#ifdef CONFIG_MS_SUPPORT_UART2
        case MUX_UART2:
            OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 4, 1 << 4);
            break;
#endif
        default:
            // UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux);
            break;
    }
}

U16 ms_uart_set_clk(struct uart_port *p, u32 request_baud)
{
    //struct clk *clk;
    unsigned int num_parents;
    struct clk **clk_parents;
    unsigned int tolerance, rate, divisor, real_baud;
    struct ms_uart_port *mp;
    int i;

    if(!p->dev)
    {
        //do nothing because clk and device node not ready
        return 0;
    }
    else
    {
        mp = (struct ms_uart_port*)(p->dev->driver_data);
        if (IS_ERR(mp->clk)) {
            // UART_ERR("%s: of_clk_get failed\n", p->dev->of_node->full_name);
            p->uartclk=172800000;
            return 0;
        }
        if(of_property_read_u32(p->dev->of_node, "tolerance", &tolerance))
        {
            UART_DBG("%s: use default tolerance 3%%\n", __func__);
            tolerance = 3;
        }

        num_parents = clk_hw_get_num_parents(__clk_get_hw(mp->clk));

        if(!num_parents)
        {
            rate=clk_get_rate(mp->clk);
            divisor = (rate + (8*request_baud)) / (16*request_baud);
            real_baud = rate / (16 * divisor);
            // UART_ERR("[uart%d]divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate);
            if( (abs(real_baud - request_baud)*100/request_baud) < tolerance)
            {
                p->uartclk=rate;
                // UART_ERR("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor);
            }
            return divisor;
        }
        else
        {
            clk_parents = kzalloc((sizeof(*clk_parents) * num_parents), GFP_KERNEL);
            if(!clk_parents)
            {
                // UART_ERR("%s: failed to allocate memory\n", __func__);
                kfree(clk_parents);
                p->uartclk=clk_get_rate(mp->clk);
                return 0;
            }

            for(i = 0; i < num_parents; i++)
            {
                clk_parents[i] = clk_hw_get_parent_by_index(__clk_get_hw(mp->clk), i)->clk;
                rate = clk_get_rate(clk_parents[i]);
                divisor = (rate + (8*request_baud)) / (16*request_baud);
                real_baud = rate / (16 * divisor);

                UART_DBG("[uart%d]foreach parent divisor=0x%02X, real_baud=%d,uart_clk=%d\n", p->line, divisor, real_baud,rate);
                if( (abs(real_baud - request_baud)*100/request_baud) < tolerance)
                {
                    clk_set_parent(mp->clk, clk_parents[i]);
                    p->uartclk=rate;
                    UART_DBG("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor);
                    break;
                }
            }

            if(i >= num_parents)
            {
                // UART_ERR("[uart%d] can't find suitable clk for baud=%d tolerance=%d%%, will not changed\n", p->line, request_baud, tolerance);
                divisor = 0;
            }
            kfree(clk_parents);
            return divisor;
        }
    }
}

void ms_uart_set_divisor(struct uart_port *p, u16 divisor)
{
    ms_uart_clear_fifos(p);

    // enable Divisor Latch Access, so Divisor Latch register can be accessed
    OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) | UART_LCR_DLAB);
    OUTREG8(REG_DLH_IER(p), (u8 )((divisor >> 8) & 0xff));
    OUTREG8(REG_DLL_THR_RBR(p), (u8 )(divisor & 0xff));
    // disable Divisor Latch Access
    OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) & ~UART_LCR_DLAB);
}

static void ms_uart_console_putchar(struct uart_port *p, s32 ch)
{
    u8  lsr_u8  = 0;    /* Line Status Register (LSR) */

    /* Check if Transmit FIFO full */
    /* we can not modify the Tx FIFO size, default is 1 byte size*/

    lsr_u8 = INREG8(REG_LSR(p));
    while(!(lsr_u8 & UART_LSR_THRE))
    {
        lsr_u8 = INREG8(REG_LSR(p));
    }

    OUTREG8(REG_DLL_THR_RBR(p),ch);

    /* Check if both TX FIFO buffer & shift register are empty */
    //lsr_u8 = INREG8(REG_LSR(p));
    //while((lsr_u8 & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE))
    //{
    //    lsr_u8 = INREG8(REG_LSR(p));
    //}
}

#if CONSOLE_DMA
static void __maybe_unused ms_uart_console_putchar_dma(struct uart_port *p, s32 ch)
{
    unsigned char c = (unsigned char)(ch & 0xFF);

    while (1 != _urdma_tx(&console_port, &c, 1));
}

static int ms_uart_console_match(struct console *co, char *name, int idx, char *options)
{
    co->index = idx;
    return -ENODEV;
}
#endif

#if CONSOLE_DMA
static s32 _ms_uart_console_prepare(int idx)
{
    struct device_node *console_np;
    struct resource res;

    char* uart_name[] =
        {
            "/soc/uart0@1F221000",
            "/soc/uart1@1F221200",
            "/soc/uart2@1F220400",
            "/soc/uart2@1F221400",
        };
    if ((0 > idx) || (NR_CONSOLE_PORTS <= idx))
        return -ENODEV;
    console_np=of_find_node_by_path(uart_name[idx]);
    if(!console_np)
    {
        console_np =of_find_node_by_path("console");
        idx = 0;
    }
    if(!console_np)
        return -ENODEV;

    BUG_ON( of_address_to_resource(console_np,0,&res) );

    console_port.port.membase = (void *)res.start;

    console_port.port.type = PORT_8250;

    console_port.port.ops=&ms_uart_ops;
    console_port.port.regshift = 0;
    console_port.port.fifosize = 16;
    console_port.port.cons=&ms_uart_console;

    console_port.port.line= idx;
    ms_uart_console.index = console_port.port.line;

    return 0;
}

#define UART_RX        (0 * 2)  // In:  Receive buffer (DLAB=0)
#define UART_TX        (0 * 2)  // Out: Transmit buffer (DLAB=0)
#define UART_DLL       (0 * 2)  // Out: Divisor Latch Low (DLAB=1)
#define UART_DLM       (1 * 2)  // Out: Divisor Latch High (DLAB=1)
#define UART_IER       (1 * 2)  // Out: Interrupt Enable Register
#define UART_IIR       (2 * 2)  // In:  Interrupt ID Register
#define UART_FCR       (2 * 2)  // Out: FIFO Control Register
#define UART_LCR       (3 * 2)  // Out: Line Control Register
#define UART_MCR       (4 * 2)  // Out: Modem Control Register
#define UART_LSR       (5 * 2)  // In:  Line Status Register
#define UART_MSR       (6 * 2)  // In:  Modem Status Register
#define UART_USR       (7 * 2)  // Out: USER Status Register
#define UART_RST      (14 * 2)  // Out: SW rstz

// #define REG_ADDR_BASE_UART1 0xFD221200
// #define REG_ADDR_BASE_FUART 0xFD220400
#define UART_BASE        IO_ADDRESS(console_port.port.membase)
#define UART_REG8(_x_)  ((U8 volatile *)(UART_BASE))[((_x_) * 4) - ((_x_) & 1)]

    #define UART_BAUDRATE       115200
    #define UART_CLK            172800000

#define UART_LCR_PARITY             0x08
#define UART_FCR_ENABLE_FIFO        0x01

// #define REG_UART_SEL3210    GET_REG16_ADDR(REG_ADDR_BASE_CHIPTOP, 0x53)
// #define REG_RX_ENABLE       GET_REG16_ADDR(REG_ADDR_BASE_PM_SLEEP, 0x09)
// #define REG_UART0_CLK       GET_REG16_ADDR(REG_ADDR_BASE_CLKGEN, 0x31)

void uart_init(void)
{
    U8 count=0;

#if 0
    // Enable uart0 clock
    OUTREG8(REG_UART0_CLK, 0x09);  //clk_xtal and gating
    CLRREG8(REG_UART0_CLK, 0x01);  //clear gating

    // Reset RX_enable
    CLRREG16(REG_RX_ENABLE, BIT11);

    // Reset PM uart pad digmux
    OUTREG16(REG_UART_SEL3210, 0x3210);
#endif

    // Toggle SW reset
    UART_REG8(UART_RST) &= ~0x01;
    UART_REG8(UART_RST) |= 0x01;

    // Disable all interrupts
    UART_REG8(UART_IER) = 0x00;

    // Set "reg_mcr_loopback";
    UART_REG8(UART_MCR) |= 0x10;

    // Poll "reg_usr_busy" till 0; (10 times)
    while(UART_REG8(UART_USR) & 0x01 && count++ < 10)
        ;

    if(count == 10)
    {
        // SetDebugFlag(FLAG_INIT_UART_BUSY); /* 0x0BF1 */
    }
    else // Set divisor
    {
        U16 DLR = ((UART_CLK+(8*UART_BAUDRATE)) / (16 * UART_BAUDRATE));
        UART_REG8(UART_LCR) |= UART_LCR_DLAB;
        UART_REG8(UART_DLL) = DLR & 0xFF;
        UART_REG8(UART_DLM) = (DLR >> 8) & 0xFF;
        UART_REG8(UART_LCR) &= ~(UART_LCR_DLAB);
    }

    // Set 8 bit char, 1 stop bit, no parity
    UART_REG8(UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP2 | UART_LCR_PARITY);

    // Unset loopback
    UART_REG8(UART_MCR) &= ~0x10;

    // Enable TX/RX fifo
    UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;;
#if 0
    // Set PM uart pad digmux to UART0
    OUTREG16(REG_UART_SEL3210, 0x3012);

    // Set RX_enable
    SETREG16(REG_RX_ENABLE, BIT11);
#endif
}
#endif


#if CONSOLE_DMA
static void ms_uart_console_write(struct console *co, const char *str, u32 count)
{
    struct ms_uart_port *mp;
    struct uart_port *p;
    unsigned long flags;
    int locked = 1;

    if( (!str )|| co->index>=NR_CONSOLE_PORTS || co->index < 0)
    {
        return;
    }

    mp = &console_port;
    p = &(mp->port);

    if (p->sysrq || oops_in_progress)
        locked = spin_trylock_irqsave(&p->lock, flags);
    else
        spin_lock_irqsave(&p->lock, flags);

    if(!mp->use_dma)
        uart_console_write(p, str, count, ms_uart_console_putchar);
    else if (mp->urdma)
    {
        uart_console_write(p, str, count, ms_uart_console_putchar_dma);
    }

    if (locked)
        spin_unlock_irqrestore(&p->lock, flags);

    return;
}

static s32 __init ms_uart_console_setup(struct console *co, char *options)
{
    /* Define Local Variables */
    s32 baud =115200;
    s32 bits = 8;
    s32 parity = 'n';
    s32 flow = 'n';

    if(!options)
    {
        options = "115200n8r"; /* Set default baudrate for console*/
    }

    /* parsing the command line arguments */
    uart_parse_options(options, &baud, &parity, &bits, &flow);
    _ms_uart_console_prepare(co->index);
    if (co->index)
        uart_init();
#if DEBUG_PAD_MUX
    {
        *((volatile int*)(0xFD203D4C)) &= 0xFFF0;
        // *((volatile int*)(0xFD203D4C)) |= 0x0003;
        *((volatile int*)(0xFD203D4C)) |= (u8SelectPad[co->index] & 0xF);
    }
#endif

    return uart_set_options(&(console_port.port), co, baud, parity, bits, flow);
}
#else // #if CONSOLE_DMA

static void ms_uart_console_write(struct console *co, const char *str, u32 count)
{
    struct ms_uart_port *mp;
    struct uart_port *p;
    unsigned long flags;
    int locked = 1;

    if( (!str )|| co->index>=NR_CONSOLE_PORTS || co->index < 0)
    {
        return;
    }

    mp = console_ports[co->index];
    p = &(mp->port);

    if (p->sysrq || oops_in_progress)
        locked = spin_trylock_irqsave(&p->lock, flags);
    else
        spin_lock_irqsave(&p->lock, flags);

    if(!mp->use_dma)
        uart_console_write(p, str, count, ms_uart_console_putchar);

    if (locked)
        spin_unlock_irqrestore(&p->lock, flags);

    return;
}

static s32 __init ms_uart_console_setup(struct console *co, char *options)
{
    /* Define Local Variables */
    s32 baud =115200;
    s32 bits = 8;
    s32 parity = 'n';
    s32 flow = 'n';

    if(!options)
    {
        options = "115200n8r"; /* Set default baudrate for console*/
    }

    /* validate console port index */
    if(co->index == -1 || co->index >= NR_CONSOLE_PORTS)
    {
        co->index = 0;
    }
    /* parsing the command line arguments */
    uart_parse_options(options, &baud, &parity, &bits, &flow);

    if(console_ports[co->index]==NULL){
        return -ENODEV;
    }

    return uart_set_options(&(console_ports[co->index]->port), co, baud, parity, bits, flow);
}

static void ms_uart_add_console_port(struct ms_uart_port *ur)
{
    if(ur->port.line < NR_CONSOLE_PORTS )
    {
        console_ports[ur->port.line] = ur;
    }
}
#endif // #if CONSOLE_DMA

static const char * ms_uart_type(struct uart_port *pPort_st)
{
    return NULL;
}

static void ms_uart_release_port(struct uart_port *pPort_st)
{

}

static s32 ms_uart_request_port(struct uart_port *pPort_st)
{
    int ret=0;
    return ret;
}

static void ms_uart_config_port(struct uart_port *pPort_st, s32 flags)
{

}

static s32 ms_uart_verify_port(struct uart_port *pPort_st, struct serial_struct *ser)
{
    int ret=0;
    return ret;
}


static void ms_uart_enable_ms(struct uart_port *pPort_st)
{

}

static u32 ms_uart_get_mctrl(struct uart_port *pPort_st)
{
    return (TIOCM_CAR|TIOCM_CTS|TIOCM_DSR);
}

static void ms_uart_set_mctrl(struct uart_port *pPort_st, u32 mctrl)
{

}


static void ms_uart_break_ctl(struct uart_port *pPort_st, s32 break_state)
{

}


static void ms_uart_stop_tx(struct uart_port *p)
{
    struct ms_uart_port *mp = (struct ms_uart_port*)(p->dev->driver_data);
    if(!mp->use_dma)
    {
#if UART_USE_SPINLOCK
        unsigned long flags;
        spin_lock_irqsave(&p->lock, flags);
        CLRREG8(REG_DLH_IER(p), UART_IER_THRI);
        spin_unlock_irqrestore(&p->lock, flags);
#else
        CLRREG8(REG_DLH_IER(p), UART_IER_THRI);
    //NOTE: Read IIR to clear dummy THRI after disable THRI occurred at ZEBU -- Spade
        INREG8(REG_IIR_FCR(p));
#endif
    }
    else
    {
//        printk(KERN_ERR "DMA_TX_STOP\n");
        URDMA_TxSetupTimeoutInterrupt(p, FALSE);
    }
    if ((p->rs485.flags & SER_RS485_ENABLED) && mp->rs485_gpio_flag)
    {
        while( !( INREG8(REG_USR(p)) & UART_USR_TXFIFO_EMPTY ) );
        ms_uart_rs485_gpio(&p->rs485,false);
        mp->rs485_gpio_flag = 0;
    }
}

static void ms_uart_stop_rx(struct uart_port *p)
{
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;

    if(!mp->use_dma)
    {
#if UART_USE_SPINLOCK
        unsigned long flags;
        spin_lock_irqsave(&p->lock, flags);
        CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI);
        spin_unlock_irqrestore(&p->lock, flags);
#else
        CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI);
#endif
    }
}

static void ms_uart_start_tx(struct uart_port *p)
{
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;
    struct circ_buf *xmit = &p->state->xmit;

    if(CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE) && (p->rs485.flags & SER_RS485_ENABLED))
    {
        mp->rs485_gpio_flag = 1;
    }

    if ((p->rs485.flags & SER_RS485_ENABLED) && mp->rs485_gpio_flag) {
        ms_uart_rs485_gpio(&p->rs485,true);
    }

    if(!mp->use_dma)
    {
#if UART_USE_SPINLOCK
        unsigned long flags;
        spin_lock_irqsave(&p->lock, flags);
        SETREG8(REG_DLH_IER(p), UART_IER_THRI);
        spin_unlock_irqrestore(&p->lock, flags);
#else
        SETREG8(REG_DLH_IER(p), UART_IER_THRI);
#endif
    }
    else
    {
//        pr_err("DMA_TX_START\n");
        URDMA_TxSetupTimeoutInterrupt(p, TRUE);
        URDMA_StartTx(p);
    }
}

static u32 ms_uart_tx_empty(struct uart_port *p)
{
    int ret=0;
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;

    if(!mp->use_dma)
    {
        /* Check if both TX FIFO buffer & shift register are empty */
        if((INREG8(REG_LSR(p)) & (UART_LSR_TEMT | UART_LSR_THRE)) == (UART_LSR_TEMT | UART_LSR_THRE))
        {
            ret=TIOCSER_TEMT; /*if no support, also return this */
        }

    }
    else
    {
        if(mp->urdma->reg_base->tx_buf_rptr == mp->urdma->reg_base->tx_buf_wptr)
        {
            return TIOCSER_TEMT; /*if no support, also return this */
        }
        else
        {
            return 0;
        }
    }

    return ret;
}

#if UART_TX_TASK
static void ms_do_xmit_task(unsigned long port_address)
{
    /* Define Local Variables */
    s32 count = 0;
    struct circ_buf *xmit;
    u8 u8USR = 0;
    struct uart_port* p = (struct uart_port*) ((void *) port_address);

    /* Parameter out-of-bound check */
    if (!p)
    {
        // UART_ERR("ms_do_xmit_task: port is NULL\n");
        return;
    }

    xmit = &p->state->xmit;

    if (p->x_char)
    {

        while( !( INREG8(REG_LSR(p)) & UART_LSR_THRE ) )
        {
            //nothing to do
        }

        OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]);
        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
        p->icount.tx++;
        p->x_char = 0;
        return;
    }

    if (uart_circ_empty(xmit) || uart_tx_stopped(p))
    {
        ms_uart_stop_tx(p);
        return;
    }

    u8USR = INREG8(REG_USR(p));
    if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty
    {
        count = p->fifosize;
    }
    else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full
    {
        count = 1;
    }

    do {
        OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]);
        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
        p->icount.tx++;

        if (uart_circ_empty(xmit))
        {
            break;
        }
    } while (--count > 0);

    if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
        uart_write_wakeup(p);

    if (uart_circ_empty(xmit))
    {
        ms_uart_stop_tx(p);
        return;
    }

#if UART_USE_SPINLOCK
    {
        unsigned long flags;
        spin_lock_irqsave(&p->lock, flags);
        SETREG8(REG_DLH_IER(p), UART_IER_THRI);
        spin_unlock_irqrestore(&p->lock, flags);
    }
#else
    SETREG8(REG_DLH_IER(p), UART_IER_THRI);
#endif
    return;
}

#else  // UART_TX_TASK = 0
static void ms_putchar(struct uart_port *p)
{

     /* Define Local Variables */
    int count;
    struct circ_buf *xmit;
    u8 u8USR = 0;

    /* Parameter out-of-bound check */
    if (!p)
    {
        // UART_ERR("ms_putchar: port is NULL\n");
        return;
    }

    xmit = &p->state->xmit;

    if (p->x_char)
    {
        while( !( INREG8(REG_USR(p)) & UART_USR_TXFIFO_NOT_FULL ) )
        {
            //nothing to do
        }
        OUTREG8(REG_DLL_THR_RBR(p), p->x_char);
        p->icount.tx++;
        p->x_char = 0;
        return;
    }

    if (uart_circ_empty(xmit) || uart_tx_stopped(p))
    {
        ms_uart_stop_tx(p);
        return;
    }

    u8USR = INREG8(REG_USR(p));

    if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty
    {
        count = p->fifosize;
    }
    else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full
    {
        count = 1;
    }else
    {
        count = 1;
    }

    do {
        OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]);

        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
        p->icount.tx++;

        if (uart_circ_empty(xmit))
        {
            break;
        }
    } while (--count > 0);

    if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
        uart_write_wakeup(p);

    if (uart_circ_empty(xmit))
    {
        ms_uart_stop_tx(p);
    }
}
#endif

static int silent_state = 0;
static void ms_getchar(struct uart_port *p)
{
    u8  lsr = 0;    /* Line Status Register (LSR) */
    u32 flag = 0;
    u32 ch = 0;    /* Character read from UART port */
    int max_count = p->fifosize;
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;
    static u8 rx_disable = 0, pad_disable = 0;
    unsigned long flags;
    char isConsole = (console_port.port.line == mp->port.line) ? 1 : 0;

    spin_lock_irqsave(&p->lock, flags);

    /* Read Line Status Register */
    lsr = INREG8(REG_LSR(p));

    /* check if Receiver Data Ready */
    if((lsr & UART_LSR_DR) != UART_LSR_DR)
    {
        mp->rx_guard++;
        if(unlikely(mp->rx_guard>2000))
        {
            ch=INREG8(REG_DLL_THR_RBR(p));
            UART_ERR("rx interrupts error!!!!!");
            mp->rx_guard=0;
        }
        /* Data NOT Ready */
        spin_unlock_irqrestore(&p->lock, flags);
        return ;
    }
    mp->rx_guard=0;

    /* while data ready, start to read data from UART FIFO */
    do{
        flag = TTY_NORMAL;
        /* read data from UART IP */
        ch = INREG8(REG_DLL_THR_RBR(p));
        p->icount.rx++;

        if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | UART_LSR_FE | UART_LSR_OE)))
        {
            if (lsr & UART_LSR_BI) {
                lsr &= ~(UART_LSR_FE | UART_LSR_PE);
                p->icount.brk++;
                /*
                 * We do the SysRQ and SAK checking
                 * here because otherwise the break
                 * may get masked by ignore_status_mask
                 * or read_status_mask.
                 */
                if (uart_handle_break(p))
                    goto IGNORE_CHAR;
            }
            else if (lsr & UART_LSR_PE)
            {
                p->icount.parity++;
            }
            else if (lsr & UART_LSR_FE)
            {
                p->icount.frame++;
            }
            else if (lsr & UART_LSR_OE)
            {
                p->icount.overrun++;
            }

            /*
             * Mask off conditions which should be ingored.
             */
            lsr &= p->read_status_mask;

            if (lsr & UART_LSR_BI) {
                UART_DBG("handling break....\n");
                flag = TTY_BREAK;
            }
            else if (lsr & UART_LSR_PE)
            {
                flag = TTY_PARITY;
            }
            else if (lsr & UART_LSR_FE)
            {
                flag = TTY_FRAME;
            }
        }
        if (silent_state==0)
        {
            #ifdef SUPPORT_SYSRQ
            if (uart_handle_sysrq_char(p, ch))
            {
                goto IGNORE_CHAR;
            }
            #endif
            uart_insert_char(p, lsr, UART_LSR_OE, ch, flag);
        }
        if (isConsole)
        {
            //when receive '11111', disable UART RX to use TV tool
            if(ch == '1')
                rx_disable++;
            else
                rx_disable=0;

            if(rx_disable == 5)
            {
                silent_state = 1 - silent_state;

                if (silent_state)
                {
                    printk("disable uart\n");
                    ch = 0;
                }
                else
                {
                    printk("enable uart\n");
                }

                //CLRREG16(0x1F001C24, 0x1<<11);
                rx_disable=0;
            }
            //when receive '22222', disable UART PAD to use TV tool
            if(ch == '2')
                pad_disable++;
            else
                pad_disable=0;

            if(pad_disable == 5)
            {
#if defined(CONFIG_ARCH_INFINITY2)
                                CLRREG16(0x1F001C24, 0x1<<11);
#else
                CLRREG16(0x1F203D4C, 0x000F);
#endif
                        pad_disable=0;
            }
        }

IGNORE_CHAR:
        lsr = INREG8(REG_LSR(p));
    }while((max_count-- >0)&&(lsr & UART_LSR_DR));

    spin_unlock_irqrestore(&p->lock, flags);
    tty_flip_buffer_push(&p->state->port);
}

static irqreturn_t ms_uart_interrupt(s32 irq, void *dev_id)
{
    /* Define Local Variables */
    u8  iir_fcr = 0;    /* Interrupt Identification Register (IIR) */
    struct uart_port *p = dev_id;
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;
    u8 count=0, retry=100;
    local_fiq_disable();
    if(mp->use_dma)
    {
        u8 status = URDMA_GetInterruptStatus(p);
        if(status & URDMA_INTR_STATUS_RX)
        {
            u8 intr_type = URDMA_RxGetInterrupt(p);

            if(intr_type & URDMA_RX_INTR_TYPE_TIMEOUT)
            {
                URDMA_RxSetupTimeoutInterrupt(p,FALSE);
            }

            if(intr_type & URDMA_RX_INTR_TYPE_THRESHOLD)
            {
                URDMA_RxSetupThresholdInterrupt(p,FALSE);
            }
            URDMA_RxClearInterrupt(p);

            URDMA_StartRx(p);
            URDMA_RxSetupTimeoutInterrupt(p,TRUE);
            URDMA_RxSetupThresholdInterrupt(p,TRUE);
        }
        else if(status & URDMA_INTR_STATUS_TX)
        {
#if CONSOLE_DMA
            URDMA_TxClearInterrupt(p);
            urdma_conditions = 1;
            wake_up_interruptible(&urdma_wait);
#else
            URDMA_TxClearInterrupt(p);
            //do nothing
#endif
        }
        else
            UART_ERR("URDMA dummy interrupt!\n");
    }
    else
    {
        /* Read Interrupt Identification Register */
        iir_fcr = INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK;

        if( (iir_fcr == UART_IIR_RDI || iir_fcr == UART_IIR_RX_TIMEOUT) ) /* Receive Data Available or Character timeout */
        {
            ms_getchar(p);
        }
        else if( iir_fcr == UART_IIR_THRI ) /* Transmitter Holding Register Empty */
        {
    #if UART_TX_TASK
        #if UART_USE_SPINLOCK
            unsigned long flags=0;
            spin_lock_irqsave(&p->lock, flags);
            CLRREG8(REG_DLH_IER(p), UART_IER_THRI);
            spin_unlock_irqrestore(&p->lock, flags);
        #else
            CLRREG8(REG_DLH_IER(p), UART_IER_THRI);
        #endif

            tasklet_schedule(&mp->xmit_tasklet);
    #else

            if (silent_state==0)
                ms_putchar(p);
    #endif
        }
        else if( iir_fcr == UART_IIR_MSI ) /* Modem Status */
        {
            // UART_ERR("UART Interrupt: Modem status\n");
            // Read MSR to clear
            INREG8(REG_MSR(p));
        }
        else if( iir_fcr == UART_IIR_BUSY ) /* Busy detect indication */
        {
            // Read USR to clear
            INREG8(REG_USR(p));

            while( ((INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK) == UART_IIR_BUSY) && (count < retry))
            {
                // Read USR to clear
                INREG8(REG_USR(p));
                count++;
            }
            if (count == retry)
                UART_ERR("UART Interrupt: UART_IIR_BUSY\n");

        }
        else if( iir_fcr == UART_IIR_RLSI ) /* Receiver line status */
        {
            // Read LSR to clear
            INREG8(REG_LSR(p));
        }
        else if( iir_fcr == UART_IIR_NO_INT ) /* No pending interrupts */
        {
            while( ((INREG8(REG_USR(p)) & UART_USR_BUSY) == UART_USR_BUSY) && (count < retry))
            {
                count++;
            }
//            if (count == retry)
//                UART_ERR("UART%d Interrupt: No IRQ rasied by UART, but come in to UART ISR. IIR:0x%02X USR:0x%02X\n", p->line, iir_fcr, INREG8(REG_USR(p)));
        }
        else /* Unknown Status */
        {
            UART_ERR("UART Unknown Interrupt, IIR:0x%02X\n", iir_fcr);
        }
    }
        local_fiq_enable();
    return IRQ_HANDLED;
}

u32 gu32_console_bug_thre_hits = 0;
module_param(gu32_console_bug_thre_hits, uint, S_IRUGO);

static void serial8250_backup_timeout(unsigned long data)
{
    struct ms_uart_port *up = (struct ms_uart_port *)data;
    u16 iir, ier = 0, lsr;
    unsigned long flags;

    spin_lock_irqsave(&up->port.lock, flags);

    iir = INREG8(REG_IIR_FCR((&up->port)));
    ier = INREG8(REG_DLH_IER((&up->port)));

    /*
     * This should be a safe test for anyone who doesn't trust the
     * IIR bits on their UART, but it's specifically designed for
     * the "Diva" UART used on the management processor on many HP
     * ia64 and parisc boxes.
     */
    lsr = INREG8(REG_LSR((&up->port)));;
    if ((iir & UART_IIR_NO_INT) && (ier & UART_IER_THRI) &&
            (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
            (lsr & UART_LSR_THRE)) {
        CLRREG8(REG_DLH_IER((&up->port)), UART_IER_THRI);
        SETREG8(REG_DLH_IER((&up->port)), UART_IER_THRI);
        gu32_console_bug_thre_hits++;
        ms_putchar((&up->port));
    }

    spin_unlock_irqrestore(&up->port.lock, flags);

    /* Standard timer interval plus 0.2s to keep the port running */
    mod_timer(&up->timer,
            jiffies + uart_poll_timeout(&up->port) + HZ / 5);
}

static s32 ms_uart_startup(struct uart_port *p)
{
    /* Define Local Variables */
    int rc = 0;
    struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data;

    ms_force_rx_disable(mp->padmux, DISABLE);
    ms_uart_clear_fifos(p);

    /*we do not support CTS now*/
    p->flags &= ~ASYNC_CTS_FLOW;

#if UART_TX_TASK
    tasklet_init(&mp->xmit_tasklet, ms_do_xmit_task, (unsigned long)p);
#endif

    if(mp->use_dma)
    {
        rc = request_irq(mp->urdma->urdma_irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial_dma",p);
    }
    else
    {
        OUTREG8(REG_DLH_IER(p), 0);
        INREG8(REG_LSR(p));
        INREG8(REG_DLL_THR_RBR(p));
        INREG8(REG_IIR_FCR(p));
        INREG8(REG_MSR(p));
        rc = request_irq(p->irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial", p);
    }

    /* Print UART interrupt request status */
    if (rc) {
        /* UART interrupt request failed */
        //UART_ERR("ms_startup(): UART%d request_irq()is failed. return code=%d\n", p->line, rc);
    } else {
        /* UART interrupt request passed */
        //UART_ERR("ms_startup(): UART%d request_irq() is passed.\n", p->line);
    }

    mp->rx_guard=0;


    if(mp->use_dma)
    {
#if CONSOLE_DMA
        unsigned char bConsole = (mp->port.membase == console_port.port.membase) ? 1 : 0;

        if (bConsole)
        {
            console_lock();
        }
#endif
        URDMA_Reset(p);
        URDMA_Activate(p,TRUE);
        URDMA_TxInit(p);
        URDMA_TxEnable(p,TRUE);
        URDMA_RxInit(p);
        URDMA_RxSetupTimeoutInterrupt(p,TRUE);
        URDMA_RxSetupThresholdInterrupt(p,TRUE);
        URDMA_RxEnable(p,TRUE);
#if CONSOLE_DMA
        if (bConsole)
        {
            console_port.use_dma = 1;
            console_unlock();
        }
#endif
    }
    else
    {
#if UART_USE_SPINLOCK
        unsigned long flags;
        spin_lock_irqsave(&p->lock, flags);
        SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI);
        spin_unlock_irqrestore(&p->lock, flags);
#else
        SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI);
#endif
    }

    ms_force_rx_disable(mp->padmux, ENABLE);
#ifndef CONFIG_MS_SUPPORT_EXT_PADMUX
    ms_select_pad(p, mp->padmux, mp->pad_mode);
#endif
#if MS_UART_8250_BUG_THRE
    mp->bugs = UART_BUG_THRE;
#endif
    /*
     * [PATCH] from drivers/tty/serial/8250/8250_core.c
     * The above check will only give an accurate result the first time
     * the port is opened so this value needs to be preserved.
     */
    if (mp->bugs & UART_BUG_THRE) {
        UART_ERR("ms_startup(): enable UART_BUG_THRE\n");
        init_timer(&mp->timer);
        mp->timer.function = serial8250_backup_timeout;
        mp->timer.data = (unsigned long)mp;
        mod_timer(&mp->timer, jiffies +
                uart_poll_timeout(&mp->port) + HZ / 5);
    }
    return rc;
}


static void ms_uart_shutdown(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;
    if(p->rs485.flags&SER_RS485_ENABLED)//deinit
    {
        p->rs485.flags &= ~SER_RS485_ENABLED;
        ms_uart_rs485_config(p, &p->rs485);
    }
    if(mp->use_dma)
    {
        URDMA_RxEnable(p,FALSE);
        URDMA_TxEnable(p,FALSE);
        URDMA_TxSetupTimeoutInterrupt(p,FALSE);
        URDMA_TxClearInterrupt(p);
        URDMA_RxSetupTimeoutInterrupt(p,FALSE);
        URDMA_RxSetupThresholdInterrupt(p,FALSE);
        URDMA_RxClearInterrupt(p);
        URDMA_Activate(p,FALSE);
        disable_irq(mp->urdma->urdma_irq);
        free_irq(mp->urdma->urdma_irq, p);
    }
    else
    {
#if UART_USE_LOOPBACK
        //set loopback mode
        SETREG8(REG_MCR(p), 0x10);
#endif
        CLRREG8(REG_LCR(p), UART_LCR_SBC);
        ms_uart_clear_fifos(p);
        INREG8(REG_DLL_THR_RBR(p));

#if UART_USE_LOOPBACK
        //clear loopback mode
        CLRREG8(REG_MCR(p), 0x10);
#endif
        //OUTREG8(REG_DLH_IER(p), 0);
        disable_irq(p->irq);
        free_irq(p->irq, p);
    }

    if (mp->bugs & UART_BUG_THRE) {
        del_timer_sync(&mp->timer);
    }

    ms_force_rx_disable(mp->padmux, DISABLE);
}

static void ms_uart_set_termios(struct uart_port *p, struct ktermios *pTermios_st, struct ktermios *pOld_st)
{
    /* Define Local Variables */
    struct ms_uart_port *mp = NULL;
    u8 uartflag = 0;
    u16 divisor = 0;
    u32 baudrate = 0;
    u32 sctp_enable = 0;

    //OUTREG8(REG_DLH_IER(p), 0);

    if(p->dev)
    {
        mp=(struct ms_uart_port*)p->dev->driver_data;
        if(mp->use_dma)
            URDMA_Activate(p,FALSE);
        ms_force_rx_disable(mp->padmux, DISABLE);
    }

    /*------- Configure Chararacter Size --------*/
    switch (pTermios_st->c_cflag & CSIZE)
    {
        case CS5: /* Word length is 5 bits */
            uartflag |= UART_LCR_WLEN5;
            break;
        case CS6: /* Word length is 6 bits */
            uartflag |= UART_LCR_WLEN6;
            break;
        case CS7: /* Word length is 7 bits */
            uartflag |= UART_LCR_WLEN7;
            break;
        case CS8: /* Word length is 8 bits */
            uartflag |= UART_LCR_WLEN8;
            break;
        default:
            UART_ERR("%s unsupported bits:%d\n", __FUNCTION__, pTermios_st->c_cflag & CSIZE);
            break;
    }

    /*------------ Configure Stop bit -----------*/
    if (pTermios_st->c_cflag & CSTOPB)
    {
        /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */
        uartflag |= UART_LCR_STOP2;
    }
    else
    {
        /* Stop length is 1 bit */
        uartflag |= UART_LCR_STOP1;
    }

    /*----------- Configure Parity --------------*/
    if (pTermios_st->c_cflag & PARENB)
    {
        /* Parity Enable */
        uartflag |= UART_LCR_PARITY_EN;

        /* Set Odd/Even Parity */
        if (pTermios_st->c_cflag & PARODD)
        {
            /* Odd Parity */
            uartflag &= (~UART_LCR_PARITY_SEL);
        }
        else
        {
            /* Even Parity */
            uartflag |= UART_LCR_PARITY_SEL;
        }
    }
    else
    {
        /* Parity Disable */
        uartflag &= (~UART_LCR_PARITY_EN);
    }
    OUTREG8(REG_LCR(p), uartflag);

    //NOTE: we are going to set LCR, be carefully here
    baudrate = uart_get_baud_rate(p, pTermios_st, pOld_st, 0, 115200 * 14);
    divisor = ms_uart_set_clk(p, baudrate);
    if(divisor)
        ms_uart_set_divisor(p, divisor);

    OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L0 | UART_FCR_TRIGGER_RX_L0);
    INREG8(REG_DLL_THR_RBR(p));

    if(p->dev != NULL){
        of_property_read_u32(p->dev->of_node, "sctp_enable", &sctp_enable);
        if(sctp_enable == 1)
        {
            if(pTermios_st->c_cflag & CRTSCTS)
            {
                //rts cts enable
                OUTREG8(REG_MCR(p), UART_MCR_AFCE | UART_MCR_RTS);
                OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L0 | UART_FCR_TRIGGER_RX_L3);
            }
            else
            {
                //rts cts disable
                OUTREG8(REG_MCR(p), INREG8(REG_MCR(p)) & ~ (UART_LCR_DLAB| UART_MCR_RTS ) );
            }
        }
    }

    if(p->dev)
    {
        if(mp->use_dma)
        {
            URDMA_Reset(p);
            URDMA_Activate(p,TRUE);
            URDMA_TxInit(p);
            URDMA_TxEnable(p,TRUE);
            URDMA_RxInit(p);
            URDMA_RxSetupTimeoutInterrupt(p,TRUE);
            URDMA_RxSetupThresholdInterrupt(p,TRUE);
            URDMA_RxEnable(p,TRUE);
        }
        ms_force_rx_disable(mp->padmux, ENABLE);
    }
}

#ifdef CONFIG_PM
static s32 ms_uart_suspend(struct platform_device *pdev, pm_message_t state)
{
    struct ms_uart_port *mp=platform_get_drvdata(pdev);
    struct uart_port *p=&mp->port;

    UART_DBG("[%s] uart%d\n", __func__, p->line);

    if(mp->use_dma)
    {
        URDMA_RxEnable(p,FALSE);
        URDMA_TxEnable(p,FALSE);
        URDMA_TxSetupTimeoutInterrupt(p,FALSE);
        URDMA_TxClearInterrupt(p);
        URDMA_RxSetupTimeoutInterrupt(p,FALSE);
        URDMA_RxSetupThresholdInterrupt(p,FALSE);
        URDMA_RxClearInterrupt(p);
        URDMA_Activate(p,FALSE);
    }

    uart_suspend_port(&ms_uart_driver, p);

    mp->backupIER = INREG8(REG_DLH_IER(p));
    mp->backupLCR = INREG8(REG_LCR(p));
    mp->backupMCR = INREG8(REG_MCR(p));

    OUTREG8(REG_DLH_IER(p), 0);
    ms_uart_clear_fifos(p);

    OUTREG8(REG_LCR(p) , mp->backupLCR | UART_LCR_DLAB);

    mp->backupDivisor = (INREG8(REG_DLH_IER(p)) << 8);
    mp->backupDivisor |= (INREG8(REG_DLL_THR_RBR(p)) & 0xFF);

    if (!IS_ERR(mp->clk))
    {
        clk_disable_unprepare(mp->clk);
#if 0
        clk_put(mp->clk);
#endif
    }

    return 0;
}

static s32 ms_uart_resume(struct platform_device *pdev)
{
    struct ms_uart_port *mp=platform_get_drvdata(pdev);
    struct uart_port *p=&mp->port;

    if (!IS_ERR(mp->clk))
        clk_prepare_enable(mp->clk);

    ms_uart_set_divisor(p, mp->backupDivisor);

    OUTREG8(REG_MCR(p), mp->backupMCR);
    OUTREG8(REG_LCR(p), mp->backupLCR);
    OUTREG8(REG_DLH_IER(p), mp->backupIER);

    if(mp->use_dma)
    {
        URDMA_Reset(p);
        URDMA_Activate(p,TRUE);
        URDMA_TxInit(p);
        URDMA_TxEnable(p,TRUE);
        URDMA_RxInit(p);
        URDMA_RxSetupTimeoutInterrupt(p,TRUE);
        URDMA_RxSetupThresholdInterrupt(p,TRUE);
        URDMA_RxEnable(p,TRUE);
    }

    uart_resume_port(&ms_uart_driver, &mp->port);

    UART_DBG("[%s] uart%d\n", __func__, p->line);

    return 0;
}
#endif

static s32 ms_uart_remove(struct platform_device *pdev)
{
    struct ms_uart_port *mp=platform_get_drvdata(pdev);

    uart_remove_one_port(&ms_uart_driver,&mp->port);

    if(mp->use_dma)
    {
        dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH), &mp->urdma->rx_urdma_base, GFP_KERNEL);
        dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH), &mp->urdma->tx_urdma_base, GFP_KERNEL);
        CamOsThreadStop(mp->urdma_task);
    }

    if (!IS_ERR(mp->clk))
    {
        clk_disable_unprepare(mp->clk);
        clk_put(mp->clk);
    }

    return 0;
}

static s32 ms_uart_probe(struct platform_device *pdev)
{
    int ret = 0;
    struct ms_uart_port *mp;
    struct ms_urdma *urdma;
    struct resource *res;
    int tx_pad;
    CamOsThreadAttrb_t tAttr = {0};
    if(!pdev)
    {
        // UART_ERR("ms_uart_probe() parameter pdev is NULL\n");
        return -ENOMEM;
    }
    mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
    if (!mp)
        return -ENOMEM;

    spin_lock_init(&mp->port.lock);

    mp->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
   /*if (mp->port.line < 0) {
        UART_ERR("[%s] failed to get alias/pdev id = %d\n", __func__, mp->port.line);
        return -EINVAL;
    }*/
    pdev->id=mp->port.line;

    mp->clk = of_clk_get(pdev->dev.of_node, 0);
    if(IS_ERR(mp->clk))
    {
         //UART_ERR("[%s] of_clk_get failed\n", __func__);
        return -EINVAL;
    }
    //enable clk in probe, because if UART no clk, it can not be accessed.
    clk_prepare_enable(mp->clk);
    mp->port.uartclk = clk_get_rate(mp->clk);

    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    if (res == NULL) {
        // UART_ERR("no memory resource defined\n");
        ret = -ENODEV;
        goto out;
    }
    mp->port.membase = (void *)res->start;

    res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
    if (res == NULL) {
        // UART_ERR("no irq resource defined\n");
        ret = -ENODEV;
        goto out;
    }
    mp->port.irq = res->start;

    of_property_read_u32(pdev->dev.of_node, "dma", &mp->use_dma);

    if (mp->use_dma)
    {
#if CONSOLE_DMA
        unsigned char bConsole = (mp->port.membase == console_port.port.membase) ? 1 : 0;
        if (bConsole)
        {
            console_lock();
        }
#endif
        mp->urdma = devm_kzalloc(&pdev->dev, sizeof(*urdma), GFP_KERNEL);
        if (!mp->urdma)
        {
            mp->use_dma=0;
            goto dma_err;
        }

        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
        if (res == NULL)
        {
            mp->use_dma = 0;
            // UART_ERR("no urdma memory resource defined...\n");
            goto dma_err;
        }
        mp->urdma->reg_base = (reg_urdma *)IO_ADDRESS(res->start);

        res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
        if (res == NULL)
        {
            mp->use_dma = 0;
            // UART_ERR("no urdma irq resource defined\n");
            goto dma_err;
        }
        mp->urdma->urdma_irq = res->start;
        mp->port.irq = res->start;

        mp->urdma->rx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH),
                    &mp->urdma->rx_urdma_base, GFP_KERNEL);
        mp->urdma->tx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH),
                    &mp->urdma->tx_urdma_base, GFP_KERNEL);
        if(!mp->urdma->rx_buf || !mp->urdma->tx_buf)
        {
            mp->use_dma = 0;
            // UART_ERR("Allocate urdma rx_buffer/tx_buffer failed, use UART mode\n");
            goto dma_err;
        }
        mp->urdma->rx_urdma_size = PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH);
        mp->urdma->tx_urdma_size = PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH);
        UART_DBG("[%s] URDMA mode enable, reg_base=0x%08X, irq=%d\n", __func__, (unsigned int)(mp->urdma->reg_base), mp->urdma->urdma_irq);
        // UART_ERR("URDMA rx_buf=0x%08X(phy:0x%08X) tx_buf=0x%08X(phy:0x%08X) size=0x%X\n", (unsigned int)mp->urdma->rx_buf, (unsigned int)mp->urdma->rx_urdma_base, (unsigned int)mp->urdma->tx_buf, (unsigned int)mp->urdma->tx_urdma_base, mp->urdma->rx_urdma_size);
#if CONSOLE_DMA
dma_err:
        if (bConsole)
        {
            // console_port.use_dma = mp->use_dma;
            if ((!mp->use_dma) && (mp->urdma))
            {
                devm_kfree(&pdev->dev, mp->urdma);
                mp->urdma = NULL;
            }
            console_port.urdma= mp->urdma;
            console_unlock();
        }
#endif
        tAttr.nPriority = 50;
        tAttr.nStackSize = 0;
        tAttr.szName = "urdma_tx_thread";
        CamOsThreadCreate(&mp->urdma_task, &tAttr, (void *)urdma_tx_thread, (void *)&mp->port);
    }
#if !CONSOLE_DMA
dma_err:
#endif
    mp->port.type = PORT_8250;
    mp->port.dev = &pdev->dev;
    mp->port.ops=&ms_uart_ops;
    mp->port.regshift = 0;
    mp->port.fifosize = 16;
    mp->port.timeout  =HZ;
    mp->port.iotype=UPIO_MEM;
    mp->port.rs485_config = ms_uart_rs485_config;
    UART_DBG("[%s] line=%d name=%s\n", __func__, mp->port.line, pdev->name);

    //[2016.11.15] Add padmux select from DTB by Spade
    if(of_property_read_u32(pdev->dev.of_node, "pad", &tx_pad))  //read property failed
    {
        //set default pad
        if(mp->port.line==0)
        {
            // improve boot-up speed, remove print log
            UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_PM_UART");
            //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_PM_UART");
            mp->padmux=MUX_PM_UART;
        }
        else if(mp->port.line==1)
        {
            // improve boot-up speed, remove print log
            UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART1");
            //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART1");
            mp->padmux=MUX_UART1;
        }
        else if(mp->port.line==2)
        {
            // improve boot-up speed, remove print log
            UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_FUART");
            //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_FUART");
            mp->padmux=MUX_FUART;
        }
#ifdef CONFIG_MS_SUPPORT_UART2
        else if(mp->port.line==3)
        {
            // improve boot-up speed, remove print log
            UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART2");
            //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART2");
            mp->padmux=MUX_UART2;
        }
#endif
        else
        {
            // improve boot-up speed, remove print log
            UART_DBG("[%s] port line %d is not supported\n", __func__, mp->port.line);
            //UART_ERR("[%s] port line %d is not supported\n", __func__, mp->port.line);
            ret = -EINVAL;
            goto out;
        }
    }
    else  //read property successfully
    {
        if (ms_uart_get_padmux(tx_pad, &(mp->padmux), &(mp->pad_mode)) != 0)
        {
            // UART_ERR("[%s] Use undefined pad number %d\n", __func__, tx_pad);
            ret = -EINVAL;
            goto out;
        }

        // improve boot-up speed, remove print log
#ifdef CONFIG_MS_SUPPORT_UART2
        UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":(mp->padmux==MUX_UART1)?"MUX_UART1":"MUX_UART2");
        //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":(mp->padmux==MUX_UART1)?"MUX_UART1":"MUX_UART2");
#else
        UART_DBG("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":"MUX_UART1");
        //UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":"MUX_UART1");
#endif
    }

    platform_set_drvdata(pdev, mp);

    ret = uart_add_one_port(&ms_uart_driver, &mp->port);
    if (ret != 0)
        goto out;

    return 0;
out:
    // UART_ERR("[UART%d]: failure [%s]: %d\n", mp->port.line, __func__, ret);
    clk_disable_unprepare(mp->clk);
    clk_put(mp->clk);
    if(mp->use_dma)
    {
        CamOsThreadStop(mp->urdma_task);
    }
    return ret;
}

static const struct of_device_id ms_uart_of_match_table[] = {
    { .compatible = "sstar,uart" },
    {}
};
MODULE_DEVICE_TABLE(of, ms_uart_of_match_table);

static struct platform_driver ms_uart_platform_driver = {
    .remove = ms_uart_remove,
    .probe = ms_uart_probe,
#ifdef CONFIG_PM
    .suspend = ms_uart_suspend,
    .resume = ms_uart_resume,
#endif
    .driver = {
        .name = "ms_uart",
        .owner = THIS_MODULE,
        .of_match_table = of_match_ptr(ms_uart_of_match_table),
    },
};

static s32 __init ms_uart_module_init(void)
{
    int ret;

    ret = uart_register_driver(&ms_uart_driver);
    if (ret != 0)
        return ret;
    ret = platform_driver_register(&ms_uart_platform_driver);
    if (ret != 0)
    {
        // UART_ERR("[ms_uart]platform_driver_register failed!!\n");
        uart_unregister_driver(&ms_uart_driver);
    }
    return ret;
}


static void __exit ms_uart_module_exit(void)
{
    platform_driver_unregister(&ms_uart_platform_driver);
    uart_unregister_driver(&ms_uart_driver);
}

module_init(ms_uart_module_init);
module_exit(ms_uart_module_exit);


static int __init ms_early_console_init(void)
{
#if !CONSOLE_DMA
    struct device_node *console_np;
    struct resource res;

    console_np=of_find_node_by_path("console");
    if(!console_np)
        return -ENODEV;


    BUG_ON( of_address_to_resource(console_np,0,&res) );

    console_port.port.membase = (void *)res.start;

    console_port.port.type = PORT_8250;

    console_port.port.ops=&ms_uart_ops;
    console_port.port.regshift = 0;
    console_port.port.fifosize = 16;
    console_port.port.line=0;
    console_port.port.cons=&ms_uart_console;
    ms_uart_add_console_port(&console_port);
#endif
    register_console(&ms_uart_console);
    return 0;
}

console_initcall(ms_early_console_init);

void URDMA_Reset(struct uart_port *p)
{
    unsigned int i=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->urdma_mode=1;

    mp->urdma->reg_base->tx_urdma_en = 0;
    mp->urdma->reg_base->rx_urdma_en = 0;

    mp->urdma->reg_base->tx_intr_en = 0;
    mp->urdma->reg_base->rx_intr1_en = 0;
    mp->urdma->reg_base->rx_intr2_en = 0;

    /* clear interrupt status */
    mp->urdma->reg_base->tx_intr_clr = 1;
    mp->urdma->reg_base->rx_intr_clr = 1;


    /* software reset */
    mp->urdma->reg_base->sw_rst = 1;

    /* make sure rx_busy is off */
    for(i=0; (mp->urdma->reg_base->rx_busy || mp->urdma->reg_base->tx_busy); i++)
    {
        if(0xFFFF == i)
        {
            break;
        }
    }

#if !CONSOLE_DMA
    mdelay(10);
#endif
    mp->urdma->reg_base->sw_rst = 0;

    mp->urdma->reg_base->urdma_mode=0;
}

void URDMA_Activate(struct uart_port *p,BOOL bEnable)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->urdma_mode=bEnable?TRUE:FALSE;
    UART_DBG("URDMA_Activate: %d\n", bEnable);

}

void URDMA_TxEnable(struct uart_port *p,BOOL bEnable)
{
    unsigned int i=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    if(bEnable)
    {
        mp->urdma->reg_base->tx_urdma_en = 1;
    }
    else
    {
        mp->urdma->reg_base->tx_urdma_en = 0;
        for(i=0; (mp->urdma->reg_base->tx_busy); i++)
        {
            if(0xFFFF == i)
            {
                return;
            }
        }
    }
}

void URDMA_RxEnable(struct uart_port *p,BOOL bEnable)
{
    unsigned int i=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    if(bEnable)
    {
        mp->urdma->reg_base->rx_urdma_en = 1;
    }
    else
    {
        mp->urdma->reg_base->rx_urdma_en = 0;
        for(i=0; (mp->urdma->reg_base->rx_busy); i++)
        {
            if(0xFFFF == i)
            {
                return;
            }
        }
    }
}

U8 URDMA_GetInterruptStatus(struct uart_port *p)
{
    U8 stat=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    if(mp->urdma->reg_base->rx_mcu_intr)
    {
        stat|=URDMA_INTR_STATUS_RX;
    }

    if(mp->urdma->reg_base->tx_mcu_intr)
    {
        stat|=URDMA_INTR_STATUS_TX;
    }

    return stat;
}

void URDMA_TxInit(struct uart_port *p)
{
    unsigned int i=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->tx_urdma_en = 0; /* disable dma */
    mp->urdma->reg_base->tx_sw_rst = 1;
    for(i=0; (mp->urdma->reg_base->tx_busy); i++)
    {
        if(0xFFFF == i)
        {
            return;
        }
    }

    mp->urdma->reg_base->tx_sw_rst = 0;
    mp->urdma->reg_base->tx_buf_base_h = URDMA_HIU16((U32)mp->urdma->tx_urdma_base);
    mp->urdma->reg_base->tx_buf_base_l = URDMA_LOU16((U32)mp->urdma->tx_urdma_base);
    mp->urdma->reg_base->tx_buf_size = (mp->urdma->tx_urdma_size/8);
    mp->urdma->reg_base->tx_timeout = URDMA_TX_TIMEOUT;
    mp->urdma->reg_base->tx_buf_wptr = 0x0;

    //2015.10.21 Refine: initialize tx_buf_wptr to 1 because HW behavior is not correct from 0 to 1
    //2016.11.27 Refine: remove initial value for tx_buf_wptr
    //mp->urdma->reg_base->tx_buf_wptr = 0x1;
}

void URDMA_RxInit(struct uart_port *p)
{
    unsigned int i=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->rx_urdma_en = 0; /* disable dma */
    mp->urdma->reg_base->rx_sw_rst = 1;
    for(i=0; (mp->urdma->reg_base->rx_busy); i++)
    {
        if(0xFFFF == i)
        {
            return;
        }
    }

    mp->urdma->reg_base->rx_sw_rst=0;
    mp->urdma->reg_base->rx_buf_base_h = URDMA_HIU16((U32)mp->urdma->rx_urdma_base);
    mp->urdma->reg_base->rx_buf_base_l = URDMA_LOU16((U32)mp->urdma->rx_urdma_base);
    mp->urdma->reg_base->rx_buf_size = (mp->urdma->rx_urdma_size/8);
    mp->urdma->reg_base->intr_threshold = URDMA_RX_INTR_LEVEL;
    mp->urdma->reg_base->rx_timeout = URDMA_RX_TIMEOUT; /* receive timeout. */

    //need to clear buffer?
    //memset(dma_rx_buf[fuartNum].Buffer,0,dma_rx_buf[fuartNum].Length);

    //2016.11.27 Refine: sw_rx_rptr is the index of rx_buf we have read
    //Give initial value (size-1) according to HW behavior
    mp->urdma->sw_rx_rptr = mp->urdma->rx_urdma_size - 1;
}

void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->tx_intr_en = bEnable?1:0;
}

void URDMA_TxClearInterrupt(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->tx_intr_clr = 1; /* clear int status */
}

void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->rx_intr1_en=bEnableTimeout?1:0;
}

void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->rx_intr2_en=bEnableThreshold?1:0;
}

U8 URDMA_RxGetInterrupt(struct uart_port *p)
{
    U8 intr=0;
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    if(mp->urdma->reg_base->rx_intr1)
    {
        intr |= URDMA_RX_INTR_TYPE_TIMEOUT;
    }

    if(mp->urdma->reg_base->rx_intr2)
    {
        intr |= URDMA_RX_INTR_TYPE_THRESHOLD;
    }

    return intr;
}

void URDMA_RxClearInterrupt(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    mp->urdma->reg_base->rx_intr_clr = 1; /* clear int status */
}

/*
U32 URDMA_GetWritableSize(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;

    return (U32)((mp->urdma->reg_base->tx_buf_rptr - mp->urdma->reg_base->tx_buf_wptr - 1) & (mp->urdma->rx_urdma_size - 1));
}
*/

#if CONSOLE_DMA
static void *urdma_tx_thread(void *arg)
{
    struct uart_port *p = (struct uart_port *)arg;
    struct circ_buf *xmit;
    while(1){
        wait_event_interruptible(urdma_wait, urdma_conditions);
        urdma_conditions = 0;
        xmit = &p->state->xmit;
        if (uart_circ_empty(xmit) || uart_tx_stopped(p))
        {
            ms_uart_stop_tx(p);
        }

        if (uart_circ_chars_pending(xmit))
       {
            URDMA_StartTx(p);
       }else
       {
            uart_write_wakeup(p);
       }
        if (CAM_OS_OK == CamOsThreadShouldStop())
                break;
    }
    return 0;
}

static int _urdma_tx(struct ms_uart_port *mp, unsigned char* buf, int buf_size)
{
    int complete_size = 0;
    int size_cp;
    U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr;
    U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr;
    unsigned long flags1;

    spin_lock_irqsave(&mutex_console_2_dma, flags1);
    if(mp->urdma->reg_base->tx_buf_wptr == 0 && mp->urdma->reg_base->tx_buf_rptr == 0){
        sw_tx_wptr = (sw_tx_wptr) & UR2DMA_TX_BUF_MASK;
    }
    else
    {
        sw_tx_wptr = (sw_tx_wptr +1) & UR2DMA_TX_BUF_MASK;
    }
    if (sw_tx_wptr >= sw_tx_rptr)
    {
        size_cp = min_t(int, (mp->urdma->tx_urdma_size - sw_tx_wptr), buf_size);
        if (size_cp)
        {
            memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), buf, size_cp);
            buf += size_cp;
            buf_size -= size_cp;
            complete_size += size_cp;
            sw_tx_wptr = (sw_tx_wptr + size_cp) & UR2DMA_TX_BUF_MASK;
        }
    }
    if (buf_size)
    {
        size_cp = min_t(int, (sw_tx_rptr - sw_tx_wptr), buf_size);
        if (size_cp)
        {
            memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), buf, size_cp);
            complete_size += size_cp;
        }
    }
    if (complete_size)
    {
        Chip_Flush_MIU_Pipe();
        if(mp->urdma->reg_base->tx_buf_wptr == 0 && mp->urdma->reg_base->tx_buf_rptr == 0)
        {
            mp->urdma->reg_base->tx_buf_wptr = ((mp->urdma->reg_base->tx_buf_wptr + complete_size -1 ) & UR2DMA_TX_BUF_MASK);
        }
        else
        {
            mp->urdma->reg_base->tx_buf_wptr = ((mp->urdma->reg_base->tx_buf_wptr + complete_size) & UR2DMA_TX_BUF_MASK);
        }
    }
    spin_unlock_irqrestore(&mutex_console_2_dma, flags1);
    return complete_size;
}

void URDMA_StartTx(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;
    struct circ_buf *xmit = &p->state->xmit;
    U16 circ_buf_out_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
    int complete_size = 0;
    U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr;
    U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr;
    int space = (sw_tx_rptr > sw_tx_wptr) ? (sw_tx_rptr - sw_tx_wptr) : (mp->urdma->tx_urdma_size - sw_tx_wptr + sw_tx_rptr);

    if (circ_buf_out_size && (space > circ_buf_out_size))
    {
        complete_size = _urdma_tx(mp, &xmit->buf[xmit->tail], circ_buf_out_size);
        p->icount.tx += complete_size;
        xmit->tail = (xmit->tail + complete_size) & (UART_XMIT_SIZE - 1);
    }

    return;
}
#else // #if CONSOLE_DMA
void URDMA_StartTx(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;
    struct circ_buf *xmit = &p->state->xmit;
    U16 circ_buf_out_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
    U16 tx_buf_space, tx_end;

    /* tx_buf_wptr point to the byte have been written to buffer */
    /* tx_buf_rptr point to the byte have been sent */
    /* if tx_buf_rptr meets tx_buf_wptr, it means all written bytes in buffer have been sent */
    /* In this case, the space equal to buffer size */

    U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr;
    U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr;

    if(sw_tx_wptr == (mp->urdma->tx_urdma_size-1))  //wptr meet the end of buffer, start from (0), end at (rptr)
    {
        sw_tx_wptr = 0;
        tx_buf_space = sw_tx_rptr;
    }
    else if(sw_tx_wptr >= sw_tx_rptr)  //start from (wptr+1), end at (buffer_size-1)
    {
        sw_tx_wptr+=1;
        tx_buf_space = mp->urdma->tx_urdma_size - sw_tx_wptr;
    }
    else  //start from (wptr+1), end at (rptr)
    {
        sw_tx_wptr+=1;
        tx_buf_space = sw_tx_rptr - sw_tx_wptr;
    }

    //pr_debug("sw_wp=%4x, sw_rp=%4x, tx_space=%4x, circ_buf_out_size=%4x, head=%4x, tail=%4x\n", sw_tx_wptr, sw_tx_rptr, tx_space, circ_buf_out_size, xmit->head, xmit->tail);

    if(circ_buf_out_size > tx_buf_space)  //tx_cnt > tx_space
    {
        memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), &xmit->buf[xmit->tail], tx_buf_space);
        p->icount.tx += tx_buf_space;
        xmit->tail += tx_buf_space;
        circ_buf_out_size -= tx_buf_space;

        //now we can start write from (0), end at (min[sw_tx_rptr,circ_buf_out_size])
        tx_end = circ_buf_out_size >= sw_tx_rptr ? sw_tx_rptr : circ_buf_out_size;
        memcpy((void *)(&mp->urdma->tx_buf[0]), &xmit->buf[xmit->tail], tx_end);

        Chip_Flush_MIU_Pipe();

        p->icount.tx += tx_end;
        xmit->tail = (xmit->tail + tx_end) & (UART_XMIT_SIZE - 1);
        mp->urdma->reg_base->tx_buf_wptr = tx_end;
    }
    else  //tx_cnt <= tx_space
    {
        memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]),&xmit->buf[xmit->tail], circ_buf_out_size);

        Chip_Flush_MIU_Pipe();

        p->icount.tx += circ_buf_out_size;
        xmit->tail = (xmit->tail + circ_buf_out_size) & (UART_XMIT_SIZE - 1);
        //mp->urdma->reg_base->tx_buf_wptr += circ_buf_out_size;
        if(mp->urdma->reg_base->tx_buf_wptr == mp->urdma->tx_urdma_size-1)
            mp->urdma->reg_base->tx_buf_wptr = circ_buf_out_size -1;
        else
            mp->urdma->reg_base->tx_buf_wptr += circ_buf_out_size;
    }

    if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
        uart_write_wakeup(p);

    if (uart_circ_empty(xmit) || uart_tx_stopped(p))
    {
        ms_uart_stop_tx(p);
    }
    return;
}
#endif

void URDMA_StartRx(struct uart_port *p)
{
    struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data;
    U16 sw_rx_wptr = mp->urdma->reg_base->rx_buf_wptr;
    U16 sw_rx_rptr = mp->urdma->sw_rx_rptr;
    U16 in_size = (sw_rx_wptr - sw_rx_rptr) & (mp->urdma->rx_urdma_size - 1);  //read from (sw_rx_rptr+1), end at (sw_rx_wptr)
    U16 rptr_to_end = mp->urdma->rx_urdma_size - sw_rx_rptr - 1;

    /* sw_rx_wptr point to the byte already read from UART */
    /* sw_rx_rptr point to the byte have been read */
    /* if sw_rx_rptr equal to sw_rx_wptr, it means all bytes in buffer have been read */

    if(sw_rx_rptr==mp->urdma->rx_urdma_size - 1)  //initial case
    {
        tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end);
        p->icount.rx += in_size - rptr_to_end;
        //update global sw_rx_rptr
        mp->urdma->sw_rx_rptr = in_size - rptr_to_end -1;
        tty_flip_buffer_push(&p->state->port);
        pr_debug("(0) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size);
    }
    else if(in_size > rptr_to_end)
    {
        tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[sw_rx_rptr+1], rptr_to_end);
        tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end);
        p->icount.rx += in_size;
        //update global sw_rx_rptr
        mp->urdma->sw_rx_rptr = (in_size - rptr_to_end - 1);
        tty_flip_buffer_push(&p->state->port);
        pr_debug("(1) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size);
    }
    else
    {
        tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[(sw_rx_rptr+1)&(mp->urdma->rx_urdma_size-1)], in_size);
        p->icount.rx += in_size;
        //update global sw_rx_rptr
        mp->urdma->sw_rx_rptr += in_size & (mp->urdma->rx_urdma_size - 1);  //avoid sw_rx_rptr overflow
        tty_flip_buffer_push(&p->state->port);
        pr_debug("(2) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size);
    }
    return;
}

太好了, 配置完dts之后自带 RS485控制, 想当年全志的RS485驱动控制撸到吐血.

离线

#8 2021-02-16 16:31:46

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

解压 IDO-SSD20X\开发板\IDO-SBC2D07\images\202_256M\images_7open_202_256M.tar.bz2 (我这个板子芯片是江波龙的FS35ND02G 2Gb SPI NAND)

得到 SigmastarUpgrade.bin

拷贝到U盘,

插入到 启明云端7寸紫色开发板

重启会自动刷固件.


或者启动的时候, 进入串口终端按住回车键不放, 进入终端, 插入有SigmastarUpgrade.bin文件的U盘, 然后输入 usbstar 命令也可以自动刷固件

这是刷固件的log:

The system is going down NOW!
Sent SIGTERM to all processes
Terminated
Requesting system reboot
reboot: Restarting system
1
IPL g5da0ceb
D-1e
HW Reset
miupll_233MHz
MIU0 zq=0x003c
miu_bw_set
utmi_1_init done
utmi_2_init done
utmi_3_init done
usbpll init done......
cpupll init done
SPI 54M
clk_init done
P1 USB_rterm trim=0x0000
P1 USB_HS_TX_CURRENT trim=0x0001
P2 USB_rterm trim=0x0000
P2 USB_HS_TX_CURRENT trim=0x0001
P3 USB_rterm trim=0x0000
P3 USB_HS_TX_CURRENT trim=0x0001
PM_vol_bgap trim=0x0005
GCR_SAR_DATA trim=0x018f
ETH 10T output swing trim=0x0000
ETH 100T output swing trim=0x0010
ETH RX input impedance trim=0x0000
ETH TX output impedance trim=0x0001
MIPI_HS_RTERM trim=0x0001
MIPI_LP_RTERM trim=0x0000
128MB
BIST0_0001-OK
Enable MMU and CACHE
Load IPL_CUST from SPINAND
QUAD MODE ENABLE
Checksum OK

IPL_CUST g5da0ceb
runUBOOT()
runUBOOT()
[SPINAND]
SPI 54M
Load UBOOT from SPINAND
 -Verify UBOOT CRC32 passed!
 -Decompress UBOOT XZ
  decomp_size=0x000a12a4
Disable MMU and D-cache before jump to UBOOT▒

U-Boot 2015.01 (Dec 14 2020 - 17:22:37)

Version: I2g#######
       Watchdog enabled
I2C:   ready
DRAM:
WARNING: Caches not enabled
SPINAND: _MDrv_SPINAND_GET_INFO: Found SPINAND INFO
(0xCD) (0xEB) (0x11)
SPINAND: board_nand_init: CIS contains part info
256 MiB
MMC:   MStar SD/MMC: 0
In:    serial
Out:   serial
Err:   serial
Net:   MAC Address 00:30:1B:BA:02:DB
Auto-Negotiation...
Link Status Speed:10 Full-duplex:0
Status Error!
sstar_emac
bootcheck start
fore uup u8KeyPad_KeyVal [0xffff]
BootMode 0
Saving Environment to NAND...
Erasing NAND...
Erasing at 0x440000 -- 100% complete.
Writing to NAND... OK
UpgradeImage env is null,use default SigmastarUpgrade.bin
Saving Environment to NAND...
Erasing NAND...
Erasing at 0x440000 -- 100% complete.
Writing to NAND... OK
(Re)start USB 1...
Check USB port[1]:
[USB] usb_lowlevel_init++
[USB] USB EHCI LIB VER: 2018.01.12
[USB] Port 1 is Enabled
[USB] TV_usb_init (UTMI Init) ++
[USB] UTMI Base 1f284a00
[USB] UHC Base 1f285000
[USB] USBC Base 1f284e00
[USB] BC Base 1f284c00
[USB] config miu select [70] [f8] [ef] ][ef]
[USB] enable miu lower bound address subtraction
[USB] init squelch level 0x2
[USB] TV_usb_init--
[USB] Usb_host_Init++
[USB] Async base addr: 0x3f78b00
[USB] Reg 0x28: 0x8b00 0x3f7
[USB] disable run
[USB] Host Speed:2
[USB] enable aynch
[USB] Usb_host_Init--
[USB] usb_lowlevel_init--
scanning bus for devices...
[USB] interface[0] conf:1 value 8:
1 USB Device(s) found
       scanning usb for storage devices... [USB] no_of_ep: 2
[USB] find bulk ep: 0
[USB] find bulk ep2: 1

[USB] bulk max packet size: ep(in) 0x200, ep2(out) 0x200
[USB] bulk0 is in
max USB Storage Device reached: 1 stopping
1 Storage Device(s) found
reading SigmastarUpgrade.bin
16384 bytes read in 177 ms (89.8 KiB/s)
reading SigmastarUpgrade.bin
18432 bytes read in 31 ms (580.1 KiB/s)
reading SigmastarUpgrade.bin
512 bytes read in 24 ms (20.5 KiB/s)
SPINAND: _MDrv_SPINAND_GET_INFO: Found SPINAND INFO
(0xCD) (0xEB) (0x11)
SPINAND: MDrv_SPINAND_SearchCIS_in_DRAM: Search CIS in DRAM
SPINAND: MDrv_SPINAND_SearchCIS_in_DRAM: SNI v:1.0.6
SPINAND: MDrv_SPINAND_SearchCIS_in_DRAM: Found SNI in given memory
U-Boot BUG at drivers/mtd/mtdcore.c:843!
Removing MTD device #0 (nand0) with use count -1
SPINAND: _MDrv_SPINAND_GET_INFO: Found SPINAND INFO
(0xCD) (0xEB) (0x11)
SPINAND: board_nand_init: CIS contains part info
256 MiB
SPINAND: MDrv_SPINAND_GetMtdParts: Force Search mtdparts from PNI...

current partition deleted, resetting current to 0
Saving Environment to NAND...
Erasing NAND...
Erasing at 0x440000 -- 100% complete.
Writing to NAND... OK

NAND erase.part: device 0 offset 0xf20000, size 0xf0e0000
Erasing at 0xffe0000 -- 100% complete.
Time:4993843 us, speed:50577 KB/s
OK
UBI: parsing mtd_dev string 'mtd=11'
UBI: attaching mtd2 to ubi0
UBI: scanning is finished
UBI: empty MTD device detected
UBI: attached mtd2 (name "mtd=11", size 240 MiB) to ubi0
UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
UBI: good PEBs: 1927, bad PEBs: 0, corrupted PEBs: 0
UBI: user volume: 0, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 1/0, WL threshold: 4096, image sequence number: 0
UBI: available PEBs: 1883, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40
Creating dynamic volume rootfs of size 214958080
Creating dynamic volume miservice of size 10485760
Creating dynamic volume customer of size 5242880
Creating dynamic volume appconfigs of size 5242880
reading SigmastarUpgrade.bin
21920 bytes read in 31 ms (690.4 KiB/s)

NAND erase.part: device 0 offset 0x140000, size 0x60000
Erasing at 0x180000 -- 100% complete.
Time:16939 us, speed:23213 KB/s
OK

NAND write: device 0 offset 0x140000, size 0x55a0
Time:25641 us, speed:854 KB/s
 21920 bytes written: OK

NAND erase.part: device 0 offset 0x1a0000, size 0x60000
Erasing at 0x1e0000 -- 100% complete.
Time:16940 us, speed:23212 KB/s
OK

NAND write: device 0 offset 0x1a0000, size 0x55a0
Time:25505 us, speed:859 KB/s
 21920 bytes written: OK
reading SigmastarUpgrade.bin
20800 bytes read in 29 ms (700.2 KiB/s)

NAND erase.part: device 0 offset 0x200000, size 0x60000
Erasing at 0x240000 -- 100% complete.
Time:16942 us, speed:23209 KB/s
OK

NAND write: device 0 offset 0x200000, size 0x5140
Time:25527 us, speed:814 KB/s
 20800 bytes written: OK

NAND erase.part: device 0 offset 0x260000, size 0x60000
Erasing at 0x2a0000 -- 100% complete.
Time:16940 us, speed:23212 KB/s
OK

NAND write: device 0 offset 0x260000, size 0x5140
Time:25365 us, speed:820 KB/s
 20800 bytes written: OK
reading SigmastarUpgrade.bin
236184 bytes read in 52 ms (4.3 MiB/s)

NAND erase.part: device 0 offset 0x2c0000, size 0xc0000
Erasing at 0x360000 -- 100% complete.
Time:33819 us, speed:23254 KB/s
OK

NAND write: device 0 offset 0x2c0000, size 0x39a98
Time:87212 us, speed:2708 KB/s
 236184 bytes written: OK

NAND erase.part: device 0 offset 0x380000, size 0xc0000
Erasing at 0x420000 -- 100% complete.
Time:33818 us, speed:23254 KB/s
OK

NAND write: device 0 offset 0x380000, size 0x39a98
Time:87142 us, speed:2710 KB/s
 236184 bytes written: OK
reading SigmastarUpgrade.bin
57972 bytes read in 31 ms (1.8 MiB/s)

NAND erase.part: device 0 offset 0x4c0000, size 0x60000
Erasing at 0x500000 -- 100% complete.
Time:17005 us, speed:23123 KB/s
OK

NAND write: device 0 offset 0x4c0000, size 0xe274
Time:21925 us, speed:2644 KB/s
 57972 bytes written: OK
reading SigmastarUpgrade.bin
2437264 bytes read in 261 ms (8.9 MiB/s)

NAND erase.part: device 0 offset 0x520000, size 0x500000
Erasing at 0xa00000 -- 100% complete.
Time:224308 us, speed:23373 KB/s
OK

NAND write: device 0 offset 0x520000, size 0x253090
Time:894314 us, speed:2725 KB/s
 2437264 bytes written: OK

NAND erase.part: device 0 offset 0xa20000, size 0x500000
Erasing at 0xf00000 -- 100% complete.
Time:224327 us, speed:23371 KB/s
OK

NAND write: device 0 offset 0xa20000, size 0x253090
Time:894006 us, speed:2726 KB/s
 2437264 bytes written: OK
UBI: detaching mtd2 from ubi0
UBI: mtd2 is detached from ubi0
UBI: parsing mtd_dev string 'mtd=11'
UBI: attaching mtd2 to ubi0
UBI: scanning is finished
UBI: attached mtd2 (name "mtd=11", size 240 MiB) to ubi0
UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
UBI: good PEBs: 1927, bad PEBs: 0, corrupted PEBs: 0
UBI: user volume: 4, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
UBI: available PEBs: 23, total reserved PEBs: 1904, PEBs reserved for bad PEB handling: 40
reading SigmastarUpgrade.bin
31744000 bytes read in 2993 ms (10.1 MiB/s)
31744000 bytes written to volume rootfs
UBI: detaching mtd2 from ubi0
UBI: mtd2 is detached from ubi0
UBI: parsing mtd_dev string 'mtd=11'
UBI: attaching mtd2 to ubi0
UBI: scanning is finished
UBI: attached mtd2 (name "mtd=11", size 240 MiB) to ubi0
UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
UBI: good PEBs: 1927, bad PEBs: 0, corrupted PEBs: 0
UBI: user volume: 4, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
UBI: available PEBs: 23, total reserved PEBs: 1904, PEBs reserved for bad PEB handling: 40
reading SigmastarUpgrade.bin
7745536 bytes read in 746 ms (9.9 MiB/s)
7745536 bytes written to volume miservice
reading SigmastarUpgrade.bin
1777664 bytes read in 191 ms (8.9 MiB/s)
1777664 bytes written to volume customer
UBI: detaching mtd2 from ubi0
UBI: mtd2 is detached from ubi0
UBI: parsing mtd_dev string 'mtd=11'
UBI: attaching mtd2 to ubi0
UBI: scanning is finished
UBI: attached mtd2 (name "mtd=11", size 240 MiB) to ubi0
UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
UBI: good PEBs: 1927, bad PEBs: 0, corrupted PEBs: 0
UBI: user volume: 4, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 0
UBI: available PEBs: 23, total reserved PEBs: 1904, PEBs reserved for bad PEB handling: 40
reading SigmastarUpgrade.bin
1650688 bytes read in 180 ms (8.7 MiB/s)
1650688 bytes written to volume appconfigs
Saving Environment to NAND...
Erasing NAND...
Erasing at 0x440000 -- 100% complete.
Writing to NAND... OK
resetting ...

IPL g5da0ceb
D-1e
HW Reset
miupll_233MHz
MIU0 zq=0x003c
miu_bw_set
utmi_1_init done
utmi_2_init done
utmi_3_init done
usbpll init done......
cpupll init done
SPI 54M
clk_init done
P1 USB_rterm trim=0x0000
P1 USB_HS_TX_CURRENT trim=0x0001
P2 USB_rterm trim=0x0000
P2 USB_HS_TX_CURRENT trim=0x0001
P3 USB_rterm trim=0x0000
P3 USB_HS_TX_CURRENT trim=0x0001
PM_vol_bgap trim=0x0005
GCR_SAR_DATA trim=0x018f
ETH 10T output swing trim=0x0000
ETH 100T output swing trim=0x0010
ETH RX input impedance trim=0x0000
ETH TX output impedance trim=0x0001
MIPI_HS_RTERM trim=0x0001
MIPI_LP_RTERM trim=0x0000
128MB
BIST0_0001-OK
Enable MMU and CACHE
Load IPL_CUST from SPINAND
QUAD MODE ENABLE
Checksum OK

IPL_CUST g5da0ceb
runUBOOT()
runUBOOT()
[SPINAND]
SPI 54M
Load UBOOT from SPINAND
 -Verify UBOOT CRC32 passed!
 -Decompress UBOOT XZ
  decomp_size=0x000a12a4
Disable MMU and D-cache before jump to UBOOT▒

U-Boot 2015.01 (Dec 14 2020 - 17:22:37)

Version: I2g#######
       Watchdog enabled
I2C:   ready
DRAM:
WARNING: Caches not enabled
SPINAND: _MDrv_SPINAND_GET_INFO: Found SPINAND INFO
(0xCD) (0xEB) (0x11)
SPINAND: board_nand_init: CIS contains part info
256 MiB

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#9 2021-02-16 17:13:39

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

IPL g5da0ceb
D-1e
HW Reset
miupll_233MHz
MIU0 zq=0x003c
miu_bw_set
utmi_1_init done
utmi_2_init done
utmi_3_init done
usbpll init done......
cpupll init done
SPI 54M
clk_init done
P1 USB_rterm trim=0x0000
P1 USB_HS_TX_CURRENT trim=0x0001
P2 USB_rterm trim=0x0000
P2 USB_HS_TX_CURRENT trim=0x0001
P3 USB_rterm trim=0x0000
P3 USB_HS_TX_CURRENT trim=0x0001
PM_vol_bgap trim=0x0005
GCR_SAR_DATA trim=0x018f
ETH 10T output swing trim=0x0000
ETH 100T output swing trim=0x0010
ETH RX input impedance trim=0x0000
ETH TX output impedance trim=0x0001
MIPI_HS_RTERM trim=0x0001
MIPI_LP_RTERM trim=0x0000
128MB
BIST0_0001-OK
Enable MMU and CACHE
Load IPL_CUST from SPINAND
QUAD MODE ENABLE
Checksum OK

IPL_CUST g5da0ceb
runUBOOT()
runUBOOT()
[SPINAND]
SPI 54M
Load UBOOT from SPINAND
 -Verify UBOOT CRC32 passed!
 -Decompress UBOOT XZ
  decomp_size=0x000a0944
Disable MMU and D-cache before jump to UBOOT▒

M

Version: I2g92fa7f5
       Watchdog enabled
I2C:   ready
DRAM:
WARNING: Caches not enabled

自己手动做了一个 USB刷机固件 SigmastarUpgrade.bin

结果把系统搞死了, 是不是一定要官方那个 debug 刷机硬件才行? 还有救吗?

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#10 2021-02-19 13:45:59

fogwizard
会员
注册时间: 2019-03-19
累计积分: 34

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

ssd201的sdk默认不支持双缓冲,lvgl跑起来有撕裂感,是否有优化方法?

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#11 2021-02-19 13:48:50

奔跑的孩子
会员
注册时间: 2021-01-28
累计积分: 2

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

fogwizard 说:

ssd201的sdk默认不支持双缓冲,lvgl跑起来有撕裂感,是否有优化方法?

LVGL的linux_frame_buffer项目加入FB双缓
http://whycan.com/t_5887.html
(出处:哇酷开发者社区)

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#12 2021-02-19 15:26:10

fogwizard
会员
注册时间: 2019-03-19
累计积分: 34

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

哥,就是按照大神的帖子改的,ssd201平台finfo.smem_len打印出来不是2倍的buffer,无法切换,会crash, 使用单缓存可以显示,但是页面切换有撕裂感

最近编辑记录 fogwizard (2021-02-19 15:26:29)

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#13 2021-02-19 15:31:58

哇酷小管家
管理员
注册时间: 2021-01-14
累计积分: 2

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

fogwizard 说:

哥,就是按照大神的帖子改的,ssd201平台finfo.smem_len打印出来不是2倍的buffer,无法切换,会crash, 使用单缓存可以显示,但是页面切换有撕裂感

你可以在那个帖子回复详细情况,我邀请作者过来回帖,干洗支持。

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#14 2021-02-21 12:45:51

TeveT
会员
注册时间: 2019-07-01
累计积分: 48

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

嗯,下载编译烧录修改追踪改了一波,
这个打印出来还不够2倍的buffer大小,要修改 /config/fbdev.ini 修改缓冲区到2倍的大小 4800x1024
代码贴一下:

[FB_DEVICE]
FB_HWLAYER_ID = 1
FB_HWWIN_ID = 0
FB_HWLAYER_DST = 3
FB_HWWIN_FORMAT = 5
FB_HWLAYER_OUTPUTCOLOR = 1
FB_WIDTH = 1024
FB_HEIGHT = 600
FB_TIMMING_WIDTH = 1920
FB_TIMMING_HEIGHT = 1080
FB_MMAP_NAME = E_MMAP_ID_FB
FB_BUFFER_LEN = 4800
#unit:Kbyte,4096=4M, fbdev.ko alloc size = FB_BUFFER_LEN*1024

FB_BUFFER_LEN = 4800
这里原来是4096, 修改成4800即可。
显然 1024*600*4 *2 =4915200 ,但是4096*1024 = 4194304 不够用,那就会crash

这里你已经可以成功单缓冲显示了,sstar_disp_init 想必你已经成功调用,这里就不贴了,我贴另一个帖子上。



fogwizard 说:

哥,就是按照大神的帖子改的,ssd201平台finfo.smem_len打印出来不是2倍的buffer,无法切换,会crash, 使用单缓存可以显示,但是页面切换有撕裂感

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#15 2021-02-21 12:46:25

TeveT
会员
注册时间: 2019-07-01
累计积分: 48

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

注意,修改了 /config/fbdev.ini 要重启机器才生效。

TeveT 说:

....

fogwizard 说:

哥,就是按照大神的帖子改的,ssd201平台finfo.smem_len打印出来不是2倍的buffer,无法切换,会crash, 使用单缓存可以显示,但是页面切换有撕裂感

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#16 2021-02-23 15:00:42

pythinker
会员
注册时间: 2019-02-12
累计积分: 214

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

前面那几个分区都有备份分区,请问是如何实现主分区无法启动,自动使用备胎的?

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#17 2021-02-23 16:54:11

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

导出带oob的ubi分区数据到U盘根目录 20x_ubi.bin

echo UDISK > /dev/udisk_4g;mkdir /mnt/udisk -p;mount /dev/sda /mnt/udisk

nanddump -o -b -f /mnt/udisk/20x_ubi.bin /dev/mtd11

挂载到ubuntu:

sudo modprobe nandsim first_id_byte=0xad second_id_byte=0xda third_id_byte=0x10 fourth_id_byte=0x95
sudo dd if=/mnt/hgfs/D/20x_ubi.bin of=/dev/mtd0
sudo modprobe ubi
sudo modprobe ubifs
sudo ubiattach --mtdn=0 --vid-hdr-offset=2048
sudo mkdir /mnt/ubifs/     -p;sudo mount -t ubifs ubi0:rootfs /mnt/ubifs/
sudo mkdir /mnt/miservice  -p;sudo mount -t ubifs ubi0:miservice /mnt/miservice
sudo mkdir /mnt/customer   -p;sudo mount -t ubifs ubi0:miservice /mnt/customer
sudo mkdir /mnt/appconfigs -p;sudo mount -t ubifs ubi0:miservice /mnt/appconfigs

目录显示正常:

$ ls /mnt/ubifs/
appconfigs           bin    config    dev  home  lib32    media  opt   root  sbin  tmp    usr  vendor
audio_all_test_case  codec  customer  etc  lib   linuxrc  mnt    proc  run   sys   udisk  var
$
$ ls /mnt/
appconfigs/ customer/   hgfs/       miservice/  ubifs/
$
$ ls /mnt/appconfigs/
config_tool  dump_config  dump_mmap  fbdev.ini  LCM  lib  miu_protect  mmap.ini  modules  riu_r  riu_w  terminfo  vdec_fw  wifi
$
$ ls /mnt/miservice/
config_tool  dump_config  dump_mmap  fbdev.ini  LCM  lib  miu_protect  mmap.ini  modules  riu_r  riu_w  terminfo  vdec_fw  wifi
$
$ ls /mnt/customer/
config_tool  dump_config  dump_mmap  fbdev.ini  LCM  lib  miu_protect  mmap.ini  modules  riu_r  riu_w  terminfo  vdec_fw  wifi
$

这是我从 /dev/mtd11 读出来带oob数据的文件: 20x_ubi.7z


参考:

请问我在 ubuntu 可以模拟挂载ubi 文件系统吗?
http://whycan.com/t_6036.html#p59914
(出处:哇酷开发者社区)

最近编辑记录 SigmaStarStudy (2021-02-23 17:01:30)

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#18 2021-02-23 16:57:39

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

/ # 
/ # date;dd if=/dev/mtd11 of=/dev/null;date
Thu Jan  1 00:05:04 UTC 1970
493312+0 records in
493312+0 records out
252575744 bytes (240.9MB) copied, 30.425950 seconds, 7.9MB/s
Thu Jan  1 00:05:35 UTC 1970
/ #

初略测试spi nand读速度 240MB/(35-04)s = 8MB/s = 64Mbps

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#19 2021-02-23 17:36:03

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

SigmaStar #
SigmaStar # printenv bootcmd
bootcmd=bootlogo 0 0 0 0 0; mw 1f001cc0 11; gpio out 8 0; nand read.e 0x22000000 KERNEL 0x500000; gpio out 8 1; bootm 0x22000000;nand read.e 0x22000000 RECOVERY 0x500000; bootm 0x22000000
SigmaStar #

nand read.e 0x22000000 KERNEL 0x500000; bootm 0x22000000;

nand read.e 0x22000000 RECOVERY 0x500000; bootm 0x22000000

这个启动脚本的大意是, 如果KERNEL分区处的kernel启动失败, 那么就读备胎分区 RECOVERY 继续启动, 可是KERNEL启动都到了LINUX了,如果失败,UBOOT真还能继续接管吗?我表示怀疑。

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#20 昨天 17:24:03

SigmaStarStudy
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注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

楼上问题我咨询过启明工程师了,

uboot使用bootm加载 uImage文件, uImage比zImage 多出一个 0x40 大小的文件头,记录了 这个映像文件的类型、加载位置、生成时间、大小, CRC校验等信息, 如果读出来一个字节有问题, 必然CRC结果不对,bootm出错, 然后uboot命令行继续接管。

这样实现了备份分区继续引导的任务。

NAND read: device 0 offset 0x520000, size 0x500000
Time:524531 us, speed:9995 KB/s
 5242880 bytes read: OK
gpio debug MHal_GPIO_Pad_Set: pin=8
gpio[8] is 1
##  Booting kernel from Legacy Image at 22000000 ...
   Image Name:   MVX4##I2M#g#######KL_LX409##[BR:
   Image Type:   ARM Linux Kernel Image (lzma compressed)
   Data Size:    2437200 Bytes = 2.3 MiB
   Load Address: 20008000
   Entry Point:  20008000
   Verifying Checksum ... OK
-usb_stop(USB_PORT0)

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#21 昨天 17:24:27

SigmaStarStudy
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注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

setenv ipaddr 192.168.1.112
setenv serverip 192.168.1.99

setenv mtdparts mtdparts='nand0:384k@1280k(IPL0),384k(IPL1),384k(IPL_CUST0),384k(IPL_CUST1),768k(UBOOT0),768k(UBOOT1),384k(ENV0),0x20000(KEY_CUST),0x60000(LOGO),0x500000(KERNEL),0x500000(RECOVERY),-(UBI)'


nand erase.part UBI


ubi part UBI
ubi create rootfs 0x5200000
ubi create miservice 0xA00000
ubi create customer 0x500000
ubi create appconfigs 0x500000
 


tftp 0x21000000 rootfs.ubifs;    ubi write 0x21000000 rootfs ${filesize}
tftp 0x21000000 customer.ubifs;  ubi write 0x21000000 customer ${filesize}
tftp 0x21000000 appconfigs.ubifs;ubi write 0x21000000 appconfigs ${filesize}
tftp 0x21000000 miservice.ubifs; ubi write 0x21000000 miservice ${filesize}

用网线连接, 手动可以敲以上命令刷新rootfs文件系统


mkdir /mnt/ubifs -p;mount -t ubifs /dev/ubi0_0 /mnt/ubifs

进入linux可以用这个命令手动挂载文件系统

mkdir /mnt/ubifs -p;mount -t ubifs ubi0:rootfs /mnt/ubifs

也可以用卷标(volume)的形式挂载

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#22 昨天 17:37:55

SigmaStarStudy
会员
注册时间: 2021-02-15
累计积分: 23

Re: 趁放假把公司的买的启明云端的7寸 SSD202 板子带回来了, 上电试一试

ubi create miservice 0xA00000
ubi create customer 0x500000
ubi create appconfigs 0x500000
/ # dd if=/dev/ubi0_1  of=/dev/null
20584+0 records in
20584+0 records out
10539008 bytes (10.1MB) copied, 0.980598 seconds, 10.2MB/s
/ #
/ # dd if=/dev/ubi0_2  of=/dev/null
10416+0 records in
10416+0 records out
5332992 bytes (5.1MB) copied, 0.214397 seconds, 23.7MB/s
/ #
/ # dd if=/dev/ubi0_3  of=/dev/null
10416+0 records in
10416+0 records out
5332992 bytes (5.1MB) copied, 0.192827 seconds, 26.4MB/s
/ #

比实际实际创建的空间大一点, 应该是把oob数据都读出来了。

_dumpNandInformation:warning, Bytes / Page :  2048
_dumpNandInformation:warning, Pages / Block:  64
_dumpNandInformation:warning, Sector/ Page :  512
_dumpNandInformation:warning, Spare / Page :  64

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