WhyCan Forum(哇酷开发者社区)

$ sudo dmesg -c
  [50227.418454] usb 1-1: USB disconnect, device number 115
  [50302.847603] usb 1-1: new full-speed USB device number 116 using xhci_hcd
  [50302.996616] usb 1-1: New USB device found, idVendor=1f3a, idProduct=efe8, bcdDevice= 2.b3
  [50302.996620] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0

$ lsusb
  Bus 001 Device 116: ID 1f3a:efe8 Onda (unverified) V972 tablet in flashing mode

Pin-01 VDD
Pin-02 GND
Pin-03 LEDA PE6
Pin-04 RST  PE11
Pin-05 CS   PD21
Pin-06 RS   PD19  => (F1C200S)PD12
Pin-07 WR   PD18  => (F1C200S)PD0
Pin-08 VDD
Pin-09 DB11 PD13  => (F1C200S)PE11
Pin-10 DB12 PD14  => (F1C200S)PA0
Pin-11 DB13 PD15  => (F1C200S)PA1
Pin-12 DB14 PD16  => (F1C200S)PA2
Pin-13 DB15 PD17  => (F1C200S)PA3
Pin-14 DB5  PD6   => (F1C200S)PE5
Pin-15 DB6  PD7   => (F1C200S)PE6
Pin-16 DB7  PD8   => (F1C200S)PE7
Pin-17 DB8  PD10  => (F1C200S)PE8
Pin-18 DB9  PD11  => (F1C200S)PE9
Pin-19 DB10 PD12  => (F1C200S)PE10
Pin-20 DB0  PD1   => (F1C200S)PE0
Pin-21 DB1  PD2   => (F1C200S)PE1
Pin-22 DB2  PD3   => (F1C200S)PE2
Pin-23 DB3  PD4   => (F1C200S)PE3
Pin-24 DB4  PD5   => (F1C200S)PE4

  .global _start
     
  .equiv CCU_BASE,              0x01c20000
  .equiv GPIO_BASE,             0x01c20800
  .equiv UART1_BASE,            0x01c25400
  
  .equiv PLL_PERIPH_CTRL_REG,   0x0028
  .equiv AHB_APB_HCLKC_CFG_REG, 0x0054
  .equiv BUS_CLK_GATING_REG2,   0x0068
  .equiv BUS_SOFT_RST_REG2,     0x02d0
   
  .equiv PA,                    (0x24 * 0)
  .equiv PB,                    (0x24 * 1)
  .equiv PC,                    (0x24 * 2)
  .equiv PD,                    (0x24 * 3)
  .equiv PE,                    (0x24 * 4)
 
  .equiv PORT_CFG0,             0x00
  .equiv PORT_CFG1,             0x04
  .equiv PORT_CFG2,             0x08
  .equiv PORT_DATA,             0x10
  .equiv PORT_PUL0,             0x1c
  .equiv PORT_PUL1,             0x20
 
  .equiv UART_RBR,              0x00
  .equiv UART_DLL,              0x00
  .equiv UART_DLH,              0x04
  .equiv UART_IER,              0x04
  .equiv UART_IIR,              0x08
  .equiv UART_LCR,              0x0c
  .equiv UART_MCR,              0x10
  .equiv UART_USR,              0x7c
  
  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
    
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  b .
  b .
 
reset:
  ldr r0, =CCU_BASE
  ldr r1, =0x80041800
  str r1, [r0, #PLL_PERIPH_CTRL_REG]
  ldr r1, =0x00003180
  str r1, [r0, #AHB_APB_HCLKC_CFG_REG]
 
  ldr r4, =GPIO_BASE
  mov r1, #0x00000000
  str r1, [r4, #(PA + PORT_CFG0)]
  str r1, [r4, #(PC + PORT_CFG0)]
  str r1, [r4, #(PD + PORT_CFG0)]
  str r1, [r4, #(PD + PORT_CFG1)]
  str r1, [r4, #(PE + PORT_CFG0)]
  str r1, [r4, #(PE + PORT_CFG1)]
  ldr r1, =0x55555555
  str r1, [r4, #(PD + PORT_PUL0)]
  str r1, [r4, #(PD + PORT_PUL1)]
  str r1, [r4, #(PE + PORT_PUL0)]
  str r1, [r4, #(PE + PORT_PUL1)]
 
  ldr r5, =0x4000
  ldr r6, =64
 
  mov r1, #0
  mov r2, r5
  mov r3, r6
0:
  str r1, [r2]
  add r2, #4
  subs r3, #4
  bne 0b
 
  ldr r4, =GPIO_BASE
0:
  ldr r1, [r4, #(PD + PORT_DATA)]
  ands r1, #(1 << 0)
  bne 0b
 
  mov r1, #0
  ldr r2, [r4, #(PD + PORT_DATA)]
  and r2, #(1 << 12)
  lsl r2, #20
  orr r1, r2
  ldr r2, [r4, #(PA + PORT_DATA)]
  and r2, #0x07
  lsl r2, #12
  orr r1, r2
  ldr r2, [r4, #(PE + PORT_DATA)]
  ldr r3, =0x7ff
  and r2, r3
  orr r1, r2
  str r1, [r5]
1:
  ldr r1, [r4, #(PD + PORT_DATA)]
  ands r1, #(1 << 0)
  beq 1b
 
  add r5, #4
  subs r6, #4
  bne 0b
  
  bl uart_init
   
  ldr r0, =0x11223344
  bl uart_4byte
 
  ldr r5, =0x4000
  ldr r6, =64
0:
  ldr r0, [r5]
  bl uart_4byte
 
  ldr r0, =0xaa
  bl uart_byte
 
  add r5, #4
  subs r6, #4
  bne 0b
  b .
  
uart_init:
  push {r4, lr}
  ldr r4, =CCU_BASE
  ldr r1, =(1 << 21)
  str r1, [r4, #BUS_CLK_GATING_REG2]
  str r1, [r4, #BUS_SOFT_RST_REG2]
   
  ldr r4, =GPIO_BASE
  ldr r1, =0x5500
  str r1, [r4, #(PA + PORT_CFG0)]
 
  ldr r4, =UART1_BASE
  ldr r1, =0x00
  str r1, [r4, #UART_IER]
  ldr r1, =0xf7
  str r1, [r4, #UART_IIR]
  ldr r1, =0x00
  str r1, [r4, #UART_MCR]
  ldr r1, [r4, #UART_LCR]
  orr r1, #(1 << 7)
  str r1, [r4, #UART_LCR]
  ldr r1, =54
  str r1, [r4, #UART_DLL]
  ldr r1, =0x00
  str r1, [r4, #UART_DLH]
  ldr r1, [r4, #UART_LCR]
  bic r1, #(1 << 7)
  str r1, [r4, #UART_LCR]
  ldr r1, [r4, #UART_LCR]
  bic r1, #0x1f
  orr r1, #0x03
  str r1, [r4, #UART_LCR]
  pop {r4, pc}
   
uart_byte:
  push {r4, lr}
  ldr r4, =UART1_BASE
1:
  ldr r1, [r4, #UART_USR]
  tst r1, #(1 << 1)
  beq 1b
  strb r0, [r4, #UART_RBR]
  pop {r4, pc}
 
uart_4byte:
  push {r4, lr}
  mov r4, r0
  lsr r0, #24
  bl uart_byte
   
  mov r0, r4
  lsr r0, #16
  bl uart_byte
   
  mov r0, r4
  lsr r0, #8
  bl uart_byte
   
  mov r0, r4
  bl uart_byte
  pop {r4, pc}
  .end

PLL = (24MHz*N*K)/(M*P)

N = 13
K = 4
M = 1
P = 1
PLL = (24MHz*13*4)/(1*1) = 1248MHz

  .global _start
     
  .equiv CCU_BASE,              0x01c20000
  .equiv GPIO_BASE,             0x01c20800
  
  .equiv PLL_CPU_CTRL_REG,      0x0000
  .equiv PLL_PERIPH_CTRL_REG,   0x0028
  .equiv AHB_APB_HCLKC_CFG_REG, 0x0054
  .equiv BUS_CLK_GATING_REG2,   0x0068
  .equiv BUS_SOFT_RST_REG2,     0x02d0
   
  .equiv PD,                    (0x24 * 3)
  .equiv PORT_CFG0,             0x00
  .equiv PORT_CFG1,             0x04
  .equiv PORT_CFG2,             0x08
  .equiv PORT_DATA,             0x10
  .equiv PORT_PUL0,             0x1c
  .equiv PORT_PUL1,             0x20
 
  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
    
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  b .
  b .
 
reset:
  ldr r4, =CCU_BASE
  ldr r1, =(1 << 31) | (12 << 8) | (3 << 4)
  str r1, [r4, #PLL_CPU_CTRL_REG]
0:
  ldr r1, [r4, #PLL_CPU_CTRL_REG]
  tst r1, #(1 << 28)
  beq 0b
 
  ldr r1, =(1 << 31) | (1 << 18) | (31 << 8)
  str r1, [r4, #PLL_PERIPH_CTRL_REG]
0:
  ldr r1, [r4, #PLL_PERIPH_CTRL_REG]
  tst r1, #(1 << 28)
  beq 0b
 
  ldr r1, =(3 << 12)
  str r1, [r4, #AHB_APB_HCLKC_CFG_REG]
 
  ldr r4, =GPIO_BASE
  mov r1, #1
  str r1, [r4, #(PD + PORT_CFG0)]
0:
  eor r1, #1
  str r1, [r4, #(PD + PORT_DATA)]
  b 0b
  .end

  .global _start
     
  .equiv CCU_BASE,              0x01c20000
  .equiv GPIO_BASE,             0x01c20800
  
  .equiv PLL_CPU_CTRL_REG,      0x0000
  .equiv PLL_PERIPH_CTRL_REG,   0x0028
  .equiv AHB_APB_HCLKC_CFG_REG, 0x0054
  .equiv BUS_CLK_GATING_REG2,   0x0068
  .equiv BUS_SOFT_RST_REG2,     0x02d0
   
  .equiv PA,                    (0x24 * 0)
  .equiv PORT_CFG0,             0x00
  .equiv PORT_DATA,             0x10
 
  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
    
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  b .
  b .
 
reset:
  ldr r4, =CCU_BASE
  ldr r1, =(1 << 31) | (20 << 8) | (3 << 4)
  str r1, [r4, #PLL_CPU_CTRL_REG]
0:
  ldr r1, [r4, #PLL_CPU_CTRL_REG]
  tst r1, #(1 << 28)
  beq 0b
 
  ldr r0, =GPIO_BASE
  ldr r1, =0x1000
  str r1, [r0, #(PA + PORT_CFG0)]
0:
  eor r1, #8
  str r1, [r0, #(PA + PORT_DATA)]
  ldr r2, =1000000
1:
  subs r2, #1
  bne 1b
  b 0b
  .end

  .thumb
  .cpu cortex-m3
  .syntax unified
    
  .equiv GPIOA_CRL,    0x40010800
  .equiv GPIOA_CRH,    0x40010804
  .equiv GPIOA_IDR,    0x40010808
  .equiv GPIOA_ODR,    0x4001080c
 
  .equiv GPIOC_CRL,    0x40011000
  .equiv GPIOC_CRH,    0x40011004
  .equiv GPIOC_IDR,    0x40011008
  .equiv GPIOC_ODR,    0x4001100c
 
  .equiv RCC_CR,       0x40021000
  .equiv RCC_CFGR,     0x40021004
  .equiv RCC_APB2ENR,  0x40021018
 
  .equiv FLASH_ACR,    0x40022000
 
  .equiv STACKINIT,    0x20005000
     
  .global _start
  .section .text
 
  .org 0x0
  .word STACKINIT
  .word _start
   
  .org 0x100
  .align 2
  .thumb_func
_start:
  bl rcc_init
  bl flash_init
   
  ldr r4, =RCC_APB2ENR
  ldr r1, =(1 << 2)
  str r1, [r4]
  
  ldr r4, =GPIOA_CRH
  ldr r1, =(3 << 0)
  str r1, [r4]
  
  ldr r4, =GPIOA_ODR
  ldr r1, =0xffffffff
  ldr r2, =0x00000000
0:
  str r1, [r4]
  str r2, [r4]
 
  @eor r2, #(1 << 8)
  @str r2, [r4]
  b 0b
   
  .align 2
  .thumb_func
rcc_init:
  push {r4, lr}
  ldr r4, =RCC_CR
  mov r1, #(1 << 16)
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 17)
  bne 0b
 
  ldr r4, =RCC_CFGR
  @mov r1, #(7 << 18) @ 72MHz
  mov r1, #(14 << 18) @ 128MHz
  orr r1, #(1 << 16)
  str r1, [r4]
 
  ldr r4, =RCC_CR
  ldr r1, [r4]
  orr r1, #(1 << 24)
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 25)
  bne 0b
 
  ldr r4, =RCC_CFGR
  ldr r1, [r4]
  orr r1, #2
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 3)
  bne 0b
  pop {r4, pc}
 
  .align
  .thumb_func
flash_init:
  push {r4, lr}
  ldr r4, =FLASH_ACR
  mov r1, #0x32
  str r1, [r4]
  pop {r4, pc}
  .end

  .thumb
  .cpu cortex-m3
  .syntax unified
 
  .equiv NVIC_ISER0,   0xe000e100
  .equiv AFIO_EXTICR1, 0x40010008
 
  .equiv EXTI_IMR,     0x40010400
  .equiv EXTI_EMR,     0x40010404
  .equiv EXTI_RTSR,    0x40010408
  .equiv EXTI_FTSR,    0x4001040c
  .equiv EXTI_SWIER,   0x40010410
  .equiv EXTI_PR,      0x40010414
     
  .equiv GPIOA_CRL,    0x40010800
  .equiv GPIOA_CRH,    0x40010804
  .equiv GPIOA_IDR,    0x40010808
  .equiv GPIOA_ODR,    0x4001080c
  
  .equiv GPIOB_CRL,    0x40010c00
  .equiv GPIOB_CRH,    0x40010c04
  .equiv GPIOB_IDR,    0x40010c08
  .equiv GPIOB_ODR,    0x40010c0c
  
  .equiv GPIOC_CRL,    0x40011000
  .equiv GPIOC_CRH,    0x40011004
  .equiv GPIOC_IDR,    0x40011008
  .equiv GPIOC_ODR,    0x4001100c
  
  .equiv RCC_CR,       0x40021000
  .equiv RCC_CFGR,     0x40021004
  .equiv RCC_APB2ENR,  0x40021018
  
  .equiv FLASH_ACR,    0x40022000
  
  .equiv UART1_SR,     0x40013800
  .equiv UART1_DR,     0x40013804
  .equiv UART1_BRR,    0x40013808
  .equiv UART1_CR1,    0x4001380c
  .equiv UART1_CR2,    0x40013810
  .equiv UART1_CR3,    0x40013814
  
  .equiv STACKINIT,    0x20005000
      
  .global _start
  .section .text
  
  .org 0x0000
  .word STACKINIT
  .word _start
 
  .org 0x005c
  .word _exti1
   
  .org 0x0200
  .align 2
  .thumb_func
_exti1:
  push {r4, lr}
  ldrh r1, [r7]
  strh r1, [r5, #2]!
  ldrh r2, [r8]
  strh r2, [r5, #2]!

  ldr r4, =EXTI_PR
  mov r1, #(1 << 1)
  str r1, [r4]
  pop {r4, pc}
 
  .align 2
  .thumb_func
_start:
  bl rcc_init
  bl flash_init
  bl uart_init
   
  ldr r4, =RCC_APB2ENR
  ldr r1, [r4]
  orr r1, #(1 << 4) | (1 << 3) | (1 << 2)
  str r1, [r4]
   
  ldr r4, =GPIOB_CRL
  ldr r1, =0x88888888
  str r1, [r4]
  
  ldr r4, =GPIOB_CRH
  ldr r1, =0x88888888
  str r1, [r4]
    
  ldr r4, =GPIOC_CRL
  ldr r1, =0x88888888
  str r1, [r4]
  
  ldr r4, =GPIOC_CRH
  ldr r1, =0x88888888
  str r1, [r4]
 
  ldr r4, =EXTI_IMR
  ldr r1, =(1 << 1)
  str r1, [r4]
 
  ldr r4, =EXTI_EMR
  ldr r1, =(1 << 1)
  str r1, [r4]
 
  ldr r4, =EXTI_FTSR
  ldr r1, =(1 << 1)
  str r1, [r4]
 
  ldr r4, =AFIO_EXTICR1
  ldr r1, =(1 << 4)
  str r1, [r4]
 
  ldr r5, =buf
  ldr r6, =buf
  ldr r7, =GPIOB_IDR
  ldr r8, =GPIOC_IDR
   
  ldr r4, =NVIC_ISER0
  ldr r1, =(1 << 7)
  str r1, [r4]
 
  add r6, #(64 * 2 * 2)
0:
  cmp r5, r6
  bcc 0b
   
  ldr r4, =NVIC_ISER0
  mov r1, #0
  str r1, [r4]
   
  ldr r4, =AFIO_EXTICR1
  mov r1, #0
  str r1, [r4]
 
  ldr r5, =buf
  ldr r6, =64
0:
  ldrh r1, [r5, #2]!
  lsl r1, #31
 
  eor r0, r0
  ldrh r0, [r5, #2]!
  orr r0, r1
  bl uart_4byte
 
  subs r6, #1
  bne 0b
 
  ldr r0, =0x11223344
  bl uart_4byte
  b .
 
  .align 2
  .thumb_func
uart_init:
  push {r4, lr}
  ldr r4, =RCC_APB2ENR
  ldr r1, [r4]
  ldr r2, =(1 << 14) | (1 << 2) | (1 << 0)
  orr r1, r2
  str r1, [r4]
  
  ldr r4, =GPIOA_CRH
  ldr r1, [r4]
  bic r1, #0xff0
  orr r1, #0x4b0
  str r1, [r4]
  
  ldr r4, =UART1_BRR
  @ldr r1, =(39 << 4) | (1 << 0) @ 115200bps 72MHz
  ldr r1, =(69 << 4) | (7 << 0) @ 115200bps 128MHz
  str r1, [r4]
  
  ldr r4, =UART1_CR1
  ldr r1, =(1 << 13) | (1 << 3)
  str r1, [r4]
  pop {r4, pc}
  
  .align 2
  .thumb_func
uart_byte:
  push {r4, lr}
  ldr r4, =UART1_SR
0:
  ldr r1, [r4]
  tst r1, #(1 << 7)
  beq 0b
  
  ldr r4, =UART1_DR
  str r0, [r4]
  pop {r4, pc}
   
  .align 2
  .thumb_func
uart_4byte:
  push {r4, lr}
  mov r4, r0
  lsr r0, #24
  bl uart_byte
 
  mov r0, r4
  lsr r0, #16
  bl uart_byte
   
  mov r0, r4
  lsr r0, #8
  bl uart_byte
   
  mov r0, r4
  bl uart_byte
  pop {r4, pc}
    
  .align 2
  .thumb_func
rcc_init:
  push {r4, lr}
  ldr r4, =RCC_CR
  ldr r1, =(1 << 26) | (1 << 16)
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 17)
  bne 0b
  
  ldr r4, =RCC_CFGR
  @mov r1, #(7 << 18) @ 72MHz
  mov r1, #(14 << 18) @ 128MHz
  orr r1, #(1 << 16)
  str r1, [r4]
  
  ldr r4, =RCC_CR
  ldr r1, [r4]
  orr r1, #(1 << 24)
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 25)
  bne 0b
  
  ldr r4, =RCC_CFGR
  ldr r1, [r4]
  orr r1, #2
  str r1, [r4]
0:
  ldr r1, [r4]
  tst r1, #(1 << 3)
  bne 0b
  pop {r4, pc}
  
  .align 2
  .thumb_func
flash_init:
  push {r4, lr}
  ldr r4, =FLASH_ACR
  mov r1, #0x32
  str r1, [r4]
  pop {r4, pc}
 
  .data
  .align 2
buf: .skip (64 * 2 * 2)
  .end

   .global _start
  
  .equiv PIO_BASE,  0x01c20800 
  .equiv PD,        (0x24 * 3)
  .equiv PE,        (0x24 * 4)
  .equiv PIO_CFG0,  0x00
  .equiv PIO_CFG1,  0x04
  .equiv PIO_CFG2,  0x08
  .equiv PIO_DATA,  0x10

  .equiv LCD_CS,    (1 << 21)
  .equiv LCD_RS,    (1 << 19)
  .equiv LCD_WR,    (1 << 18)
  .equiv LCD_RST,   (1 << 11)
  .equiv LCD_BL,    (1 << 6)
  
  /*
  Pin-01 VDD
  Pin-02 GND
  Pin-03 LEDA PE6
  Pin-04 RST  PE11
  Pin-05 CS   PD21
  Pin-06 RS   PD19
  Pin-07 WR   PD18
  Pin-08 VDD
  Pin-09 DB11 PD13
  Pin-10 DB12 PD14
  Pin-11 DB13 PD15
  Pin-12 DB14 PD16
  Pin-13 DB15 PD17
  Pin-14 DB5  PD6
  Pin-15 DB6  PD7
  Pin-16 DB7  PD8
  Pin-17 DB8  PD10
  Pin-18 DB9  PD11
  Pin-19 DB10 PD12
  Pin-20 DB0  PD1
  Pin-21 DB1  PD2
  Pin-22 DB2  PD3
  Pin-23 DB3  PD4
  Pin-24 DB4  PD5
  */

  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
   
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  b .
  b .
   
reset:
  ldr r4, =PIO_BASE + PD
  ldr r1, =0x11111111
  str r1, [r4, #PIO_CFG0]
  str r1, [r4, #PIO_CFG1]
  str r1, [r4, #PIO_CFG2]

  ldr r4, =PIO_BASE + PE
  ldr r1, =0x11111111
  str r1, [r4, #PIO_CFG0]
  str r1, [r4, #PIO_CFG1]

  ldr r4, =PIO_BASE + PD
  ldr r1, =0xffffffff
  str r1, [r4, #PIO_DATA]

  ldr r4, =PIO_BASE + PE
  ldr r1, =0xffffffff
  str r1, [r4, #PIO_DATA]

  bl lcd_rst

  ldr r0, =0xfe
  bl lcd_cmd
  ldr r0, =0xef
  bl lcd_cmd

  ldr r0, =0x36
  bl lcd_cmd
  ldr r0, =0x28
  bl lcd_dat

  ldr r0, =0x3a
  bl lcd_cmd
  ldr r0, =0x05
  bl lcd_dat

  ldr r0, =0xa4
  bl lcd_cmd
  ldr r0, =0x44
  bl lcd_dat
  ldr r0, =0x44
  bl lcd_dat

  ldr r0, =0xa5
  bl lcd_cmd
  ldr r0, =0x42
  bl lcd_dat
  ldr r0, =0x42
  bl lcd_dat

  ldr r0, =0xaa
  bl lcd_cmd
  ldr r0, =0x88
  bl lcd_dat
  ldr r0, =0x88
  bl lcd_dat

  ldr r0, =0xe8
  bl lcd_cmd
  ldr r0, =0x11
  bl lcd_dat
  ldr r0, =0x0b
  bl lcd_dat

  ldr r0, =0xe3
  bl lcd_cmd
  ldr r0, =0x01
  bl lcd_dat
  ldr r0, =0x10
  bl lcd_dat

  ldr r0, =0xff
  bl lcd_cmd
  ldr r0, =0x61
  bl lcd_dat

  ldr r0, =0xac
  bl lcd_cmd
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0xad
  bl lcd_cmd
  ldr r0, =0x33
  bl lcd_dat

  ldr r0, =0xae
  bl lcd_cmd
  ldr r0, =0x2b
  bl lcd_dat

  ldr r0, =0xaf
  bl lcd_cmd
  ldr r0, =0x55
  bl lcd_dat

  ldr r0, =0xa6
  bl lcd_cmd
  ldr r0, =0x2a
  bl lcd_dat
  ldr r0, =0x2a
  bl lcd_dat

  ldr r0, =0xa7
  bl lcd_cmd
  ldr r0, =0x2b
  bl lcd_dat
  ldr r0, =0x2b
  bl lcd_dat

  ldr r0, =0xa8
  bl lcd_cmd
  ldr r0, =0x18
  bl lcd_dat
  ldr r0, =0x18
  bl lcd_dat

  ldr r0, =0xa9
  bl lcd_cmd
  ldr r0, =0x2a
  bl lcd_dat
  ldr r0, =0x2a
  bl lcd_dat

  ldr r0, =0x2b
  bl lcd_cmd
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0xef
  bl lcd_dat

  ldr r0, =0x2a
  bl lcd_cmd
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x01
  bl lcd_dat
  ldr r0, =0x3f
  bl lcd_dat

  ldr r0, =0x2c
  bl lcd_cmd

  ldr r0, =0xf0
  bl lcd_cmd
  ldr r0, =0x02
  bl lcd_dat
  ldr r0, =0x01
  bl lcd_dat
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x06
  bl lcd_dat
  ldr r0, =0x09
  bl lcd_dat
  ldr r0, =0x0c
  bl lcd_dat

  ldr r0, =0xf1
  bl lcd_cmd
  ldr r0, =0x01
  bl lcd_dat
  ldr r0, =0x03
  bl lcd_dat
  ldr r0, =0x00
  bl lcd_dat
  ldr r0, =0x3a
  bl lcd_dat
  ldr r0, =0x3e
  bl lcd_dat
  ldr r0, =0x09
  bl lcd_dat

  ldr r0, =0xf2
  bl lcd_cmd
  ldr r0, =0x0c
  bl lcd_dat
  ldr r0, =0x09
  bl lcd_dat
  ldr r0, =0x26
  bl lcd_dat
  ldr r0, =0x07
  bl lcd_dat
  ldr r0, =0x07
  bl lcd_dat
  ldr r0, =0x30
  bl lcd_dat

  ldr r0, =0xf3
  bl lcd_cmd
  ldr r0, =0x09
  bl lcd_dat
  ldr r0, =0x06
  bl lcd_dat
  ldr r0, =0x57
  bl lcd_dat
  ldr r0, =0x03
  bl lcd_dat
  ldr r0, =0x03
  bl lcd_dat
  ldr r0, =0x6b
  bl lcd_dat

  ldr r0, =0xf4
  bl lcd_cmd
  ldr r0, =0x0d
  bl lcd_dat
  ldr r0, =0x1d
  bl lcd_dat
  ldr r0, =0x1c
  bl lcd_dat
  ldr r0, =0x06
  bl lcd_dat
  ldr r0, =0x08
  bl lcd_dat
  ldr r0, =0x0f
  bl lcd_dat

  ldr r0, =0xf5
  bl lcd_cmd
  ldr r0, =0x0c
  bl lcd_dat
  ldr r0, =0x05
  bl lcd_dat
  ldr r0, =0x06
  bl lcd_dat
  ldr r0, =0x33
  bl lcd_dat
  ldr r0, =0x31
  bl lcd_dat
  ldr r0, =0x0f
  bl lcd_dat

  ldr r0, =0x11
  bl lcd_cmd
  ldr r0, =10000
  bl delay

  ldr r0, =0x29
  bl lcd_cmd
  ldr r0, =10000
  bl delay

  ldr r0, =0x2c
  bl lcd_cmd

  ldr r4, =320*30
  ldr r5, =0xf800
0:
  mov r0, r5
  bl lcd_dat
  subs r4, #1
  bne 0b

  ldr r4, =PIO_BASE + PE
  ldr r5, =0xffffffff
0:
  eor r5, #LCD_BL
  str r5, [r4, #PIO_DATA]
  ldr r0, =50000
  bl delay
  b 0b

delay:
  push {lr}
0:
  subs r0, #1
  bne 0b
  pop {pc}

lcd_rst:
  push {r4, r5, lr}
  ldr r4, =PIO_BASE + PE
  ldr r5, =0xffffffff
  str r5, [r4, #PIO_DATA]
  ldr r0, =10000
  bl delay

  bic r5, #LCD_RST
  str r5, [r4, #PIO_DATA]
  ldr r0, =10000
  bl delay

  orr r5, #LCD_RST
  str r5, [r4, #PIO_DATA]
  ldr r0, =10000
  bl delay
  pop {r4, r5, pc}

lcd_wr:
  push {r4, r5, lr}
  ldr r4, =PIO_BASE + PD

  /*
  mov r2, r0, lsl #11
  and r2, #(0x1f << 11)
  mov r3, r0, lsr #11
  and r3, #0x1f
  orr r2, r3
  and r3, r0, #0x7e0
  orr r2, r3
  mov r0, r2
  */

  and r2, r0, #0x00ff
  and r3, r0, #0xff00
  lsl r2, #1
  lsl r3, #2

  mov r5, #0
  orr r5, r1
  orr r5, r2
  orr r5, r3
  str r5, [r4, #PIO_DATA]
  ldr r0, =100
  bl delay
  
  bic r5, #LCD_CS
  str r5, [r4, #PIO_DATA]
  ldr r0, =100
  bl delay
  
  bic r5, #LCD_WR
  str r5, [r4, #PIO_DATA]
  ldr r0, =100
  bl delay
  
  orr r5, #LCD_WR
  str r5, [r4, #PIO_DATA]
  ldr r0, =100
  bl delay
  
  orr r5, #LCD_CS
  str r5, [r4, #PIO_DATA]
  ldr r0, =100
  bl delay
  pop {r4, r5, pc}

lcd_dat:
  push {lr}
  mov r1, #LCD_CS | LCD_WR | LCD_RS
  bl lcd_wr
  pop {pc}

lcd_cmd:
  push {lr}
  mov r1, #LCD_CS | LCD_WR
  bl lcd_wr
  pop {pc}
  .end

CMD:0x800
DAT:0x100
CMD:0x1000
DAT:0x700
CMD:0x1800
DAT:0xc002
CMD:0x2000
DAT:0x0
CMD:0x4000
DAT:0x1200
CMD:0x4800
DAT:0x0
CMD:0x5000
DAT:0x0
CMD:0x6000
DAT:0x0
CMD:0x6800
DAT:0x0
CMD:0x7800
DAT:0x0
CMD:0x8000
DAT:0x0
CMD:0x8800
DAT:0x3800
CMD:0x9000
DAT:0x0
CMD:0x9800
DAT:0x0
CMD:0x3800
DAT:0x800
CMD:0x8000
DAT:0x8682
CMD:0x8800
DAT:0x3e60
CMD:0x9000
DAT:0xc080
CMD:0x9800
DAT:0x603
CMD:0x4820
DAT:0xf000
CMD:0x5820
DAT:0x7000
CMD:0x20
DAT:0x0
CMD:0x820
DAT:0x0
CMD:0x8020
DAT:0x0
CMD:0x8820
DAT:0x3d00
CMD:0x9020
DAT:0x2000
CMD:0xa820
DAT:0x2a00
CMD:0xb020
DAT:0x2000
CMD:0xb820
DAT:0x3b00
CMD:0xc020
DAT:0x1000
CMD:0xc820
DAT:0x3f00
CMD:0xe020
DAT:0x1500
CMD:0xe820
DAT:0x2000
CMD:0x8040
DAT:0x0
CMD:0x8840
DAT:0x78e0
CMD:0x9040
DAT:0x0
CMD:0x9840
DAT:0xf920
CMD:0x60
DAT:0x714
CMD:0x860
DAT:0x800
CMD:0x5060
DAT:0x0
CMD:0x80
DAT:0x0
CMD:0x880
DAT:0x0
CMD:0x1080
DAT:0x0
CMD:0x1880
DAT:0x0
CMD:0x2080
DAT:0x0
CMD:0x2880
DAT:0x0
CMD:0x8080
DAT:0x8000
CMD:0x9080
DAT:0x600
CMD:0x1800
DAT:0x4020
CMD:0x3800
DAT:0x9920
CMD:0x8040
DAT:0x0
CMD:0x8840
DAT:0x78e0
CMD:0x9040
DAT:0x0
CMD:0x9840
DAT:0xf920
CMD:0x20
DAT:0x78e0
CMD:0x820
DAT:0x0
CMD:0x1020
DAT:0x0

  .global _start
   
  .equiv PIO_BASE,  0x01c20800 
  .equiv PD,        (0x24 * 3)
  .equiv PE,        (0x24 * 4)
  .equiv PIO_CFG0,  0x00
  .equiv PIO_CFG1,  0x04
  .equiv PIO_CFG2,  0x08
  .equiv PIO_DATA,  0x10
 
  .equiv LCD_CS,    (1 << 21)
  .equiv LCD_RD,    (1 << 20)
  .equiv LCD_RS,    (1 << 19)
  .equiv LCD_WR,    (1 << 18)
  .equiv LCD_RST,   (1 << 11)
  .equiv LCD_BL,    (1 << 6)
   
  .arm
  .text
_start:
  .long 0xea000016
  .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
  .long 0, __spl_size
  .byte 'S', 'P', 'L', 2
  .long 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
  .long 0, 0, 0, 0, 0, 0, 0, 0
    
_vector:
  b reset
  b .
  b .
  b .
  b .
  b .
  b .
  b .
    
reset:
  ldr r4, =PIO_BASE + PD
  ldr r1, =0x11111111
  str r1, [r4, #PIO_CFG0]
  str r1, [r4, #PIO_CFG1]
  ldr r1, =0x00111111
  str r1, [r4, #PIO_CFG2]
 
  ldr r4, =PIO_BASE + PE
  ldr r1, [r4, #PIO_CFG0]
  bic r1, #0xf000000
  orr r1, #0x1000000
  str r1, [r4, #PIO_CFG0]
 
  ldr r1, [r4, #PIO_CFG1]
  bic r1, #0xf000
  orr r1, #0x1000
  str r1, [r4, #PIO_CFG1]
 
  ldr r4, =PIO_BASE + PD
  ldr r1, =0xffffffff
  str r1, [r4, #PIO_DATA]
 
  ldr r4, =PIO_BASE + PE
  ldr r1, =0xffffffff
  str r1, [r4, #PIO_DATA]
 
  bl lcd_rst
 
  ldr r0, =0x800
  bl lcd_cmd
 
  ldr r0, =0x100
  bl lcd_dat
 
  ldr r0, =0x1000
  bl lcd_cmd
 
  ldr r0, =0x700
  bl lcd_dat
 
  ldr r0, =0x1800
  bl lcd_cmd
 
  ldr r0, =0xc002
  bl lcd_dat
 
  ldr r0, =0x2000
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x4000
  bl lcd_cmd
 
  ldr r0, =0x1200
  bl lcd_dat
 
  ldr r0, =0x4800
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x5000
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x6000
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x6800
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x7800
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8000
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8800
  bl lcd_cmd
 
  ldr r0, =0x3800
  bl lcd_dat
 
  ldr r0, =0x9000
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x9800
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x3800
  bl lcd_cmd
 
  ldr r0, =0x800
  bl lcd_dat
 
  ldr r0, =0x8000
  bl lcd_cmd
 
  ldr r0, =0x8682
  bl lcd_dat
 
  ldr r0, =0x8800
  bl lcd_cmd
 
  ldr r0, =0x3e60
  bl lcd_dat
 
  ldr r0, =0x9000
  bl lcd_cmd
 
  ldr r0, =0xc080
  bl lcd_dat
 
  ldr r0, =0x9800
  bl lcd_cmd
 
  ldr r0, =0x603
  bl lcd_dat
 
  ldr r0, =0x4820
  bl lcd_cmd
 
  ldr r0, =0xf000
  bl lcd_dat
 
  ldr r0, =0x5820
  bl lcd_cmd
 
  ldr r0, =0x7000
  bl lcd_dat
 
  ldr r0, =0x20
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x820
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8020
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8820
  bl lcd_cmd
 
  ldr r0, =0x3d00
  bl lcd_dat
 
  ldr r0, =0x9020
  bl lcd_cmd
 
  ldr r0, =0x2000
  bl lcd_dat
 
  ldr r0, =0xa820
  bl lcd_cmd
 
  ldr r0, =0x2a00
  bl lcd_dat
 
  ldr r0, =0xb020
  bl lcd_cmd
 
  ldr r0, =0x2000
  bl lcd_dat
 
  ldr r0, =0xb820
  bl lcd_cmd
 
  ldr r0, =0x3b00
  bl lcd_dat
 
  ldr r0, =0xc020
  bl lcd_cmd
 
  ldr r0, =0x1000
  bl lcd_dat
 
  ldr r0, =0xc820
  bl lcd_cmd
 
  ldr r0, =0x3f00
  bl lcd_dat
 
  ldr r0, =0xe020
  bl lcd_cmd
 
  ldr r0, =0x1500
  bl lcd_dat
 
  ldr r0, =0xe820
  bl lcd_cmd
 
  ldr r0, =0x2000
  bl lcd_dat
 
  ldr r0, =0x8040
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8840
  bl lcd_cmd
 
  ldr r0, =0x78e0
  bl lcd_dat
 
  ldr r0, =0x9040
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x9840
  bl lcd_cmd
 
  ldr r0, =0xf920
  bl lcd_dat
 
  ldr r0, =0x60
  bl lcd_cmd
 
  ldr r0, =0x714
  bl lcd_dat
 
  ldr r0, =0x860
  bl lcd_cmd
 
  ldr r0, =0x800
  bl lcd_dat
 
  ldr r0, =0x5060
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x80
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x880
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x1080
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x1880
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x2080
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x2880
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8080
  bl lcd_cmd
 
  ldr r0, =0x8000
  bl lcd_dat
 
  ldr r0, =0x9080
  bl lcd_cmd
 
  ldr r0, =0x600
  bl lcd_dat
 
  ldr r0, =0x1800
  bl lcd_cmd
 
  ldr r0, =0x4020
  bl lcd_dat
 
  ldr r0, =0x3800
  bl lcd_cmd
 
  ldr r0, =0x9920
  bl lcd_dat
 
  ldr r0, =0x8040
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x8840
  bl lcd_cmd
 
  ldr r0, =0x78e0
  bl lcd_dat
 
  ldr r0, =0x9040
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x9840
  bl lcd_cmd
 
  ldr r0, =0xf920
  bl lcd_dat
 
  ldr r0, =0x20
  bl lcd_cmd
 
  ldr r0, =0x78e0
  bl lcd_dat
 
  ldr r0, =0x820
  bl lcd_cmd
 
  ldr r0, =0x0
  bl lcd_dat
 
  ldr r0, =0x1020
  bl lcd_cmd
 
  ldr r4, =320*80
  ldr r5, =0x1f
0:
  mov r0, r5
  bl lcd_dat
  subs r4, #1
  bne 0b
   
  ldr r4, =320*80
  ldr r5, =0x7e0
0:
  mov r0, r5
  bl lcd_dat
  subs r4, #1
  bne 0b
   
  ldr r4, =320*80
  ldr r5, =0xf800
0:
  mov r0, r5
  bl lcd_dat
  subs r4, #1
  bne 0b
  b .
 
delay:
  push {lr}
0:
  subs r0, #1
  bne 0b
  pop {pc}
 
lcd_rst:
  push {r4, r5, lr}
  ldr r4, =PIO_BASE + PE
  ldr r5, =0xffffffff
 
  bic r5, #LCD_RST
  str r5, [r4, #PIO_DATA]
  ldr r0, =10000
  bl delay
 
  orr r5, #LCD_RST
  str r5, [r4, #PIO_DATA]
  ldr r0, =10000
  bl delay
  pop {r4, r5, pc}
 
lcd_wr:
  push {r4, r5, lr}
  ldr r4, =PIO_BASE + PD
 
  and r2, r0, #0x00ff
  and r3, r0, #0xff00
  lsl r2, #1
  lsl r3, #2
 
  eor r5, r5
  orr r5, r1
  orr r5, r2
  orr r5, r3
  orr r5, #LCD_RD
  str r5, [r4, #PIO_DATA]
 
  orr r5, #LCD_WR
  str r5, [r4, #PIO_DATA]
  pop {r4, r5, pc}
 
lcd_dat:
  push {lr}
  mov r1, #LCD_RS
  bl lcd_wr
  pop {pc}
 
lcd_cmd:
  push {lr}
  mov r1, #0
  bl lcd_wr
  pop {pc}
  .end

$ xxd trimui_model_S_dark_V0.105_en.img | head
  00000000: 494d 4147 4557 5459 0003 0000 6000 0000  IMAGEWTY....`...
  00000010: 0000 d004 3402 1000 00c8 5606 0000 0000  ....4.....V.....
  00000020: 0004 0000 3412 0000 4387 0000 0001 0000  ....4...C.......
  00000030: 0001 0000 0100 0000 0004 0000 1c00 0000  ................
  00000040: 0004 0000 0000 0000 0000 0000 0000 0000  ................
  00000050: 0000 0000 0000 0000 0000 0000 0000 0000  ................
  00000060: 00c1 8449 10d9 a471 4011 e4b9 9069 4421  ...I...q@....iD!
  00000070: 00e1 c4a9 9079 6451 4031 2419 1009 0401  .....ydQ@1$.....
  00000080: 0001 0409 1019 2431 4051 6479 90a9 c4e1  ......$1@Qdy....
  00000090: 0021 4469 90b9 e411 4071 a4d9 1049 84c1  .!Di....@q...I..

$ cd
$ git clone https://github.com/Ithamar/awutils
$ cd awutils
$ gcc parsecfg.c twofish.c rc6.c awimage.c -o awimage -I.

$ ./awimage ../trimui_model_S_dark_V0.105_en.img 
  ./awimage: unpacking ../trimui_model_S_dark_V0.105_en.img to ../trimui_model_S_dark_V0.105_en.img.dump
  Extracting: COMMON   SYS_CONFIG100000 (45841, 45856)
  Extracting: COMMON   SYS_CONFIG_BIN00 (28672, 28672)
  Extracting: COMMON   SPLIT_0000000000 (512, 512)
  Extracting: COMMON   SYS_CONFIG000000 (3119, 3120)
  Extracting: COMMON   DTB_CONFIG000000 (50176, 50176)
  Extracting: BOOT     BOOT0_0000000000 (16384, 16384)
  Extracting: 12345678 1234567890BOOT_0 (32768, 32768)
  Extracting: 12345678 UBOOT_0000000000 (671744, 671744)
  Extracting: 12345678 TOC1_00000000000 (8, 16)
  Extracting: 12345678 TOC0_00000000000 (8, 16)
  Extracting: FES      FES_1-0000000000 (11648, 11648)
  Extracting: 12345678 BOOTPKG-00000000 (753664, 753664)
  Extracting: PXTOOLSB XXXXXXXXXXXXXXXX (147968, 147968)
  Extracting: UPFLYTLS XXXXXXXXXXXXXXXX (165019, 165024)
  Extracting: UPFLTL32 XXXXXXXXXXXXXXXX (150847, 150848)
  Extracting: 12345678 1234567890CARDTL (73216, 73216)
  Extracting: 12345678 1234567890SCRIPT (1758, 1760)
  Extracting: 12345678 1234567890___MBR (65536, 65536)
  Extracting: 12345678 1234567890DLINFO (16384, 16384)
  Extracting: 12345678 1234567890ARISC (15, 16)
  Extracting: RFSFAT16 BOOTLOGO_FEX0000 (153738, 153744)
  Extracting: RFSFAT16 VBOOTLOGO_FEX000 (4, 16)
  Extracting: RFSFAT16 ENV_FEX000000000 (131072, 131072)
  Extracting: RFSFAT16 VENV_FEX00000000 (4, 16)
  Extracting: RFSFAT16 BOOT_FEX00000000 (3124088, 3124096)
  Extracting: RFSFAT16 VBOOT_FEX0000000 (4, 16)
  Extracting: RFSFAT16 ROOTFS_FEX000000 (100663296, 100663296)
  Extracting: RFSFAT16 VROOTFS_FEX00000 (4, 16)

$ file * | grep -i Linux
  RFSFAT16_BOOT_FEX00000000:     u-boot legacy uImage, ARM OpenWrt Linux-3.10.65, Linux/ARM, OS Kernel Image (Not compressed), 3124024 bytes, Thu Jan  1 00:00:00 1970, Load Address: 0x80008000, Entry Point: 0x80008000, Header CRC: 0x1877E4E2, Data CRC: 0x8DD5320A
  RFSFAT16_ROOTFS_FEX000000:     Linux rev 1.0 ext2 filesystem data, UUID=57f8f4bc-abf4-655f-bf67-946fc0f9f25b (extents) (large files)

$ strings RFSFAT16_BOOT_FEX00000000 | grep Linux
  ARM OpenWrt Linux-3.10.65
  Uncompressing Linux...
   Linux Documentah
  Linux

$ dd if=RFSFAT16_BOOT_FEX00000000 of=zImage bs=1 skip=64
  3124024+0 records in
  3124024+0 records out
  3124024 bytes (3.1 MB, 3.0 MiB) copied, 5.43237 s, 575 kB/s

$ file zImage
  zImage: Linux kernel ARM boot executable zImage (little-endian)

$ file "COMMON  _DTB_CONFIG000000"
  COMMON  _DTB_CONFIG000000: Device Tree Blob version 17, size=45683, boot CPU=0, string block size=7371, DT structure block size=38240

$ cp "COMMON  _DTB_CONFIG000000" dtb
$ dtc -I dtb -O dts -f dtb -o trimui.dts
$ vim trimui.dts
  lcd0@0 {
    allwinner,pins = "PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD18\0PD20\0PD21";
    allwinner,function = "lcd0";
    allwinner,pname = "lcdd5\0lcdd6\0lcdd7\0lcdd10\0lcdd11\0lcdd12\0lcdclk\0lcdhsync\0lcdvsync";

  sdc0@0 {
    allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";

  lcd0@01c0c000 {
    lcd_x = < 0x140 >;
    lcd_y = < 0xf0 >;
    lcd_width = < 0x32 >;
    lcd_height = < 0x25 >;
    lcd_pwm_used = < 0x01 >;
    lcd_pwm_ch = < 0x01 >;
    lcd_hbp = < 0x26 >;
    lcd_ht = < 0x465 >;
    lcd_hspw = < 0x12 >;
    lcd_vbp = < 0x06 >;
    lcd_vt = < 0x11e >;
    lcd_vspw = < 0x04 >;
    lcd_cpu_if = < 0x00 >;

  keyboard {
    compatible = "allwinner,keyboard_2000mv";

  chosen {
    bootargs = "earlyprintk=sunxi-uart,0x01c25000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";

#include <stdio.h>
#include <stdlib.h>
#include <SDL.h>
 
int main(int argc, char** argv)
{
  uint32_t cnt=0;
  SDL_Surface* screen=NULL;
  uint32_t col[]={0xf800, 0x7e0, 0x1f};
 
  SDL_Init(SDL_INIT_VIDEO);
  screen = SDL_SetVideoMode(320, 240, 16, SDL_SWSURFACE | SDL_DOUBLEBUF);
  while(cnt < 600){
    cnt+= 1;
    SDL_FillRect(screen, &screen->clip_rect, col[cnt % 3]);
    SDL_Flip(screen);
    SDL_Delay(1000 / 60);
  }
  SDL_Quit();
  return 0;
}

#!/bin/sh
dir=`dirname $0`
cd $dir

killall updateui
killall keymon
LD_LIBRARY_PATH=/usr/trimui/lib ./main

$ arm-linux-gnueabi-gcc main.c -o main -I/usr/include/SDL /xxx/usr/trimui/lib/libSDL-1.2.so.0

$ zip TrimuiUpdateV9999_tearing.zip updater main

LCD TE		NC
LCD RESET	4.7K RC
LCD K		N-CHANNEL MOSFET D (AO3416 AE9T)
LCD A		90416 PIN-6
LCD D0		PD3
LCD D1		PD4
LCD D2		PD5
LCD D3		PD6
LCD D4		PD7
LCD D5		PD8
LCD CS		PD11
LCD SCL		PD9
LCD DCLK	PD18
LCD HS		PD20
LCD VS		PD21
LCD SDA		PD10

0x00FE
0x00EF
0x0036
0x0140
0x003A
0x0155
0x0084
0x0104
0x0086
0x01FB
0x0087
0x0179
0x0089
0x010B
0x008A
0x0120
0x008B
0x0180
0x008D
0x013B
0x008E
0x01CF
0x00EC
0x0133
0x0102
0x014C
0x0098
0x013E
0x009C
0x014B
0x0099
0x013E
0x009D
0x014B
0x009B
0x0155
0x00E8
0x0111
0x0100
0x00FF
0x0162
0x00C3
0x0120
0x00C4
0x0103
0x00C9
0x010A
0x003A
0x0155
0x0084
0x0161
0x008A
0x0140
0x00F6
0x01C7
0x00B0
0x0163
0x00B5
0x0102
0x0102
0x0114
0x00F0
0x014A
0x0110
0x010A
0x010A
0x0126
0x0139
0x00F2
0x014A
0x0110
0x010A
0x010A
0x0126
0x0139
0x00F1
0x0150
0x018F
0x01AF
0x013B
0x013F
0x017F
0x00F3
0x0150
0x018F
0x01AF
0x013B
0x013F
0x017F
0x00BA
0x010A
0x0035
0x0100
0x0021
0x00FE
0x00EE
0x0011
0x0029
0x002C

GCC: (OpenWrt/Linaro GCC 6.4-2017.11 2017-11) 6.4.1

Unix path: /home/<username>/Work/<username>/F1C100S_TINA/out/violin-F1C200s/compile_dir/toolchain/glibc-2.23-final/csu/abi-note.o

/*
 * driver/fb-f1c500s.c
 *
 * Copyright(c) 2007-2021 Jianjun Jiang <8192542@qq.com>
 * Official site: http://xboot.org
 * Mobile phone: +86-18665388956
 * QQ: 8192542
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */
 
#include <xboot.h>
#include <dma/dma.h>
#include <clk/clk.h>
#include <reset/reset.h>
#include <gpio/gpio.h>
#include <led/led.h>
#include <interrupt/interrupt.h>
#include <framebuffer/framebuffer.h>
#include <f1c500s-gpio.h>
#include <f1c500s/reg-tcon.h>
#include <f1c500s/reg-debe.h>
#include <f1c500s/reg-defe.h>
 
#define F1C500S_GPIO_BASE   (0x01c20800)
#define F1C500S_GPIOD_CFG0  ((3 * 0x24) + 0x00)
#define F1C500S_GPIOD_DATA  ((3 * 0x24) + 0x10)
 
struct fb_f1c500s_pdata_t
{
    virtual_addr_t virtdefe;
    virtual_addr_t virtdebe;
    virtual_addr_t virttcon;
    virtual_addr_t virtgpio;
 
    char * clkdefe;
    char * clkdebe;
    char * clktcon;
    int rstdefe;
    int rstdebe;
    int rsttcon;
    int width;
    int height;
    int pwidth;
    int pheight;
    int bits_per_pixel;
    int bytes_per_pixel;
    int pixlen;
    int index;
    void * vram[2];
    struct region_list_t * nrl, * orl;
 
    struct {
        int pixel_clock_hz;
        int h_front_porch;
        int h_back_porch;
        int h_sync_len;
        int v_front_porch;
        int v_back_porch;
        int v_sync_len;
        int h_sync_active;
        int v_sync_active;
        int den_active;
        int clk_active;
    } timing;
 
    struct led_t * backlight;
    int brightness;
};
 
static inline void spi_9bits_write(struct fb_f1c500s_pdata_t * pdat, u32_t val)
{
  uint8_t cnt=0;
  uint32_t tmp=read32(pdat->virtgpio + F1C500S_GPIOD_DATA);
 
  tmp&= ~(1 << 11);
    write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
  for(cnt=0; cnt<9; cnt++){
    tmp&= ~(1 << 10);
    if(val & 0x100){
      tmp|= (1 << 10);
    }
    val<<= 1;
     
    tmp&= ~(1 << 9);
      write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
    tmp|= (1 << 9);
      write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
  }
  tmp|= (1 << 11);
    write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
}
 
static inline void gc9308_init(struct fb_f1c500s_pdata_t * pdat)
{
  spi_9bits_write(pdat, 0x00fe);
  spi_9bits_write(pdat, 0x00ef);
  spi_9bits_write(pdat, 0x0036);
  spi_9bits_write(pdat, 0x0140);
  spi_9bits_write(pdat, 0x003a);
  spi_9bits_write(pdat, 0x0155);
  spi_9bits_write(pdat, 0x0084);
  spi_9bits_write(pdat, 0x0104);
  spi_9bits_write(pdat, 0x0086);
  spi_9bits_write(pdat, 0x01fb);
  spi_9bits_write(pdat, 0x0087);
  spi_9bits_write(pdat, 0x0179);
  spi_9bits_write(pdat, 0x0089);
  spi_9bits_write(pdat, 0x010b);
  spi_9bits_write(pdat, 0x008a);
  spi_9bits_write(pdat, 0x0120);
  spi_9bits_write(pdat, 0x008b);
  spi_9bits_write(pdat, 0x0180);
  spi_9bits_write(pdat, 0x008d);
  spi_9bits_write(pdat, 0x013b);
  spi_9bits_write(pdat, 0x008e);
  spi_9bits_write(pdat, 0x01cf);
  spi_9bits_write(pdat, 0x00ec);
  spi_9bits_write(pdat, 0x0133);
  spi_9bits_write(pdat, 0x0102);
  spi_9bits_write(pdat, 0x014c);
  spi_9bits_write(pdat, 0x0098);
  spi_9bits_write(pdat, 0x013e);
  spi_9bits_write(pdat, 0x009c);
  spi_9bits_write(pdat, 0x014b);
  spi_9bits_write(pdat, 0x0099);
  spi_9bits_write(pdat, 0x013e);
  spi_9bits_write(pdat, 0x009d);
  spi_9bits_write(pdat, 0x014b);
  spi_9bits_write(pdat, 0x009b);
  spi_9bits_write(pdat, 0x0155);
  spi_9bits_write(pdat, 0x00e8);
  spi_9bits_write(pdat, 0x0111);
  spi_9bits_write(pdat, 0x0100);
  spi_9bits_write(pdat, 0x00ff);
  spi_9bits_write(pdat, 0x0162);
  spi_9bits_write(pdat, 0x00c3);
  spi_9bits_write(pdat, 0x0120);
  spi_9bits_write(pdat, 0x00c4);
  spi_9bits_write(pdat, 0x0103);
  spi_9bits_write(pdat, 0x00c9);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x003a);
  spi_9bits_write(pdat, 0x0155);
  spi_9bits_write(pdat, 0x0084);
  spi_9bits_write(pdat, 0x0161);
  spi_9bits_write(pdat, 0x008a);
  spi_9bits_write(pdat, 0x0140);
  spi_9bits_write(pdat, 0x00f6);
  spi_9bits_write(pdat, 0x01c7);
  spi_9bits_write(pdat, 0x00b0);
  spi_9bits_write(pdat, 0x0163);
  spi_9bits_write(pdat, 0x00b5);
  spi_9bits_write(pdat, 0x0102);
  spi_9bits_write(pdat, 0x0102);
  spi_9bits_write(pdat, 0x0114);
  spi_9bits_write(pdat, 0x00f0);
  spi_9bits_write(pdat, 0x014a);
  spi_9bits_write(pdat, 0x0110);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x0126);
  spi_9bits_write(pdat, 0x0139);
  spi_9bits_write(pdat, 0x00f2);
  spi_9bits_write(pdat, 0x014a);
  spi_9bits_write(pdat, 0x0110);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x0126);
  spi_9bits_write(pdat, 0x0139);
  spi_9bits_write(pdat, 0x00f1);
  spi_9bits_write(pdat, 0x0150);
  spi_9bits_write(pdat, 0x018f);
  spi_9bits_write(pdat, 0x01af);
  spi_9bits_write(pdat, 0x013b);
  spi_9bits_write(pdat, 0x013f);
  spi_9bits_write(pdat, 0x017f);
  spi_9bits_write(pdat, 0x00f3);
  spi_9bits_write(pdat, 0x0150);
  spi_9bits_write(pdat, 0x018f);
  spi_9bits_write(pdat, 0x01af);
  spi_9bits_write(pdat, 0x013b);
  spi_9bits_write(pdat, 0x013f);
  spi_9bits_write(pdat, 0x017f);
  spi_9bits_write(pdat, 0x00ba);
  spi_9bits_write(pdat, 0x010a);
  spi_9bits_write(pdat, 0x0035);
  spi_9bits_write(pdat, 0x0100);
  spi_9bits_write(pdat, 0x0021);
  spi_9bits_write(pdat, 0x00fe);
  spi_9bits_write(pdat, 0x00ee);
  spi_9bits_write(pdat, 0x0011);
  spi_9bits_write(pdat, 0x0029);
  spi_9bits_write(pdat, 0x002c);
}
 
static inline void r61520_write(struct fb_f1c500s_pdata_t * pdat, u32_t isdat, u32_t val)
{
    u32_t tmp;
 
    tmp = (val & 0x00ff) << 1;
    tmp |= (val & 0xff00) << 2;
    tmp |= isdat ? 0x80000 : 0;
    tmp |= 0x100000;
    write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
    tmp |= 0x40000;
    write32(pdat->virtgpio + F1C500S_GPIOD_DATA, tmp);
}
 
static void r61520_write_cmd(struct fb_f1c500s_pdata_t * pdat, u32_t val)
{
    r61520_write(pdat, 0, val);
}
 
static void r61520_write_dat(struct fb_f1c500s_pdata_t * pdat, u32_t val)
{
    r61520_write(pdat, 1, val);
}
 
static inline void r61520_init(struct fb_f1c500s_pdata_t * pdat)
{
    r61520_write_cmd(pdat, 0xb0);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xb1);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xb3);
    r61520_write_dat(pdat, 0x02);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xb4);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xc0);
    r61520_write_dat(pdat, 0x07);
    r61520_write_dat(pdat, 0x4f);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x01);
    r61520_write_dat(pdat, 0x33);
 
    r61520_write_cmd(pdat, 0xc1);
    r61520_write_dat(pdat, 0x01);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x1a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x08);
 
    r61520_write_cmd(pdat, 0xc3);
    r61520_write_dat(pdat, 0x01);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x1a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x08);
 
    r61520_write_cmd(pdat, 0xc4);
    r61520_write_dat(pdat, 0x11);
    r61520_write_dat(pdat, 0x01);
    r61520_write_dat(pdat, 0x43);
    r61520_write_dat(pdat, 0x01);
 
    r61520_write_cmd(pdat, 0xc8);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x8a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x09);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x23);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x60);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xc9);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x8a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x09);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x23);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x09);
    r61520_write_dat(pdat, 0x88);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x23);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xca);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x8a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x09);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x23);
    r61520_write_dat(pdat, 0x10);
    r61520_write_dat(pdat, 0x05);
    r61520_write_dat(pdat, 0x09);
    r61520_write_dat(pdat, 0x88);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x08);
    r61520_write_dat(pdat, 0x0a);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x23);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0xd0);
    r61520_write_dat(pdat, 0x07);
    r61520_write_dat(pdat, 0xc6);
    r61520_write_dat(pdat, 0xdc);
 
    r61520_write_cmd(pdat, 0xd1);
    r61520_write_dat(pdat, 0x54);
    r61520_write_dat(pdat, 0x0d);
    r61520_write_dat(pdat, 0x02);
 
    r61520_write_cmd(pdat, 0xd2);
    r61520_write_dat(pdat, 0x63);
    r61520_write_dat(pdat, 0x24);
 
    r61520_write_cmd(pdat, 0xd4);
    r61520_write_dat(pdat, 0x63);
    r61520_write_dat(pdat, 0x24);
 
    r61520_write_cmd(pdat, 0xd8);
    r61520_write_dat(pdat, 0x07);
    r61520_write_dat(pdat, 0x07);
 
    r61520_write_cmd(pdat, 0xe0);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0x13);
 
    r61520_write_cmd(pdat, 0x20);
 
    r61520_write_cmd(pdat, 0x35);
    r61520_write_dat(pdat, 0x00);
 
    r61520_write_cmd(pdat, 0x44);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x30);
 
    r61520_write_cmd(pdat, 0x36);
    r61520_write_dat(pdat, 0xe0);
 
    r61520_write_cmd(pdat, 0x3a);
    r61520_write_dat(pdat, 0x55);
 
    r61520_write_cmd(pdat, 0x2a);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x01);
    r61520_write_dat(pdat, 0x3f);
 
    r61520_write_cmd(pdat, 0x2b);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0x00);
    r61520_write_dat(pdat, 0xef);
 
    r61520_write_cmd(pdat, 0x11);
    r61520_write_cmd(pdat, 0x29);
    r61520_write_cmd(pdat, 0x2c);
}
 
static inline void f1c500s_debe_set_mode(struct fb_f1c500s_pdata_t * pdat)
{
    struct f1c500s_debe_reg_t * debe = (struct f1c500s_debe_reg_t *)(pdat->virtdebe);
    u32_t val;
 
    val = read32((virtual_addr_t)&debe->mode);
    val |= (1 << 0);
    write32((virtual_addr_t)&debe->mode, val);
 
    write32((virtual_addr_t)&debe->disp_size, (((pdat->height) - 1) << 16) | (((pdat->width) - 1) << 0));
    write32((virtual_addr_t)&debe->layer0_size, (((pdat->height) - 1) << 16) | (((pdat->width) - 1) << 0));
    write32((virtual_addr_t)&debe->layer0_stride, ((pdat->width) << 5));
    write32((virtual_addr_t)&debe->layer0_addr_low32b, (u32_t)(pdat->vram[pdat->index]) << 3);
    write32((virtual_addr_t)&debe->layer0_addr_high4b, (u32_t)(pdat->vram[pdat->index]) >> 29);
    write32((virtual_addr_t)&debe->layer0_attr1_ctrl, 9 << 8);
 
    val = read32((virtual_addr_t)&debe->mode);
    val |= (1 << 8);
    write32((virtual_addr_t)&debe->mode, val);
 
    val = read32((virtual_addr_t)&debe->reg_ctrl);
    val |= (1 << 0);
    write32((virtual_addr_t)&debe->reg_ctrl, val);
 
    val = read32((virtual_addr_t)&debe->mode);
    val |= (1 << 1);
    write32((virtual_addr_t)&debe->mode, val);
}
 
static inline void f1c500s_debe_set_address(struct fb_f1c500s_pdata_t * pdat, void * vram)
{
    struct f1c500s_debe_reg_t * debe = (struct f1c500s_debe_reg_t *)(pdat->virtdebe);
 
    write32((virtual_addr_t)&debe->layer0_addr_low32b, (u32_t)vram << 3);
    write32((virtual_addr_t)&debe->layer0_addr_high4b, (u32_t)vram >> 29);
}
 
static inline void f1c500s_tcon_enable(struct fb_f1c500s_pdata_t * pdat)
{
    struct f1c500s_tcon_reg_t * tcon = (struct f1c500s_tcon_reg_t *)pdat->virttcon;
    u32_t val;
 
    val = read32((virtual_addr_t)&tcon->ctrl);
    val |= (1 << 31);
    write32((virtual_addr_t)&tcon->ctrl, val);
 
    val = read32((virtual_addr_t)&tcon->tcon0_cpu_intf);
    val |= (1 << 28);
    write32((virtual_addr_t)&tcon->tcon0_cpu_intf, val);
}
 
static inline void f1c500s_tcon_disable(struct fb_f1c500s_pdata_t * pdat)
{
    struct f1c500s_tcon_reg_t * tcon = (struct f1c500s_tcon_reg_t *)pdat->virttcon;
    u32_t val;
 
    write32((virtual_addr_t)&tcon->ctrl, 0);
    write32((virtual_addr_t)&tcon->int0, 0);
 
    val = read32((virtual_addr_t)&tcon->tcon0_dclk);
    val &= ~(0xf << 28);
    write32((virtual_addr_t)&tcon->tcon0_dclk, val);
 
    write32((virtual_addr_t)&tcon->tcon0_io_tristate, 0xffffffff);
    write32((virtual_addr_t)&tcon->tcon1_io_tristate, 0xffffffff);
}
 
static inline void f1c500s_tcon_set_mode(struct fb_f1c500s_pdata_t * pdat)
{
    struct f1c500s_tcon_reg_t * tcon = (struct f1c500s_tcon_reg_t *)pdat->virttcon;
    int bp, total;
    u32_t val;
 
    val = read32((virtual_addr_t)&tcon->ctrl);
    val &= ~(0x1 << 0);
    write32((virtual_addr_t)&tcon->ctrl, val);
 
    val = (pdat->timing.v_front_porch + pdat->timing.v_back_porch + pdat->timing.v_sync_len);
    write32((virtual_addr_t)&tcon->tcon0_ctrl, (1 << 31) | ((val & 0x1f) << 4));
    val = clk_get_rate(pdat->clktcon) / pdat->timing.pixel_clock_hz;
    write32((virtual_addr_t)&tcon->tcon0_dclk, (0xf << 28) | (val << 0));
    write32((virtual_addr_t)&tcon->tcon0_timing_active, ((pdat->width - 1) << 16) | ((pdat->height - 1) << 0));
 
    bp = pdat->timing.h_sync_len + pdat->timing.h_back_porch;
    total = pdat->width * 3 + pdat->timing.h_front_porch + bp;
    write32((virtual_addr_t)&tcon->tcon0_timing_h, ((total - 1) << 16) | ((bp - 1) << 0));
    bp = pdat->timing.v_sync_len + pdat->timing.v_back_porch;
    total = pdat->height + pdat->timing.v_front_porch + bp;
    write32((virtual_addr_t)&tcon->tcon0_timing_v, ((total * 2) << 16) | ((bp - 1) << 0));
    write32((virtual_addr_t)&tcon->tcon0_timing_sync, ((pdat->timing.h_sync_len - 1) << 16) | ((pdat->timing.v_sync_len - 1) << 0));
 
    write32((virtual_addr_t)&tcon->tcon0_hv_intf, (1 << 31));
    write32((virtual_addr_t)&tcon->tcon0_cpu_intf, 0);
 
    write32((virtual_addr_t)&tcon->tcon0_io_polarity, (1 << 28));
    write32((virtual_addr_t)&tcon->tcon0_io_tristate, 0);
}
 
static inline void fb_f1c500s_cfg_gpios(int base, int n, int cfg, enum gpio_pull_t pull, enum gpio_drv_t drv)
{
    for(; n > 0; n--, base++)
    {
        gpio_set_cfg(base, cfg);
        gpio_set_pull(base, pull);
        gpio_set_drv(base, drv);
    }
}
 
static inline void fb_f1c500s_init(struct fb_f1c500s_pdata_t * pdat)
{
    fb_f1c500s_cfg_gpios(F1C500S_GPIOD9, 3, 1, GPIO_PULL_NONE, GPIO_DRV_STRONG);
    write32(pdat->virtgpio + F1C500S_GPIOD_DATA, 0xffffffff);
    //r61520_init(pdat);
  gc9308_init(pdat);
    fb_f1c500s_cfg_gpios(F1C500S_GPIOD1, 7, 2, GPIO_PULL_NONE, GPIO_DRV_STRONG);
    fb_f1c500s_cfg_gpios(F1C500S_GPIOD10, 12, 2, GPIO_PULL_NONE, GPIO_DRV_STRONG);
 
    f1c500s_tcon_disable(pdat);
    f1c500s_debe_set_mode(pdat);
    f1c500s_tcon_set_mode(pdat);
    f1c500s_tcon_enable(pdat);
}
 
static void fb_setbl(struct framebuffer_t * fb, int brightness)
{
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
    led_set_brightness(pdat->backlight, brightness);
}
 
static int fb_getbl(struct framebuffer_t * fb)
{
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
    return led_get_brightness(pdat->backlight);
}
 
static struct surface_t * fb_create(struct framebuffer_t * fb)
{
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
    return surface_alloc(pdat->width, pdat->height, NULL);
}
 
static void fb_destroy(struct framebuffer_t * fb, struct surface_t * s)
{
    surface_free(s);
}
 
static void fb_present(struct framebuffer_t * fb, struct surface_t * s, struct region_list_t * rl)
{
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
    struct region_list_t * nrl = pdat->nrl;
 
    region_list_clear(nrl);
    region_list_merge(nrl, pdat->orl);
    region_list_merge(nrl, rl);
    region_list_clone(pdat->orl, rl);
 
    pdat->index = (pdat->index + 1) & 0x1;
    if(nrl->count > 0)
        present_surface(pdat->vram[pdat->index], s, nrl);
    else
        memcpy(pdat->vram[pdat->index], s->pixels, s->pixlen);
    dma_cache_sync(pdat->vram[pdat->index], pdat->pixlen, DMA_TO_DEVICE);
    f1c500s_debe_set_address(pdat, pdat->vram[pdat->index]);
}
 
static struct device_t * fb_f1c500s_probe(struct driver_t * drv, struct dtnode_t * n)
{
    struct fb_f1c500s_pdata_t * pdat;
    struct framebuffer_t * fb;
    struct device_t * dev;
    char * clkdefe = dt_read_string(n, "clock-name-defe", NULL);
    char * clkdebe = dt_read_string(n, "clock-name-debe", NULL);
    char * clktcon = dt_read_string(n, "clock-name-tcon", NULL);
    int i;
 
    if(!search_clk(clkdefe) || !search_clk(clkdebe) || !search_clk(clktcon))
        return NULL;
 
    pdat = malloc(sizeof(struct fb_f1c500s_pdata_t));
    if(!pdat)
        return NULL;
 
    fb = malloc(sizeof(struct framebuffer_t));
    if(!fb)
    {
        free(pdat);
        return NULL;
    }
 
    pdat->virtdefe = phys_to_virt(F1C500S_DEFE_BASE);
    pdat->virtdebe = phys_to_virt(F1C500S_DEBE_BASE);
    pdat->virttcon = phys_to_virt(F1C500S_TCON_BASE);
    pdat->virtgpio = phys_to_virt(F1C500S_GPIO_BASE);
    pdat->clkdefe = strdup(clkdefe);
    pdat->clkdebe = strdup(clkdebe);
    pdat->clktcon = strdup(clktcon);
    pdat->rstdefe = dt_read_int(n, "reset-defe", -1);
    pdat->rstdebe = dt_read_int(n, "reset-debe", -1);
    pdat->rsttcon = dt_read_int(n, "reset-tcon", -1);
    pdat->width = dt_read_int(n, "width", 320);
    pdat->height = dt_read_int(n, "height", 240);
    pdat->pwidth = dt_read_int(n, "physical-width", 216);
    pdat->pheight = dt_read_int(n, "physical-height", 135);
    pdat->bits_per_pixel = 18;
    pdat->bytes_per_pixel = 4;
    pdat->pixlen = pdat->width * pdat->height * pdat->bytes_per_pixel;
    pdat->index = 0;
    pdat->vram[0] = dma_alloc_noncoherent(pdat->pixlen);
    pdat->vram[1] = dma_alloc_noncoherent(pdat->pixlen);
    pdat->nrl = region_list_alloc(0);
    pdat->orl = region_list_alloc(0);
 
    pdat->timing.pixel_clock_hz = dt_read_long(n, "clock-frequency", 8000000);
    pdat->timing.h_front_porch = dt_read_int(n, "hfront-porch", 40);
    pdat->timing.h_back_porch = dt_read_int(n, "hback-porch", 87);
    pdat->timing.h_sync_len = dt_read_int(n, "hsync-len", 1);
    pdat->timing.v_front_porch = dt_read_int(n, "vfront-porch", 13);
    pdat->timing.v_back_porch = dt_read_int(n, "vback-porch", 31);
    pdat->timing.v_sync_len = dt_read_int(n, "vsync-len", 1);
    pdat->timing.h_sync_active = dt_read_bool(n, "hsync-active", 0);
    pdat->timing.v_sync_active = dt_read_bool(n, "vsync-active", 0);
    pdat->timing.den_active = dt_read_bool(n, "den-active", 0);
    pdat->timing.clk_active = dt_read_bool(n, "clk-active", 0);
    pdat->backlight = search_led(dt_read_string(n, "backlight", NULL));
 
    fb->name = alloc_device_name(dt_read_name(n), dt_read_id(n));
    fb->width = pdat->width;
    fb->height = pdat->height;
    fb->pwidth = pdat->pwidth;
    fb->pheight = pdat->pheight;
    fb->setbl = fb_setbl;
    fb->getbl = fb_getbl;
    fb->create = fb_create;
    fb->destroy = fb_destroy;
    fb->present = fb_present;
    fb->priv = pdat;
 
    clk_enable(pdat->clkdefe);
    clk_enable(pdat->clkdebe);
    clk_enable(pdat->clktcon);
    if(pdat->rstdefe >= 0)
        reset_deassert(pdat->rstdefe);
    if(pdat->rstdebe >= 0)
        reset_deassert(pdat->rstdebe);
    if(pdat->rsttcon >= 0)
        reset_deassert(pdat->rsttcon);
    for(i = 0x0800; i < 0x1000; i += 4)
        write32(pdat->virtdebe + i, 0);
    fb_f1c500s_init(pdat);
 
    if(!(dev = register_framebuffer(fb, drv)))
    {
        clk_disable(pdat->clkdefe);
        clk_disable(pdat->clkdebe);
        clk_disable(pdat->clktcon);
        free(pdat->clkdefe);
        free(pdat->clkdebe);
        free(pdat->clktcon);
        dma_free_noncoherent(pdat->vram[0]);
        dma_free_noncoherent(pdat->vram[1]);
        region_list_free(pdat->nrl);
        region_list_free(pdat->orl);
        free_device_name(fb->name);
        free(fb->priv);
        free(fb);
        return NULL;
    }
    return dev;
}
 
static void fb_f1c500s_remove(struct device_t * dev)
{
    struct framebuffer_t * fb = (struct framebuffer_t *)dev->priv;
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
 
    if(fb)
    {
        unregister_framebuffer(fb);
        clk_disable(pdat->clkdefe);
        clk_disable(pdat->clkdebe);
        clk_disable(pdat->clktcon);
        free(pdat->clkdefe);
        free(pdat->clkdebe);
        free(pdat->clktcon);
        dma_free_noncoherent(pdat->vram[0]);
        dma_free_noncoherent(pdat->vram[1]);
        region_list_free(pdat->nrl);
        region_list_free(pdat->orl);
        free_device_name(fb->name);
        free(fb->priv);
        free(fb);
    }
}
 
static void fb_f1c500s_suspend(struct device_t * dev)
{
    struct framebuffer_t * fb = (struct framebuffer_t *)dev->priv;
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
 
    pdat->brightness = led_get_brightness(pdat->backlight);
    led_set_brightness(pdat->backlight, 0);
}
 
static void fb_f1c500s_resume(struct device_t * dev)
{
    struct framebuffer_t * fb = (struct framebuffer_t *)dev->priv;
    struct fb_f1c500s_pdata_t * pdat = (struct fb_f1c500s_pdata_t *)fb->priv;
 
    led_set_brightness(pdat->backlight, pdat->brightness);
}
 
static struct driver_t fb_f1c500s = {
    .name       = "fb-f1c500s",
    .probe      = fb_f1c500s_probe,
    .remove     = fb_f1c500s_remove,
    .suspend    = fb_f1c500s_suspend,
    .resume     = fb_f1c500s_resume,
};
 
static __init void fb_f1c500s_driver_init(void)
{
    register_driver(&fb_f1c500s);
}
 
static __exit void fb_f1c500s_driver_exit(void)
{
    unregister_driver(&fb_f1c500s);
}
 
driver_initcall(fb_f1c500s_driver_init);
driver_exitcall(fb_f1c500s_driver_exit);

  "fb-f1c500s@0": {
    "clock-name-defe": "link-defe",
    "clock-name-debe": "link-debe",
    "clock-name-tcon": "link-tcon",
    "reset-defe": 46, 
    "reset-debe": 44, 
    "reset-tcon": 36, 
    "width": 320,
    "height": 240,
    "physical-width": 216,
    "physical-height": 135,
    "clock-frequency": 18000000,
    "hfront-porch": 32, 
    "hback-porch": 20, 
    "hsync-len": 10, 
    "vfront-porch": 1,
    "vback-porch": 1,
    "vsync-len": 10, 
    "hsync-active": false,
    "vsync-active": false,
    "den-active": true,
    "clk-active": true,
    "backlight": "led-pwm-bl.0"
  },

UP			PA0
DOWN			PE2
LEFT			PE4
RIGHT			PE8
A			PD19
B			PD12
X			PD2
Y			PD17
L			PD0
R			PD1
SELECT			PD14
MENU			PE11
START			PD13
LED RED			PE5
LED BLUE		+3.3v
SPI FLASH CS		PC1
SPI FLASH DO		PC2
SPI FLASH DI		PC3
SPI FLASH CLK		PC0
LCD TE			NC
LCD RESET		4.7K RC
LCD BL			PE6
LCD D0			PD3
LCD D1			PD4
LCD D2			PD5
LCD D3			PD6
LCD D4			PD7
LCD D5			PD8
LCD CS			PD11
LCD SCL			PD9
LCD DCLK		PD18
LCD HS			PD20
LCD VS			PD21
LCD SDA			PD10
MicroSD D0		PF1
MicroSD D1		PF0
MicroSD D2		PF5
MicroSD D3		PF4
MicroSD CLK		PF2
MicroSD CMD		PF3
MicroSD CD		PE4

0x0000: 0x80000000
0x0004: 0x80000000
0x0008: 0x00000000
0x000c: 0x00000000
0x0010: 0x80000000
0x0014: 0x00000001
0x0018: 0x00000003
0x001c: 0x00000005
0x0020: 0x00000007
0x0024: 0x0000000b
0x0028: 0x0000000d
0x002c: 0x01010000
0x0030: 0x15151111
0x0034: 0x57575555
0x0038: 0x7f7f7777
0x003c: 0x00000000
0x0040: 0x800001f0
0x0044: 0xf000000f
0x0048: 0x013f00ef
0x004c: 0x04640025
0x0050: 0x023c0005
0x0054: 0x00110003
0x0058: 0x80000000
0x005c: 0x00000000
0x0060: 0x00000000
0x0064: 0x00000000
0x0068: 0x00000000
0x006c: 0x00000000
0x0070: 0x00000000
0x0074: 0x00000000
0x0078: 0x00000000
0x007c: 0x00000000
0x0080: 0x00000000
0x0084: 0x00000000
0x0088: 0x00000000
0x008c: 0xe0000000
0x0090: 0x00000000
0x0094: 0x00000000
0x0098: 0x00000000
0x009c: 0x00000000
0x00a0: 0x00000000
0x00a4: 0x00000000
0x00a8: 0x00000000
0x00ac: 0x00000000
0x00b0: 0x00000000
0x00b4: 0x00000000
0x00b8: 0x00000000
0x00bc: 0x00000000
0x00c0: 0x00000000
0x00c4: 0x00000000
0x00c8: 0x00000000
0x00cc: 0x00000000
0x00d0: 0x00000000
0x00d4: 0x00000000
0x00d8: 0x00000000
0x00dc: 0x00000000
0x00e0: 0x00000000
0x00e4: 0x00000000
0x00e8: 0x00000000
0x00ec: 0x00000000
0x00f0: 0x00000000
0x00f4: 0xffffffff
0x00f8: 0x00000000
0x00fc: 0x10f10000

0x0000: 0x00000000
0x0004: 0x00000000
0x0008: 0x00000000
0x000c: 0x00000000
0x0010: 0x00000000
0x0014: 0x00000000
0x0018: 0x00000000
0x001c: 0x16190478
0x0020: 0x00000000
0x0024: 0x00000000
0x0028: 0x00000000
0x002c: 0x00000000
0x0030: 0x00000000
0x0034: 0x00000000
0x0038: 0x00000000
0x003c: 0x20101013
0x0040: 0x00000000
0x0044: 0x00000000
0x0048: 0x00000000
0x004c: 0x00000000
0x0050: 0x00000000
0x0054: 0x00000000
0x0058: 0x00000000
0x005c: 0x00000000
0x0060: 0x00000000
0x0064: 0x00000000
0x0068: 0x00000000
0x006c: 0x00000000
0x0070: 0x00000000
0x0074: 0x00000000
0x0078: 0x00000000
0x007c: 0x00000000
0x0080: 0x00000000
0x0084: 0x00000000
0x0088: 0x00000000
0x008c: 0x00000000
0x0090: 0x00000000
0x0094: 0x00000000
0x0098: 0x00000000
0x009c: 0x00000000
0x00a0: 0x00000000
0x00a4: 0x00000000
0x00a8: 0x00000000
0x00ac: 0x00000000
0x00b0: 0x00000000
0x00b4: 0x00000000
0x00b8: 0x00000000
0x00bc: 0x00000000
0x00c0: 0x00000000
0x00c4: 0x00000000
0x00c8: 0x00000000
0x00cc: 0x00000000
0x00d0: 0x00000000
0x00d4: 0x00000000
0x00d8: 0x00000000
0x00dc: 0x00000000
0x00e0: 0x00000000
0x00e4: 0x00000000
0x00e8: 0x00000000
0x00ec: 0x00000000
0x00f0: 0x00000000
0x00f4: 0x00000000
0x00f8: 0x00000000
0x00fc: 0x00000000

0x0800: 0x00000803
0x0804: 0x00000000
0x0808: 0x00ef013f
0x080c: 0x00000000
0x0810: 0xffffffff
0x0814: 0xffffffff
0x0818: 0xffffffff
0x081c: 0x00ef013f
0x0820: 0x00000000
0x0824: 0x00000000
0x0828: 0x00000000
0x082c: 0x00000000
0x0830: 0x00000000
0x0834: 0x00000000
0x0838: 0x00000000
0x083c: 0x00000000
0x0840: 0x00000000
0x0844: 0x00000000
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0x1e04: 0x00000000
0x1e08: 0x00000000
0x1e0c: 0x00000000
0x1e10: 0x00000000
0x1e14: 0x00000000
0x1e18: 0x00000000
0x1e1c: 0x00000000
0x1e20: 0x00000000
0x1e24: 0x00000000
0x1e28: 0x00000000
0x1e2c: 0x00000000
0x1e30: 0x00000000
0x1e34: 0x00000000
0x1e38: 0x00000000
0x1e3c: 0x00000000
0x1e40: 0x00000000
0x1e44: 0x00000000
0x1e48: 0x00000000
0x1e4c: 0x00000000
0x1e50: 0x00000000
0x1e54: 0x00000000
0x1e58: 0x00000000
0x1e5c: 0x00000000
0x1e60: 0x00000000
0x1e64: 0x00000000
0x1e68: 0x00000000
0x1e6c: 0x00000000
0x1e70: 0x00000000
0x1e74: 0x00000000
0x1e78: 0x00000000
0x1e7c: 0x00000000
0x1e80: 0x00000000
0x1e84: 0x00000000
0x1e88: 0x00000000
0x1e8c: 0x00000000
0x1e90: 0x00000000
0x1e94: 0x00000000
0x1e98: 0x00000000
0x1e9c: 0x00000000
0x1ea0: 0x00000000
0x1ea4: 0x00000000
0x1ea8: 0x00000000
0x1eac: 0x00000000
0x1eb0: 0x00000000
0x1eb4: 0x00000000
0x1eb8: 0x00000000
0x1ebc: 0x00000000
0x1ec0: 0x00000000
0x1ec4: 0x00000000
0x1ec8: 0x00000000
0x1ecc: 0x00000000
0x1ed0: 0x00000000
0x1ed4: 0x00000000
0x1ed8: 0x00000000
0x1edc: 0x00000000
0x1ee0: 0x00000000
0x1ee4: 0x00000000
0x1ee8: 0x00000000
0x1eec: 0x00000000
0x1ef0: 0x00000000
0x1ef4: 0x00000000
0x1ef8: 0x00000000
0x1efc: 0x00000000
0x1f00: 0x00000000
0x1f04: 0x00000000
0x1f08: 0x00000000
0x1f0c: 0x00000000
0x1f10: 0x00000000
0x1f14: 0x00000000
0x1f18: 0x00000000
0x1f1c: 0x00000000
0x1f20: 0x00000000
0x1f24: 0x00000000
0x1f28: 0x00000000
0x1f2c: 0x00000000
0x1f30: 0x00000000
0x1f34: 0x00000000
0x1f38: 0x00000000
0x1f3c: 0x00000000
0x1f40: 0x00000000
0x1f44: 0x00000000
0x1f48: 0x00000000
0x1f4c: 0x00000000
0x1f50: 0x00000000
0x1f54: 0x00000000
0x1f58: 0x00000000
0x1f5c: 0x00000000
0x1f60: 0x00000000
0x1f64: 0x00000000
0x1f68: 0x00000000
0x1f6c: 0x00000000
0x1f70: 0x00000000
0x1f74: 0x00000000
0x1f78: 0x00000000
0x1f7c: 0x00000000
0x1f80: 0x00000000
0x1f84: 0x00000000
0x1f88: 0x00000000
0x1f8c: 0x00000000
0x1f90: 0x00000000
0x1f94: 0x00000000
0x1f98: 0x00000000
0x1f9c: 0x00000000
0x1fa0: 0x00000000
0x1fa4: 0x00000000
0x1fa8: 0x00000000
0x1fac: 0x00000000
0x1fb0: 0x00000000
0x1fb4: 0x00000000
0x1fb8: 0x00000000
0x1fbc: 0x00000000
0x1fc0: 0x00000000
0x1fc4: 0x00000000
0x1fc8: 0x00000000
0x1fcc: 0x00000000
0x1fd0: 0x00000000
0x1fd4: 0x00000000
0x1fd8: 0x00000000
0x1fdc: 0x00000000
0x1fe0: 0x00000000
0x1fe4: 0x00000000
0x1fe8: 0x00000000
0x1fec: 0x00000000
0x1ff0: 0x00000000
0x1ff4: 0x00000000
0x1ff8: 0x00000000
0x1ffc: 0x00000000

GPIOs 0-191, platform/pio, pio:
 gpio-0   (GPIO Key Up         ) in  hi
 gpio-96  (GPIO Key L          ) in  hi
 gpio-97  (GPIO Key R          ) in  hi
 gpio-98  (GPIO Key X          ) in  hi
 gpio-108 (GPIO Key B          ) in  hi
 gpio-109 (GPIO Key START      ) in  hi
 gpio-110 (GPIO Key SELECT     ) in  hi
 gpio-111 (alpu_scl            ) out hi
 gpio-112 (alpu_sda            ) out hi
 gpio-113 (GPIO Key A          ) in  hi
 gpio-115 (GPIO Key Y          ) in  hi
 gpio-129 (lcd_reset           ) out hi
 gpio-130 (GPIO Key Down       ) in  hi
 gpio-131 (sdc0 cd             ) in  hi
 gpio-132 (GPIO Key Left       ) in  hi
 gpio-134 (?                   ) in  hi
 gpio-135 (otg_det             ) in  lo
 gpio-136 (GPIO Key Right      ) in  hi
 gpio-137 (otg_id              ) in  hi
 gpio-139 (GPIO Key MENU       ) in  hi

platform/1c21000.pwm, 2 PWM devices
 pwm-0   ((null)              ):
 pwm-1   (lcd                 ): requested enabled

Requested pin control handlers their pinmux maps:
device: pio current state: none
device: twi0 current state: default
  state: default
    type: MUX_GROUP controller pio group: PD12 (24) function: twi0 (19)
    type: CONFIGS_GROUP controller pio group PD12 (24) 00000000 00000000 00000000
    type: MUX_GROUP controller pio group: PD0 (12) function: twi0 (19)
    type: CONFIGS_GROUP controller pio group PD0 (12) 00000000 00000000 00000000
  state: sleep
    type: MUX_GROUP controller pio group: PD12 (24) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PD12 (24) 00140009 00000005
    type: MUX_GROUP controller pio group: PD0 (12) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PD0 (12) 00140009 00000005
device: uart1 current state: default
  state: default
    type: MUX_GROUP controller pio group: PA2 (2) function: uart1 (4)
    type: CONFIGS_GROUP controller pio group PA2 (2) 00000003 00000000 00000000
    type: MUX_GROUP controller pio group: PA3 (3) function: uart1 (4)
    type: CONFIGS_GROUP controller pio group PA3 (3) 00000003 00000000 00000000
  state: sleep
    type: MUX_GROUP controller pio group: PA3 (3) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PA3 (3) 00140009 00000003
    type: MUX_GROUP controller pio group: PA2 (2) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PA2 (2) 00140009 00000003
device: spinand current state: default
  state: default
    type: MUX_GROUP controller pio group: PC1 (9) function: spi0 (14)
    type: CONFIGS_GROUP controller pio group PC1 (9) 00000003 00000000 00000000
    type: MUX_GROUP controller pio group: PC0 (8) function: spi0 (14)
    type: CONFIGS_GROUP controller pio group PC0 (8) 00000000 00000000 00000000
    type: MUX_GROUP controller pio group: PC3 (11) function: spi0 (14)
    type: CONFIGS_GROUP controller pio group PC3 (11) 00000000 00000000 00000000
    type: MUX_GROUP controller pio group: PC2 (10) function: spi0 (14)
    type: CONFIGS_GROUP controller pio group PC2 (10) 00000000 00000000 00000000
  state: sleep
    type: MUX_GROUP controller pio group: PC0 (8) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PC0 (8) 00140009 00000005
    type: MUX_GROUP controller pio group: PC1 (9) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PC1 (9) 00140009 00000005
    type: MUX_GROUP controller pio group: PC2 (10) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PC2 (10) 00140009 00000005
    type: MUX_GROUP controller pio group: PC3 (11) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PC3 (11) 00140009 00000005
device: sdc0 current state: sleep
  state: default
    type: MUX_GROUP controller pio group: PF0 (47) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF0 (47) 00280009 00000003 00000000
    type: MUX_GROUP controller pio group: PF1 (48) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF1 (48) 00280009 00000003 00000000
    type: MUX_GROUP controller pio group: PF2 (49) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF2 (49) 00280009 00000003 00000000
    type: MUX_GROUP controller pio group: PF3 (50) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF3 (50) 00280009 00000003 00000000
    type: MUX_GROUP controller pio group: PF4 (51) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF4 (51) 00280009 00000003 00000000
    type: MUX_GROUP controller pio group: PF5 (52) function: sdc0 (29)
    type: CONFIGS_GROUP controller pio group PF5 (52) 00280009 00000003 00000000
  state: sleep
    type: MUX_GROUP controller pio group: PF0 (47) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF0 (47) 00140009 00000003
    type: MUX_GROUP controller pio group: PF1 (48) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF1 (48) 00140009 00000003
    type: MUX_GROUP controller pio group: PF2 (49) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF2 (49) 00140009 00000003
    type: MUX_GROUP controller pio group: PF3 (50) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF3 (50) 00140009 00000003
    type: MUX_GROUP controller pio group: PF4 (51) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF4 (51) 00140009 00000003
    type: MUX_GROUP controller pio group: PF5 (52) function: io_disabled (6)
    type: CONFIGS_GROUP controller pio group PF5 (52) 00140009 00000003
device: lcd0 current state: active
  state: active
    type: MUX_GROUP controller pio group: PD3 (15) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD3 (15) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD4 (16) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD4 (16) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD5 (17) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD5 (17) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD6 (18) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD6 (18) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD7 (19) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD7 (19) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD8 (20) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD8 (20) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD18 (30) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD18 (30) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD20 (32) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD20 (32) 00000005 00000000 00000000
    type: MUX_GROUP controller pio group: PD21 (33) function: lcd0 (18)
    type: CONFIGS_GROUP controller pio group PD21 (33) 00000005 00000000 00000000

Pinctrl maps:
device twi0
state default
type MUX_GROUP (2)
controlling device pio
group PD12
function twi0

device twi0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PD12
config 00000000
config 00000000
config 00000000

device twi0
state default
type MUX_GROUP (2)
controlling device pio
group PD0
function twi0

device twi0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PD0
config 00000000
config 00000000
config 00000000

device twi0
state sleep
type MUX_GROUP (2)
controlling device pio
group PD12
function io_disabled

device twi0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PD12
config 00140009
config 00000005

device twi0
state sleep
type MUX_GROUP (2)
controlling device pio
group PD0
function io_disabled

device twi0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PD0
config 00140009
config 00000005

device uart1
state default
type MUX_GROUP (2)
controlling device pio
group PA2
function uart1

device uart1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PA2
config 00000003
config 00000000
config 00000000

device uart1
state default
type MUX_GROUP (2)
controlling device pio
group PA3
function uart1

device uart1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PA3
config 00000003
config 00000000
config 00000000

device uart1
state sleep
type MUX_GROUP (2)
controlling device pio
group PA3
function io_disabled

device uart1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PA3
config 00140009
config 00000003

device uart1
state sleep
type MUX_GROUP (2)
controlling device pio
group PA2
function io_disabled

device uart1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PA2
config 00140009
config 00000003

device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC1
function spi0

device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC1
config 00000003
config 00000000
config 00000000

device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC0
function spi0

device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC0
config 00000000
config 00000000
config 00000000

device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC3
function spi0

device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC3
config 00000000
config 00000000
config 00000000

device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC2
function spi0

device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC2
config 00000000
config 00000000
config 00000000

device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC0
function io_disabled

device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC0
config 00140009
config 00000005

device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC1
function io_disabled

device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC1
config 00140009
config 00000005

device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC2
function io_disabled

device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC2
config 00140009
config 00000005

device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC3
function io_disabled

device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC3
config 00140009
config 00000005

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF0
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF0
config 00280009
config 00000003
config 00000000

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF1
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF1
config 00280009
config 00000003
config 00000000

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF2
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF2
config 00280009
config 00000003
config 00000000

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF3
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF3
config 00280009
config 00000003
config 00000000

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF4
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF4
config 00280009
config 00000003
config 00000000

device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF5
function sdc0

device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF5
config 00280009
config 00000003
config 00000000

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF0
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF0
config 00140009
config 00000003

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF1
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF1
config 00140009
config 00000003

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF2
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF2
config 00140009
config 00000003

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF3
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF3
config 00140009
config 00000003

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF4
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF4
config 00140009
config 00000003

device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF5
function io_disabled

device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF5
config 00140009
config 00000003

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD3
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD3
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD4
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD4
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD5
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD5
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD6
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD6
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD7
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD7
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD8
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD8
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD18
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD18
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD20
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD20
config 00000005
config 00000000
config 00000000

device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD21
function lcd0

device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD21
config 00000005
config 00000000
config 00000000

GPIO ranges handled:
0: pio GPIOS [0 - 0] PINS [0 - 0]
1: pio GPIOS [1 - 1] PINS [1 - 1]
2: pio GPIOS [2 - 2] PINS [2 - 2]
3: pio GPIOS [3 - 3] PINS [3 - 3]
32: pio GPIOS [32 - 32] PINS [32 - 32]
33: pio GPIOS [33 - 33] PINS [33 - 33]
34: pio GPIOS [34 - 34] PINS [34 - 34]
35: pio GPIOS [35 - 35] PINS [35 - 35]
64: pio GPIOS [64 - 64] PINS [64 - 64]
65: pio GPIOS [65 - 65] PINS [65 - 65]
66: pio GPIOS [66 - 66] PINS [66 - 66]
67: pio GPIOS [67 - 67] PINS [67 - 67]
96: pio GPIOS [96 - 96] PINS [96 - 96]
97: pio GPIOS [97 - 97] PINS [97 - 97]
98: pio GPIOS [98 - 98] PINS [98 - 98]
99: pio GPIOS [99 - 99] PINS [99 - 99]
100: pio GPIOS [100 - 100] PINS [100 - 100]
101: pio GPIOS [101 - 101] PINS [101 - 101]
102: pio GPIOS [102 - 102] PINS [102 - 102]
103: pio GPIOS [103 - 103] PINS [103 - 103]
104: pio GPIOS [104 - 104] PINS [104 - 104]
105: pio GPIOS [105 - 105] PINS [105 - 105]
106: pio GPIOS [106 - 106] PINS [106 - 106]
107: pio GPIOS [107 - 107] PINS [107 - 107]
108: pio GPIOS [108 - 108] PINS [108 - 108]
109: pio GPIOS [109 - 109] PINS [109 - 109]
110: pio GPIOS [110 - 110] PINS [110 - 110]
111: pio GPIOS [111 - 111] PINS [111 - 111]
112: pio GPIOS [112 - 112] PINS [112 - 112]
113: pio GPIOS [113 - 113] PINS [113 - 113]
114: pio GPIOS [114 - 114] PINS [114 - 114]
115: pio GPIOS [115 - 115] PINS [115 - 115]
116: pio GPIOS [116 - 116] PINS [116 - 116]
117: pio GPIOS [117 - 117] PINS [117 - 117]
128: pio GPIOS [128 - 128] PINS [128 - 128]
129: pio GPIOS [129 - 129] PINS [129 - 129]
130: pio GPIOS [130 - 130] PINS [130 - 130]
131: pio GPIOS [131 - 131] PINS [131 - 131]
132: pio GPIOS [132 - 132] PINS [132 - 132]
133: pio GPIOS [133 - 133] PINS [133 - 133]
134: pio GPIOS [134 - 134] PINS [134 - 134]
135: pio GPIOS [135 - 135] PINS [135 - 135]
136: pio GPIOS [136 - 136] PINS [136 - 136]
137: pio GPIOS [137 - 137] PINS [137 - 137]
138: pio GPIOS [138 - 138] PINS [138 - 138]
139: pio GPIOS [139 - 139] PINS [139 - 139]
140: pio GPIOS [140 - 140] PINS [140 - 140]
160: pio GPIOS [160 - 160] PINS [160 - 160]
161: pio GPIOS [161 - 161] PINS [161 - 161]
162: pio GPIOS [162 - 162] PINS [162 - 162]
163: pio GPIOS [163 - 163] PINS [163 - 163]
164: pio GPIOS [164 - 164] PINS [164 - 164]
165: pio GPIOS [165 - 165] PINS [165 - 165]
No config found for dev/state/pin, expected:
Searched dev:
Searched state:
Searched pin:
Use: modify config_pin <devname> <state> <pinname> <value>
Pin config settings per pin group
Format: group (name): configs
0 (PA0):
1 (PA1):
2 (PA2):
3 (PA3):
4 (PB0):
5 (PB1):
6 (PB2):
7 (PB3):
8 (PC0):
9 (PC1):
10 (PC2):
11 (PC3):
12 (PD0):
13 (PD1):
14 (PD2):
15 (PD3):
16 (PD4):
17 (PD5):
18 (PD6):
19 (PD7):
20 (PD8):
21 (PD9):
22 (PD10):
23 (PD11):
24 (PD12):
25 (PD13):
26 (PD14):
27 (PD15):
28 (PD16):
29 (PD17):
30 (PD18):
31 (PD19):
32 (PD20):
33 (PD21):
34 (PE0):
35 (PE1):
36 (PE2):
37 (PE3):
38 (PE4):
39 (PE5):
40 (PE6):
41 (PE7):
42 (PE8):
43 (PE9):
44 (PE10):
45 (PE11):
46 (PE12):
47 (PF0):
48 (PF1):
49 (PF2):
50 (PF3):
51 (PF4):
52 (PF5):
Pin config settings per pin
Format: pin (name): configs
pin 0 (PA0):
pin 1 (PA1):
pin 2 (PA2):
pin 3 (PA3):
pin 32 (PB0):
pin 33 (PB1):
pin 34 (PB2):
pin 35 (PB3):
pin 64 (PC0):
pin 65 (PC1):
pin 66 (PC2):
pin 67 (PC3):
pin 96 (PD0):
pin 97 (PD1):
pin 98 (PD2):
pin 99 (PD3):
pin 100 (PD4):
pin 101 (PD5):
pin 102 (PD6):
pin 103 (PD7):
pin 104 (PD8):
pin 105 (PD9):
pin 106 (PD10):
pin 107 (PD11):
pin 108 (PD12):
pin 109 (PD13):
pin 110 (PD14):
pin 111 (PD15):
pin 112 (PD16):
pin 113 (PD17):
pin 114 (PD18):
pin 115 (PD19):
pin 116 (PD20):
pin 117 (PD21):
pin 128 (PE0):
pin 129 (PE1):
pin 130 (PE2):
pin 131 (PE3):
pin 132 (PE4):
pin 133 (PE5):
pin 134 (PE6):
pin 135 (PE7):
pin 136 (PE8):
pin 137 (PE9):
pin 138 (PE10):
pin 139 (PE11):
pin 140 (PE12):
pin 160 (PF0):
pin 161 (PF1):
pin 162 (PF2):
pin 163 (PF3):
pin 164 (PF4):
pin 165 (PF5):
registered pin groups:
group: PA0
pin 0 (PA0)

group: PA1
pin 1 (PA1)

group: PA2
pin 2 (PA2)

group: PA3
pin 3 (PA3)

group: PB0
pin 32 (PB0)

group: PB1
pin 33 (PB1)

group: PB2
pin 34 (PB2)

group: PB3
pin 35 (PB3)

group: PC0
pin 64 (PC0)

group: PC1
pin 65 (PC1)

group: PC2
pin 66 (PC2)

group: PC3
pin 67 (PC3)

group: PD0
pin 96 (PD0)

group: PD1
pin 97 (PD1)

group: PD2
pin 98 (PD2)

group: PD3
pin 99 (PD3)

group: PD4
pin 100 (PD4)

group: PD5
pin 101 (PD5)

group: PD6
pin 102 (PD6)

group: PD7
pin 103 (PD7)

group: PD8
pin 104 (PD8)

group: PD9
pin 105 (PD9)

group: PD10
pin 106 (PD10)

group: PD11
pin 107 (PD11)

group: PD12
pin 108 (PD12)

group: PD13
pin 109 (PD13)

group: PD14
pin 110 (PD14)

group: PD15
pin 111 (PD15)

group: PD16
pin 112 (PD16)

group: PD17
pin 113 (PD17)

group: PD18
pin 114 (PD18)

group: PD19
pin 115 (PD19)

group: PD20
pin 116 (PD20)

group: PD21
pin 117 (PD21)

group: PE0
pin 128 (PE0)

group: PE1
pin 129 (PE1)

group: PE2
pin 130 (PE2)

group: PE3
pin 131 (PE3)

group: PE4
pin 132 (PE4)

group: PE5
pin 133 (PE5)

group: PE6
pin 134 (PE6)

group: PE7
pin 135 (PE7)

group: PE8
pin 136 (PE8)

group: PE9
pin 137 (PE9)

group: PE10
pin 138 (PE10)

group: PE11
pin 139 (PE11)

group: PE12
pin 140 (PE12)

group: PF0
pin 160 (PF0)

group: PF1
pin 161 (PF1)

group: PF2
pin 162 (PF2)

group: PF3
pin 163 (PF3)

group: PF4
pin 164 (PF4)

group: PF5
pin 165 (PF5)

function: gpio_in, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PE0 PE1 PE2 PE3 PE4 PE5 PE6 ]
function: gpio_out, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PE0 PE1 PE2 PE3 PE4 PE5]
function: tp0, groups = [ PA0 PA1 PA2 PA3 ]
function: da0, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PD7 PD8 PD9 PD10 PD11 PE3 PE4 PE5 PE6 PE12 ]
function: uart1, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PD1 PD2 PD3 PD4 ]
function: spi1, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PE7 PE8 PE9 PE10 ]
function: io_disabled, groups = [ PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PE0 PE1 PE2 PE3 PE4 ]
function: pwm0, groups = [ PA2 PB2 PE12 ]
function: ir0, groups = [ PA3 PB3 PE11 PF0 ]
function: dqs0, groups = [ PB0 ]
function: twi1, groups = [ PB0 PB1 PD5 PD6 ]
function: dqs1, groups = [ PB1 ]
function: ckb, groups = [ PB2 ]
function: ddr_ref_d, groups = [ PB3 ]
function: spi0, groups = [ PC0 PC1 PC2 PC3 PD18 PD19 PD20 PD21 ]
function: sdc1, groups = [ PC0 PC1 PC2 ]
function: vdevice, groups = [ PC0 PC1 ]
function: uart0, groups = [ PC3 PE0 PE1 PF2 PF4 ]
function: lcd0, groups = [ PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PE0 PE1 PE2 PE3 PE4 PE5 ]
function: twi0, groups = [ PD0 PD12 PE11 PE12 ]
function: rsb0, groups = [ PD0 PD12 PE3 PE4 ]
function: irq, groups = [ PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PF0 PF1 PF2 PF3 PF4 P]
function: uart2, groups = [ PD13 PD15 PD16 PE7 PE8 PE9 PE10 ]
function: lvds1, groups = [ PD14 ]
function: twi2, groups = [ PD15 PD16 PE0 PE1 ]
function: spdif0, groups = [ PD17 PE6 ]
function: csi0, groups = [ PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 ]
function: clk0, groups = [ PE2 PE11 ]
function: pwm1, groups = [ PE6 ]
function: sdc0, groups = [ PF0 PF1 PF2 PF3 PF4 PF5 ]
function: dbg0, groups = [ PF0 PF3 PF5 ]
function: dgb0, groups = [ PF1 ]
function: pmw1, groups = [ PF5 ]
Pinmux settings per pin
Format: pin (name): mux_owner gpio_owner hog?
pin 0 (PA0): (MUX UNCLAIMED) pio:0
pin 1 (PA1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 2 (PA2): uart1 (GPIO UNCLAIMED) function uart1 group PA2
pin 3 (PA3): uart1 (GPIO UNCLAIMED) function uart1 group PA3
pin 32 (PB0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 33 (PB1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 34 (PB2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 35 (PB3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 64 (PC0): spinand (GPIO UNCLAIMED) function spi0 group PC0
pin 65 (PC1): spinand (GPIO UNCLAIMED) function spi0 group PC1
pin 66 (PC2): spinand (GPIO UNCLAIMED) function spi0 group PC2
pin 67 (PC3): spinand (GPIO UNCLAIMED) function spi0 group PC3
pin 96 (PD0): twi0 pio:96 function twi0 group PD0
pin 97 (PD1): (MUX UNCLAIMED) pio:97
pin 98 (PD2): (MUX UNCLAIMED) pio:98
pin 99 (PD3): lcd0 (GPIO UNCLAIMED) function lcd0 group PD3
pin 100 (PD4): lcd0 (GPIO UNCLAIMED) function lcd0 group PD4
pin 101 (PD5): lcd0 (GPIO UNCLAIMED) function lcd0 group PD5
pin 102 (PD6): lcd0 (GPIO UNCLAIMED) function lcd0 group PD6
pin 103 (PD7): lcd0 (GPIO UNCLAIMED) function lcd0 group PD7
pin 104 (PD8): lcd0 (GPIO UNCLAIMED) function lcd0 group PD8
pin 105 (PD9): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 106 (PD10): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 107 (PD11): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 108 (PD12): twi0 pio:108 function twi0 group PD12
pin 109 (PD13): (MUX UNCLAIMED) pio:109
pin 110 (PD14): (MUX UNCLAIMED) pio:110
pin 111 (PD15): (MUX UNCLAIMED) pio:111
pin 112 (PD16): (MUX UNCLAIMED) pio:112
pin 113 (PD17): (MUX UNCLAIMED) pio:113
pin 114 (PD18): lcd0 (GPIO UNCLAIMED) function lcd0 group PD18
pin 115 (PD19): (MUX UNCLAIMED) pio:115
pin 116 (PD20): lcd0 (GPIO UNCLAIMED) function lcd0 group PD20
pin 117 (PD21): lcd0 (GPIO UNCLAIMED) function lcd0 group PD21
pin 128 (PE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 129 (PE1): (MUX UNCLAIMED) pio:129
pin 130 (PE2): (MUX UNCLAIMED) pio:130
pin 131 (PE3): (MUX UNCLAIMED) pio:131
pin 132 (PE4): (MUX UNCLAIMED) pio:132
pin 133 (PE5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 134 (PE6): (MUX UNCLAIMED) pio:134
pin 135 (PE7): (MUX UNCLAIMED) pio:135
pin 136 (PE8): (MUX UNCLAIMED) pio:136
pin 137 (PE9): (MUX UNCLAIMED) pio:137
pin 138 (PE10): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 139 (PE11): (MUX UNCLAIMED) pio:139
pin 140 (PE12): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 160 (PF0): sdc0 (GPIO UNCLAIMED) function io_disabled group PF0
pin 161 (PF1): sdc0 (GPIO UNCLAIMED) function io_disabled group PF1
pin 162 (PF2): sdc0 (GPIO UNCLAIMED) function io_disabled group PF2
pin 163 (PF3): sdc0 (GPIO UNCLAIMED) function io_disabled group PF3
pin 164 (PF4): sdc0 (GPIO UNCLAIMED) function io_disabled group PF4
pin 165 (PF5): sdc0 (GPIO UNCLAIMED) function io_disabled group PF5
registered pins: 53
pin 0 (PA0) 
pin 1 (PA1) 
pin 2 (PA2) 
pin 3 (PA3) 
pin 32 (PB0) 
pin 33 (PB1) 
pin 34 (PB2) 
pin 35 (PB3) 
pin 64 (PC0) 
pin 65 (PC1) 
pin 66 (PC2) 
pin 67 (PC3) 
pin 96 (PD0) 
pin 97 (PD1) 
pin 98 (PD2) 
pin 99 (PD3) 
pin 100 (PD4) 
pin 101 (PD5) 
pin 102 (PD6) 
pin 103 (PD7) 
pin 104 (PD8) 
pin 105 (PD9) 
pin 106 (PD10) 
pin 107 (PD11) 
pin 108 (PD12) 
pin 109 (PD13) 
pin 110 (PD14) 
pin 111 (PD15) 
pin 112 (PD16) 
pin 113 (PD17) 
pin 114 (PD18) 
pin 115 (PD19) 
pin 116 (PD20) 
pin 117 (PD21) 
pin 128 (PE0) 
pin 129 (PE1) 
pin 130 (PE2) 
pin 131 (PE3) 
pin 132 (PE4) 
pin 133 (PE5) 
pin 134 (PE6) 
pin 135 (PE7) 
pin 136 (PE8) 
pin 137 (PE9) 
pin 138 (PE10) 
pin 139 (PE11) 
pin 140 (PE12) 
pin 160 (PF0) 
pin 161 (PF1) 
pin 162 (PF2) 
pin 163 (PF3) 
pin 164 (PF4) 
pin 165 (PF5) 

	"fb-f1c200s@0": {
		"clock-name-defe": "link-defe",
		"clock-name-debe": "link-debe",
		"clock-name-tcon": "link-tcon",
		"reset-defe": 46,
		"reset-debe": 44,
		"reset-tcon": 36,
		"width": 320,
		"height": 240,
		"physical-width": 41,
		"physical-height": 31,
		"clock-frequency": 19000000,
		"hfront-porch": 749,
		"hback-porch": 38,
		"hsync-len": 18,
		"vfront-porch": 36,
		"vback-porch": 6,
		"vsync-len": 4,
		"hsync-active": false,
		"vsync-active": false,
		"den-active": true,
		"clk-active": true,
		"backlight": "led-pwm-bl.0"
	},