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/********************************************************************************
 * @file     ds18b20.c															*
 * @brief    The Driver code for DS18B20 with SWM181CBT6						*
 * @version  1.0.0																*
 * @date     2018/09/19 19:26:35												*
 *																				*
 * @note																		*
 * Copyright (C) 2000-2018 PM9GZY by yuanxihua@21cn.com. All rights reserved.	*
 ********************************************************************************/
/* Includes --------------------------------------------------------------------*/
#include "main.h"
/*
_________________________________________________
|	SWM181CBT6						DS18B20		|
|												|
|	DATA -	PC2			<--->		DQ0			|
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
#define SkipROM			0xCC		//跳过ROM 
#define SearchROM		0xF0		//搜索ROM 
#define ReadROM			0x33		//读ROM 
#define MatchROM		0x55		//匹配ROM 
#define AlarmROM		0xEC		//告警ROM 
 
#define StartConvert	0x44 		//开始温度转换，在温度转换期间总线上输出0，转换结束后输出1 
#define ReadScratchpad	0xBE 		//读寄存器的9个字节 
#define WriteScratchpad	0x4E 		//写寄存器的温度告警TH和TL 
#define CopyScratchpad	0x48 		//将寄存器的温度告警复制到EEPROM，在复制期间总线上输出0，复制完后输出1 
#define RecallEEPROM	0xB8  		//将EEPROM的温度告警复制到寄存器中，复制期间输出0，复制完成后输出1 
#define ReadPower		0xB4  		//读电源的供电方式：0为寄生电源供电；1为外部电源供电 
/* Private define ------------------------------------------------------------*/
#define PC2     				PIN2 
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
//void delay_us(uint32_t us)
//{
//    int32_t t=SysTick->VAL-(us*CyclesPerUs); 
//    if(t<0){t+=SysTick->LOAD;while((SysTick->CTRL&SysTick_CTRL_COUNTFLAG_Msk)==0){;}}
//    while(SysTick->VAL>t){;}
//}
//1.初始化
uint8_t DS18B20_init(uint32_t n)
{
	uint32_t i=0,ret=1;
	GPIO_Init(GPIOC, n, 1, 1, 0, 0);		//DQ 配置为输出引脚，开启上拉，推挽输出
	GPIO_SetBit(GPIOC, n);					//DQ=1;
	delay_us(900);							//稍作延时
	//开始初始化
	GPIO_ClrBit(GPIOC, n);					//DQ=0;
	delay_us(540);							//延时540us
	GPIO_SetBit(GPIOC, n);					//DQ=1;
	GPIO_Init(GPIOC, n, 0, 1, 0, 0);		//DQ 配置为输入引脚，开启上拉
	delay_us(60);							//稍作延时
	while(GPIO_GetBit(GPIOC, n))    		//等待DS18B20拉低总线
	{
		delay_us(1);				
        if(i++>240){ret=0;break;}			//初始化失败
	}
	GPIO_Init(GPIOC, n, 1, 1, 0, 0);		//DQ 配置为输出引脚，开启上拉，推挽输出
	GPIO_SetBit(GPIOC, n);					//DQ=1;
	delay_us(480);
	return ret;								//初始化成功
}
//2.写字节
void write_byte(uint32_t n,uint8_t dat)   	//写一个字节
{
	uint8_t i;
	for(i=0;i<8;i++)
	{
		GPIO_ClrBit(GPIOC, n);					//DQ=0; 总线拉低1us
		delay_us(1);	
		if(dat&0x01){GPIO_SetBit(GPIOC, n);}	//取最低位写入
		else{GPIO_ClrBit(GPIOC, n);}
		delay_us(60);				  			//延时60us
		GPIO_SetBit(GPIOC, n);					//DQ=1; 释放总线
		delay_us(1); 
		dat=dat>>1;    							//从低位开始写
	}
}
//3.读字节
uint8_t read_byte(uint32_t n)    				//读一个字节
{
	uint8_t i,dat=0;
	for(i=0;i<8;i++)
	{
		GPIO_ClrBit(GPIOC, n);					//DQ=0; 总线拉低1us
		delay_us(1);
		GPIO_SetBit(GPIOC, n);					//DQ=1; 释放总线
		GPIO_Init(GPIOC, n, 0, 1, 0, 0);		//DQ 配置为输入引脚，开启上拉
		delay_us(2);								//延时等待数据稳定 5
		dat=dat>>1;       						//从最低位开始读
		if(GPIO_GetBit(GPIOC, n)){dat|=0x80;}	//每次读一位
		else{dat&=0x7f;}
		delay_us(30); 							//等待读取数据稳定
		GPIO_Init(GPIOC, n, 1, 1, 0, 0);		//DQ 配置为输出引脚，开启上拉，推挽输出
		GPIO_SetBit(GPIOC, n);					//DQ=1; 释放总线
		delay_us(1); 
	}
	return dat;
}
//4.按位CRC运算
//Purpose:    To calculate an 8-bit CRC based on a polynomial and the series 
//            of data bytes 
//Note:       Polynomial used x^8 + x^5 + x^4 + 1 = 10001100 
//Inputs:     A pointer to an array of the data bytes and an uint8_t saying how many 
//            bytes there are in the data array 
//Outputs:    An uint8_t which is the calculated CRC 
uint8_t OneWireCRC8(uint8_t *buf, uint8_t len)
{
    #define CRC8_POLYNOMIAL 0x8C
    uint8_t crc=0,val=0,inb,mix;
    while(len--){inb=*buf++;if(inb){val=1;}for(uint8_t i=8;i;i--){mix=(crc^inb)&0x01;crc>>=1;if(mix){crc^=CRC8_POLYNOMIAL;}inb>>=1;}}
    if(!val){return 0xFF;}  /* If all bytes are 0, return a different CRC so that the test will fail */
    return crc;
}
//5.读温度
uint16_t read_temper(uint32_t n)
{    
	uint16_t temp=0xffff;uint8_t data[9],crc,ret;ret=ret; 
	ret=DS18B20_init(n);   
	write_byte(n,0xcc);	//跳过ROM操作命令
	write_byte(n,0x44);	//发送启动温度转换命令
	delay_us(2000);
	ret=DS18B20_init(n); 
	write_byte(n,0xcc);	//跳过ROM操作命令
	write_byte(n,0xbe);	//发送读温度寄存器命令
	delay_us(2000);
    
    for(int i=0;i<9;i++){data[i]=read_byte(n);}                         //read Scratchpad Memory of DS
    crc=OneWireCRC8(data,8);                                            //calculate crc
    if(crc==data[8]){temp=((uint16_t)data[1]<<8)|data[0];}              //compare : calculate with received
    return temp;        //返回温度值
}
//6.温度转换
float temper_change(uint32_t n)
{
    int32_t temper;float tp;
    temper=read_temper(n);
	printf("temper=0x%04x\n\r",temper);
    if(temper<0)    			//考虑负温度的情况
    {
        temper=temper-1;
        temper=~temper;
    }
    tp=temper/16;  		        //16位温度转换成10进制的温度
    temper=tp*100+0.5;   	    //留两个小数点，并四舍五入
	printf("DS18B20=%3.2f\n\r",tp);
    return temper;
}
//代码完毕

#include "main.h"

/******************************************************************
Lin总线帧格式：帧头+应答

帧头：同步间隔段（至少13个显性电平）+同步间隔段间隔符（至少1位隐形电平）+同步段（0x55）+字节间间隔+PID（ID+校验位）
注：PID=ID（6位）+校验（2位）
ID 取值范围为： 0x00~0x3f
ID的取值分类：  
                信号携带帧 ：                           0x00~0x3b
                诊断帧（主机请求）：        0x3c
                诊断帧（从机应答）：        0x3d
                保留帧 ：                          0x3e,0x3f
P0 = ID0⊕ID1⊕ID2⊕ID4                异或运算
P1 = ┐（ID3⊕ID4⊕ID5⊕ID1）                异或后取非

应答：应答间隔+数据段+校验和段
注：数据段           低字节的低位先发
标准型校验和：        只校验数据段
增强型校验和：        校验数据段以及PID
诊断帧只能用标准型校验和

******************************************************************/

/******************************************************************
lin中断接收函数功能：
1、回环效果：即主机发送帧头或者主机发送帧头+应答，主机的中断服务程序都会接收数据。
        可以检测出：主机串口Tx、Rx、Lin脚，三个引脚上的信号是相同的（除了电平不同）。
2、当串口检测到连续至少11位显性电平即进入中断开始接收。
3、中断服务函数接收数据时按进程推进
        ①接收同步段是否OK？
        ②接收ID校验后解析是数据执行还是反馈
        若是执行：                                        若是反馈：
        ③分步接收数据                                ③准备数据在帧头结束后发送数据
        ④匹配校验数据是否正确
        ⑤解析数据并执行

******************************************************************/
uint8_t TxData = 0;
volatile uint32_t TBtIdx = 0;
volatile uint32_t TxBusy = 0;
#define UART_TX_PIN                        PIN18
#define UART_TX_LOW()                GPIO_ClrBit(GPION, UART_TX_PIN)
#define UART_TX_HIGH()                GPIO_SetBit(GPION, UART_TX_PIN)
#define UART_RX_PIN               PIN19
#define UART_RX_Value()                GPIO_GetBit(GPION, UART_RX_PIN)
//#define UART_RX_POINT                GPIOB, PIN7
#define UART_RX_POINT                GPION, PIN5
uint8_t RxData = 0;
volatile uint32_t RBtIdx = 0;
volatile uint32_t RxBusy = 0;

void uart1_putchar(uint8_t ch)
{
        while(TxBusy){;}                                                                //等待发送空闲
        TxData = ch;TBtIdx = 0;TxBusy = 1;
        TIMR_Start(TIMR1);
        while(TxBusy){;}                                                                //等待发送完成
}
void TIMR1_Handler(void)
{
        TIMR_INTClr(TIMR1);
        if(TBtIdx == 0){UART_TX_LOW(); }else                        //起始位
        if(TBtIdx <  9){if(TxData&0x1){UART_TX_HIGH();}else{UART_TX_LOW();}        TxData>>=1;}else
        if(TBtIdx == 9){UART_TX_HIGH();TIMR_Stop(TIMR1);TxBusy = 0;TBtIdx = 0;return;} //停止位
        TBtIdx++;
}
void uart1_putbuf(uint8_t *buf,uint32_t len){while(len--){uart1_putchar(*buf++);}}
void uart1_puts(char *str){while(*str){uart1_putchar((int)*str++);}}        

void UART1Init(void)
{
        GPIO_Init(GPION, PIN19, 0, 1, 0);                                //GPION.19 配置为输入引脚，开启上拉
        GPIO_Init(GPION, PIN18, 1, 0, 0);                                //GPION.18 配置为输出引脚，推挽输出
        GPIO_Init(GPION, PIN17, 1, 0, 0);                                //GPION.17 配置为输出引脚，推挽输出
        GPIO_Init(UART_RX_POINT , 1, 0, 0);                                //GPIOB.7  配置为输出引脚，推挽输出        用于调试接收采样点
        GPIO_SetBit(GPION, PIN18);
        GPIO_SetBit(GPION, PIN17);
        TIMR_Init(TIMR1, TIMR_MODE_TIMER, (SystemCoreClock/LIN_BPS)*1.00, 1);        //每1/LIN_BPS秒钟触发一次中断，用于发送
        TIMR_Init(TIMR2, TIMR_MODE_TIMER, (SystemCoreClock/LIN_BPS)*0.99, 1);        //每1/LIN_BPS秒钟触发一次中断，用于接收
}

// 主机帧头部分
// 起先是同步间隔段，因为作为主机要连续发送至少13位显性电平，这里用的是STM32自带的库函数，直接调用就行。
void Lin_SendBreak(void)
{
        UART_TX_LOW();                                                                        //显性电平
        DelayUs((1000000*13)/LIN_BPS);                                        //至少13位显性电平
        UART_TX_HIGH();                                                                        //隐形电平
        DelayUs((1000000*1 )/LIN_BPS);                                        //至少01位隐形电平
}

// 接着就是同步段，发送0x55
void Lin_SendSyncSegment(void){uart1_putchar(0x55);}
//然后就是发送PID（protect ID），这里的前六位为ID，后两位为校验位，函数功能为：输入ID，返回PID。
uint8_t Lin_CheckPID(uint8_t id)
{
        uint8_t P0 = (((id)^(id>>1)^(id>>2)^(id>>4))&0x01)<<6 ;
        uint8_t P1 = ((~((id>>1)^(id>>3)^(id>>4)^(id>>5)))&0x01)<<7 ;
        return (id|P0|P1) ;
}
// 该函数体就是单片机作为主机发送的帧头，可以指定ID发送帧头，接收从机返回的数据；也可以发送帧头+数据，让从机接收。
void Lin_Hearder(uint8_t id)
{
        Lin_SendBreak();
        Lin_SendSyncSegment();
        uart1_putchar(Lin_CheckPID(id));
}
// 此段函数功能：输入ID+数据，返回校验和段，里面有调用返回PID函数。诊断帧只能用标准校验这里还没有验证过，因为校验还没有测试。
// 是经典校验还是增强校验，另：诊断帧只能经典校验
uint8_t Lin_Checksum(uint8_t id , uint8_t data[])
{
        uint8_t t ;
        uint16_t sum ;

        sum = data[0];
        if(id == 0x3c)                        // 如果是诊断帧，用经典校验
        {
                for(t=1;t<8;t++)
                {
                        sum += data[t];
                        if(sum&0xff00)
                        {
                                sum&=0x00ff;
                                sum+=1;
                        }
                }
                sum = ~sum;        
                return (uint8_t)sum ;
        }
        for(t=1;t<8;t++)
        {
                sum += data[t];
                if(sum&0xff00)
                {
                        sum&=0x00ff;
                        sum+=1;
                }
        }
        sum+=Lin_CheckPID(id);
        if(sum&0xff00)
        {
                sum&=0x00ff;
                sum+=1;
        }
        sum = ~sum;        
        return (uint8_t)sum ;
}
//上面三个函数是单片机无论作为主机还是从机都需要用到的部分，所以在后面进行预编译选择的时候，放到外面。
//这里是主机的响应函数调用。
void Lin_Response(uint8_t id ,uint8_t data[])
{
        uart1_putbuf(data,8);
        uart1_putchar(Lin_Checksum(id,data));
}
void Lin_MainPutData(uint8_t id,uint8_t *data)
{
        Lin_Hearder(id);
        Lin_Response(id,data);
}
uint8_t uart1_getchar(void)
{
        TIMR_Start(TIMR2);
        TBtIdx = 0;RxBusy = 1;
        while(RxBusy){;}                                                                //等待接收完成
        return RxData;
}
void TIMR2_Handler(void)
{
        TIMR_INTClr(TIMR2);
        if(RBtIdx == 0){}else                                                        //起始位
        if(RBtIdx <  9){RxData>>=1;GPIO_InvBit(UART_RX_POINT);if(UART_RX_Value()){RxData|=0x80;}GPIO_InvBit(UART_RX_POINT);}else
        if(RBtIdx == 9){TIMR_Stop(TIMR2);RxBusy = 0;RBtIdx = 0;return;} //停止位
        RBtIdx++;
}
uint8_t Lin_MainGetData(uint8_t id,uint8_t *data)
{
        Lin_Hearder(id);                                                                //发送命令头
        while(UART_RX_Value()){;}                                                //等待起始位
        DelayUs((1000000*0.425)/LIN_BPS);                                //延时半个采样点
        for(int i=0;i<8;i++){data=uart1_getchar();}        //接收8字节数据
        uint8_t ReceiveCheckSum = uart1_getchar();                //接收校验和
        uint8_t SumCheck = Lin_Checksum(id,data);                //计算校验和
//        printf("ReceiveCheckSum & SumCheck: 0x%02x=0x%02x ",ReceiveCheckSum,SumCheck);
        if(ReceiveCheckSum == SumCheck)        {return 1;}                //校验正确
        return 0;
}        

/*
代码完毕部分内容参考了CSDN上的帖子
*/

#include <stdio.h>
#include "M051Series.h"
#include "Driver\DrvSYS.h"
#include "Driver\DrvUART.h"
#include "Driver\DrvGPIO.h"

//SD5128的逻辑0是25%的高75%的低，逻辑1是75%的高25%的低，那就是相当于开始25%是固定低，
//结束的25%是固定高，中间50%与逻辑相同，那么就可以简化为数据1000和1110代表逻辑0和逻辑1；
//SD5128的每个像素是3个字节的RGB数据，结束符是一位的低，25位的高，即可表示为0X7FFFFFFF
//串口UART起始位是低，结束位是高，刚好与上面的SD5128的逻辑相反，那么串口数据用6位，
//UART波形取反相后就能与SD5128的占空比符合，每个字符代表SD5128的两个BIT。编码关系如下：
//           __________________________________
//     |_ST_| D0 | D1 | D2 | D3 | D4 | D5 | SP |
//  00 | 0    1  1  1   0    1   1 1  | = 0x37
//  01 | 0   1  1  1   0    0   0 1  | = 0x07
//  10 | 0   0  0  1   0    1   1 1  | = 0x34
//  11 | 0   0  0  1   0    0   0 1  | = 0x04

unsigned char  BIT2BYTE[4]={0x37,0x07,0x34,0x04}; //BIT2BYTE
unsigned char  ENDCODE[4] ={0x7F,0xFF,0xFF,0xFF}; //ENDCODE
 
int SD5128_Init(void)
{
 STR_UART_T sParam;
    
 /* Set UART0 Pin */
 DrvGPIO_InitFunction(E_FUNC_UART0);

 /* Select UART0 Clock Source From 12Mhz*/
 DrvSYS_SelectIPClockSource(E_SYS_UART_CLKSRC,0);
 /* Select UART0 Clock Source From PLL*/
// DrvSYS_SelectIPClockSource(E_SYS_UART_CLKSRC,1);

 /* UART0 Setting */
    sParam.u32BaudRate   = 800000; //1000K
    sParam.u8cDataBits   = DRVUART_DATABITS_6;
    sParam.u8cStopBits   = DRVUART_STOPBITS_1;
    sParam.u8cParity   = DRVUART_PARITY_NONE;
    sParam.u8cRxTriggerLevel= DRVUART_FIFO_1BYTES;

 if(DrvUART_Open(UART_PORT0,&sParam) != E_SUCCESS)
 {
  printf("UART0 open failed\n");
  return FALSE;
 }
 return TRUE;
}

void SD5128_BYTE(unsigned char *buf,unsigned int length)
{
 int i;

 while(length--)
 {
  i=6;
  while(i>=0)
  {
   while(UART0->FSR.TX_FULL == 1);
   { 
    UART0->DATA = BIT2BYTE[(*buf>>i)&0x3];// printf(" 0x%02x",BIT2BYTE[(*buf>>i)&0x3]);
   }
   i=i-2;
  }
  buf++;
 }
}
void SD5128_Test(void)
{
 unsigned int i=0;
 unsigned char RGBDATA[3];   //RGB
 unsigned int  dly;

 printf("\n\r\n\r");
 printf("*** 9G-M0516 V1.00 Build by yuanxihua@21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
 printf("*** 9G-M0516 V1.00 Rebooting ...\n\r\n\r");
    
 SD5128_Init();
 while(1)
 {
  if(i++ > 0xFE) i=0;
  RGBDATA[0]=RGBDATA[1]=RGBDATA[2]=i; // printf("\n\ri=%02x |",i);
  SD5128_BYTE(RGBDATA,3);    // printf(" ||");//send rgbdata
  SD5128_BYTE(ENDCODE,4); //send endcode
  for(dly=0;dly<50;dly++) DrvSYS_Delay(1000); //delay 50ms
 }
}

/********************************************************************************/
/* @file	ad7124.c															*/
/* @version	V1.00																*/
/* $author:	yuanxihua@21cn.com													*/
/* $Date: 	2019/03/04 02:54 $ 													*/
/* @brief 	SWM320RBT6 Series AD7124 Driver Sample Code							*/
/*																				*/
/* @note																		*/
/* Copyright (C) 2010-2019 PM9GZY Technology Corp. All rights reserved.			*/
/*																				*/
/********************************************************************************/ 
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "ad7124.h"
/*
_________________________________________________
|	SWM320RBT6						AD7124		|
|												|
|	PP1		MISO1		<----		MISO		|
|	PP2		MOSI1		---->		MOSI		|
|	PP3		SCLK1		---->		SCLK		|
|	PP4		NSS1		---->		ANCS		|
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AD7124_CS_L()		GPIO_ClrBit(GPIOP, PIN4)
#define AD7124_CS_H()		GPIO_SetBit(GPIOP, PIN4)
/* Private macro -------------------------------------------------------------*/
#define INVALID_VAL 		-1 /* Invalid argument */
#define COMM_ERR    		-2 /* Communication error on receive */
#define TIMEOUT     		-3 /* A timeout has occured */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
void AD7124_Init(void);
void AD7124_Reset(void);
/* Private functions ---------------------------------------------------------*/
void SPI1Init(void)
{
	SPI_InitStructure SPI_initStruct;

	PORT_Init(PORTP, PIN1, FUNMUX1_SPI1_MISO, 1);
	PORT_Init(PORTP, PIN2, FUNMUX0_SPI1_MOSI, 0);
	PORT_Init(PORTP, PIN3, FUNMUX1_SPI1_SCLK, 0);
	GPIO_Init(GPIOP, PIN4, 1, 0, 0);AD7124_CS_H();//PORT_Init(PORTP, PIN4, FUNMUX0_SPI1_SSEL, 0);
	
	SPI_initStruct.clkDiv 		= SPI_CLKDIV_64;//0.52US
	SPI_initStruct.FrameFormat 	= SPI_FORMAT_SPI;
	SPI_initStruct.SampleEdge 	= SPI_FIRST_EDGE;
	SPI_initStruct.IdleLevel 	= SPI_LOW_LEVEL;
	SPI_initStruct.WordSize 	= 8;
	SPI_initStruct.Master 		= 1;
	SPI_initStruct.RXHFullIEn 	= 0;
	SPI_initStruct.TXEmptyIEn 	= 0;
	SPI_initStruct.TXCompleteIEn = 0;
	SPI_Init(SPI1, &SPI_initStruct);
	
	SPI_Open(SPI1);
	AD7124_Reset();
	AD7124_Init();
}
void AD7124_Read_Register(ad7124_reg_t *reg)
{
	uint8_t cmd=reg->addr+0x40,width=reg->size,admit=reg->rw;uint32_t val=0;
	if(!(admit&AD7124_RO)){return;}
	AD7124_CS_L();
	SPI_ReadWrite(SPI1,cmd);while(width--){val<<=8;val|=SPI_ReadWrite(SPI1,0x55)&0xff;}reg->value=val;
	AD7124_CS_H();
}
void AD7124_Write_Register(ad7124_reg_t *reg)
{
	uint8_t cmd=reg->addr+0x00,width=reg->size,admit=reg->rw;uint32_t val=reg->value;
	if(!(admit&AD7124_WO)){return;}
	AD7124_CS_L();
	SPI_ReadWrite(SPI1,cmd);while(width--){SPI_ReadWrite(SPI1,(val>>(width*8))&0xff);}
	AD7124_CS_H();
}
void AD7124_Reset(void){AD7124_CS_L();for(uint8_t i=0;i<8;i++){SPI_ReadWrite(SPI1,0xFF);}AD7124_CS_H();osDelay(10);}
void AD7124_Init(void){for(uint8_t i=AD7124_Status;i<AD7124_REG_END;i++){AD7124_Write_Register(&ad7124_regs[i]);}}
uint8_t AD7124_CRC8(uint8_t *buf, uint8_t len)
{
    uint8_t i,crc=0,MULA=AD7124_CRC8_POLYNOMIAL_REPRESENTATION;
    while(len--){for(i=0x80;i!=0;i>>=1){if(((crc&0x80)!=0)!=((*buf&i)!=0)){crc<<=1;crc^=MULA;}else{crc<<=1;}}buf++;}
    return crc;
}

void AD7124_Gain(void){}
uint8_t AD7124_Read(uint32_t *data)
{
	int32_t timeout=1000000;uint8_t total=0;
	uint8_t lastch=20;uint8_t nowch=20;
	
	while(1)
	{
		while(--timeout)
		{
			/* Read the value of the Status Register */
			AD7124_Read_Register(&ad7124_regs[AD7124_Status]);
			/* Check the RDY bit in the Status Register */
			if((ad7124_regs[AD7124_Status].value & AD7124_STATUS_REG_RDY)==0) 
			{nowch = AD7124_STATUS_REG_CH_ACTIVE(ad7124_regs[AD7124_Status].value);break;} 
		}
		if(timeout<=0){printf("AD Conv Timeout!!!\n\r");return total;}
		if(lastch!=nowch)
		{
			/* Read the value of the Data Register */
			AD7124_Read_Register(&ad7124_regs[AD7124_Data]);
			/* Get the read result */
			data[nowch] = ad7124_regs[AD7124_Data].value; data[nowch]&=0xFFFFFF;
			lastch=nowch;total++;
//			printf("AD7124_Read data[%d] = 0x%08x \n\r",nowch,data[nowch]);
		}
		if(total>=4){break;}
	}		
	return total;
}

void AD7124_Test(void)
{
	uint32_t adc[4]={0};float val[4];	
//	AD7124_CS_L(); SPI_ReadWrite(SPI1,0x55);AD7124_CS_H();
//	AD7124_Read_Register(&ad7124_regs[AD7124_ID]);
//	printf("AD7124_ID = 0x%02x \n\r",ad7124_regs[AD7124_ID].value);	

//	AD7124_Read_Register(&ad7124_regs[AD7124_CHANNEL_0]);
//	printf("AD7124_CHANNEL_0 = 0x%08x \n\r",ad7124_regs[AD7124_CHANNEL_0].value);	
	
//	ad7124_regs[AD7124_FILTER_0].value=0x555555;
//	AD7124_Write_Register(&ad7124_regs[AD7124_FILTER_0]);
//	AD7124_Read_Register(&ad7124_regs[AD7124_FILTER_0]);
//	printf("AD7124_FILTER_0 = 0x%08x \n\r",ad7124_regs[AD7124_FILTER_0].value);	

//	for(uint8_t i=AD7124_Status;i<AD7124_REG_END;i++)
//	{
//		AD7124_Read_Register(&ad7124_regs[i]);
//		printf("ad7124_regs[0x%02x]=0x%08x \n\r",i,ad7124_regs[i].value);	
//	}

	AD7124_Read(adc);
//	printf("ADC[0]=0x%08x,ADC[1]=0x%08x,ADC[2]=0x%08x,ADC[3]=0x%08x\n\r",adc[0],adc[1],adc[2],adc[3]);
	for(uint8_t i=0;i<4;i++)
	{
		val[i]=adc[i];val[i]*=2.500;val[i]/=0xffffff;
	}
	val[0]/=128;val[1]/=16;val[2]/=4;val[3]/=1;
//	printf("VAL[0]=%3.10f V\n\r",val[0]);
//	printf("VAL[1]=%3.10f V\n\r",val[1]);
//	printf("VAL[2]=%3.10f V\n\r",val[2]);
//	printf("VAL[3]=%3.10f V\n\r",val[3]);
//	val[0]*=1000;val[1]*=1000;val[2]*=1000;val[3]*=1000;
	printf("%3.10f,%3.10f,%3.10f,%3.10f\n\r",val[0],val[1],val[2],val[3]);
	OLED_Volute(val);
	osDelay(200);
}

#ifndef __AD7124_H__
#define __AD7124_H__

#define AD7124_CRC8_POLYNOMIAL_REPRESENTATION		0x07 	/* x8 + x2 + x + 1 */

#define AD7124_WO 1   /* Write */
#define	AD7124_RO 2   /* Read */
#define	AD7124_RW 3   /* Read and Write */

/* AD7124 Register Map */
#define AD7124_COMM_REG      0x00
#define AD7124_STATUS_REG    0x00
#define AD7124_ADC_CTRL_REG  0x01
#define AD7124_DATA_REG      0x02
#define AD7124_IO_CTRL1_REG  0x03
#define AD7124_IO_CTRL2_REG  0x04
#define AD7124_ID_REG        0x05
#define AD7124_ERR_REG       0x06
#define AD7124_ERREN_REG     0x07
#define AD7124_CH0_MAP_REG   0x09
#define AD7124_CH1_MAP_REG   0x0A
#define AD7124_CH2_MAP_REG   0x0B
#define AD7124_CH3_MAP_REG   0x0C
#define AD7124_CH4_MAP_REG   0x0D
#define AD7124_CH5_MAP_REG   0x0E
#define AD7124_CH6_MAP_REG   0x0F
#define AD7124_CH7_MAP_REG   0x10
#define AD7124_CH8_MAP_REG   0x11
#define AD7124_CH9_MAP_REG   0x12
#define AD7124_CH10_MAP_REG  0x13
#define AD7124_CH11_MAP_REG  0x14
#define AD7124_CH12_MAP_REG  0x15
#define AD7124_CH13_MAP_REG  0x16
#define AD7124_CH14_MAP_REG  0x17
#define AD7124_CH15_MAP_REG  0x18
#define AD7124_CFG0_REG      0x19
#define AD7124_CFG1_REG      0x1A
#define AD7124_CFG2_REG      0x1B
#define AD7124_CFG3_REG      0x1C
#define AD7124_CFG4_REG      0x1D
#define AD7124_CFG5_REG      0x1E
#define AD7124_CFG6_REG      0x1F
#define AD7124_CFG7_REG      0x20
#define AD7124_FILT0_REG     0x21
#define AD7124_FILT1_REG     0x22
#define AD7124_FILT2_REG     0x23
#define AD7124_FILT3_REG     0x24
#define AD7124_FILT4_REG     0x25
#define AD7124_FILT5_REG     0x26
#define AD7124_FILT6_REG     0x27
#define AD7124_FILT7_REG     0x28
#define AD7124_OFFS0_REG     0x29
#define AD7124_OFFS1_REG     0x2A
#define AD7124_OFFS2_REG     0x2B
#define AD7124_OFFS3_REG     0x2C
#define AD7124_OFFS4_REG     0x2D
#define AD7124_OFFS5_REG     0x2E
#define AD7124_OFFS6_REG     0x2F
#define AD7124_OFFS7_REG     0x30
#define AD7124_GAIN0_REG     0x31
#define AD7124_GAIN1_REG     0x32
#define AD7124_GAIN2_REG     0x33
#define AD7124_GAIN3_REG     0x34
#define AD7124_GAIN4_REG     0x35
#define AD7124_GAIN5_REG     0x36
#define AD7124_GAIN6_REG     0x37
#define AD7124_GAIN7_REG     0x38

/* Communication Register bits */
#define AD7124_COMM_REG_WEN    					(0 << 7)
#define AD7124_COMM_REG_WR     					(0 << 6)
#define AD7124_COMM_REG_RD     					(1 << 6)
#define AD7124_COMM_REG_RA(x)  					((x) & 0x3F)

/* Status Register bits */
#define AD7124_STATUS_REG_RDY          			(1 << 7)
#define AD7124_STATUS_REG_ERROR_FLAG   			(1 << 6)
#define AD7124_STATUS_REG_POR_FLAG     			(1 << 4)
#define AD7124_STATUS_REG_CH_ACTIVE(x) 			((x) & 0xF)

/* ADC_Control Register bits */
#define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL   		(1 << 12)
#define AD7124_ADC_CTRL_REG_CONT_READ      		(1 << 11)
#define AD7124_ADC_CTRL_REG_DATA_STATUS    		(1 << 10)
#define AD7124_ADC_CTRL_REG_CS_EN          		(1 << 9)
#define AD7124_ADC_CTRL_REG_REF_EN         		(1 << 8)
#define AD7124_ADC_CTRL_REG_POWER_MODE(x)  		(((x) & 0x3) << 6)
#define AD7124_ADC_CTRL_REG_MODE(x)        		(((x) & 0xF) << 2)
#define AD7124_ADC_CTRL_REG_CLK_SEL(x))    		(((x) & 0x3) << 0)

/* IO_Control_1 Register bits */
#define AD7124_IO_CTRL1_REG_GPIO_DAT2     		(1 << 23)
#define AD7124_IO_CTRL1_REG_GPIO_DAT1     		(1 << 22)
#define AD7124_IO_CTRL1_REG_GPIO_CTRL2    		(1 << 19)
#define AD7124_IO_CTRL1_REG_GPIO_CTRL1    		(1 << 18)
#define AD7124_IO_CTRL1_REG_PDSW          		(1 << 15)
#define AD7124_IO_CTRL1_REG_IOUT1(x)      		(((x) & 0x7) << 11)
#define AD7124_IO_CTRL1_REG_IOUT0(x)      		(((x) & 0x7) << 8)
#define AD7124_IO_CTRL1_REG_IOUT_CH1(x)   		(((x) & 0xF) << 4)
#define AD7124_IO_CTRL1_REG_IOUT_CH0(x)   		(((x) & 0xF) << 0)

/*IO_Control_1 AD7124-8 specific bits */
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 		(1 << 23)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT3     	(1 << 22)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT2     	(1 << 21)
#define AD7124_8_IO_CTRL1_REG_GPIO_DAT1     	(1 << 20)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4    	(1 << 19)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3    	(1 << 18)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2    	(1 << 17)
#define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1    	(1 << 16)

/* IO_Control_2 Register bits */
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS7   		(1 << 15)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS6   		(1 << 14)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS5   		(1 << 11)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS4   		(1 << 10)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS3   		(1 << 5)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS2   		(1 << 4)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS1   		(1 << 1)
#define AD7124_IO_CTRL2_REG_GPIO_VBIAS0   		(1 << 0)

/*IO_Control_2 AD7124-8 specific bits */
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15  	(1 << 15)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14  	(1 << 14)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13  	(1 << 13)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12  	(1 << 12)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11  	(1 << 11)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10  	(1 << 10)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9   	(1 << 9)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8   	(1 << 8)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7   	(1 << 7)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6   	(1 << 6)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5   	(1 << 5)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4   	(1 << 4)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3   	(1 << 3)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2   	(1 << 2)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1   	(1 << 1)
#define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0   	(1 << 0)

/* ID Register bits */
#define AD7124_ID_REG_DEVICE_ID(x)   			(((x) & 0xF) << 4)
#define AD7124_ID_REG_SILICON_REV(x) 			(((x) & 0xF) << 0)

/* Error Register bits */
#define AD7124_ERR_REG_LDO_CAP_ERR        		(1 << 19)
#define AD7124_ERR_REG_ADC_CAL_ERR        		(1 << 18)
#define AD7124_ERR_REG_ADC_CONV_ERR       		(1 << 17)
#define AD7124_ERR_REG_ADC_SAT_ERR        		(1 << 16)
#define AD7124_ERR_REG_AINP_OV_ERR        		(1 << 15)
#define AD7124_ERR_REG_AINP_UV_ERR        		(1 << 14)
#define AD7124_ERR_REG_AINM_OV_ERR        		(1 << 13)
#define AD7124_ERR_REG_AINM_UV_ERR        		(1 << 12)
#define AD7124_ERR_REG_REF_DET_ERR        		(1 << 11)
#define AD7124_ERR_REG_DLDO_PSM_ERR       		(1 << 9)
#define AD7124_ERR_REG_ALDO_PSM_ERR       		(1 << 7)
#define AD7124_ERR_REG_SPI_IGNORE_ERR     		(1 << 6)
#define AD7124_ERR_REG_SPI_SLCK_CNT_ERR   		(1 << 5)
#define AD7124_ERR_REG_SPI_READ_ERR       		(1 << 4)
#define AD7124_ERR_REG_SPI_WRITE_ERR      		(1 << 3)
#define AD7124_ERR_REG_SPI_CRC_ERR        		(1 << 2)
#define AD7124_ERR_REG_MM_CRC_ERR         		(1 << 1)

/* Error_En Register bits */
#define AD7124_ERREN_REG_MCLK_CNT_EN           	(1 << 22)
#define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN   	(1 << 21)
#define AD7124_ERREN_REG_LDO_CAP_CHK(x)        	(((x) & 0x3) << 19)
#define AD7124_ERREN_REG_ADC_CAL_ERR_EN        	(1 << 18)
#define AD7124_ERREN_REG_ADC_CONV_ERR_EN       	(1 << 17)
#define AD7124_ERREN_REG_ADC_SAT_ERR_EN        	(1 << 16)
#define AD7124_ERREN_REG_AINP_OV_ERR_EN        	(1 << 15)
#define AD7124_ERREN_REG_AINP_UV_ERR_EN       	(1 << 14)
#define AD7124_ERREN_REG_AINM_OV_ERR_EN       	(1 << 13)
#define AD7124_ERREN_REG_AINM_UV_ERR_EN        	(1 << 12)
#define AD7124_ERREN_REG_REF_DET_ERR_EN       	(1 << 11)
#define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN 	(1 << 10)
#define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR      	(1 << 9)
#define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN 	(1 << 8)
#define AD7124_ERREN_REG_ALDO_PSM_ERR_EN       	(1 << 7)
#define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN     	(1 << 6)
#define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN   	(1 << 5)
#define AD7124_ERREN_REG_SPI_READ_ERR_EN       	(1 << 4)
#define AD7124_ERREN_REG_SPI_WRITE_ERR_EN      	(1 << 3)
#define AD7124_ERREN_REG_SPI_CRC_ERR_EN        	(1 << 2)
#define AD7124_ERREN_REG_MM_CRC_ERR_EN         	(1 << 1)

/* Channel Registers 0-15 bits */
#define AD7124_CH_MAP_REG_CH_ENABLE    			(1 << 15)
#define AD7124_CH_MAP_REG_SETUP(x)     			(((x) & 0x7) << 12)
#define AD7124_CH_MAP_REG_AINP(x)      			(((x) & 0x1F) << 5)    
#define AD7124_CH_MAP_REG_AINM(x)      			(((x) & 0x1F) << 0)

/* Configuration Registers 0-7 bits */
#define AD7124_CFG_REG_BIPOLAR     				(1 << 11)
#define AD7124_CFG_REG_BURNOUT(x)  				(((x) & 0x3) << 9)
#define AD7124_CFG_REG_REF_BUFP    				(1 << 8)
#define AD7124_CFG_REG_REF_BUFM    				(1 << 7)
#define AD7124_CFG_REG_AIN_BUFP    				(1 << 6)
#define AD7124_CFG_REG_AINN_BUFM   				(1 << 5)
#define AD7124_CFG_REG_REF_SEL(x)  				((x) & 0x3) << 3
#define AD7124_CFG_REG_PGA(x)      				(((x) & 0x7) << 0)

/* Filter Register 0-7 bits */
#define AD7124_FILT_REG_FILTER(x)         		(((x) & 0x7) << 21)
#define AD7124_FILT_REG_REJ60             		(1 << 20)
#define AD7124_FILT_REG_POST_FILTER(x)    		(((x) & 0x7) << 17)
#define AD7124_FILT_REG_SINGLE_CYCLE      		(1 << 16)
#define AD7124_FILT_REG_FS(x)             		(((x) & 0x7FF) << 0)

/*! Device register info */
typedef struct 
{
	uint8_t addr;
	int32_t value;
	uint8_t size;
	uint8_t rw;
}ad7124_reg_t;

/*! Array holding the info for the ad7124 registers - address, initial value,
    size and access type. */
ad7124_reg_t ad7124_regs[] =
{
	{0x00,     0x00, 1, AD7124_RO}, /* AD7124_Status */
	//使能DATA_STATUS、REF_EN 和 FULL POWER的连续采样模式，禁止用DOUT_RDY_DEL、CONT_READ和CS_EN，内时钟CLK无输出
	{0x01,   0x0580, 2, AD7124_RW}, /* AD7124_ADC_Control */
	{0x02, 0x000000, 3, AD7124_RO}, /* AD7124_Data */
	//禁用IOUT0、IOUT1、不用PDSW低边桥开关
	{0x03, 0x000000, 3, AD7124_RW}, /* AD7124_IOCon1 */
	//禁用VBIAS0-VBIAS7
	{0x04,   0x0000, 2, AD7124_RW}, /* AD7124_IOCon2 */
	{0x05,     0x04, 1, AD7124_RO}, /* AD7124_ID */
	{0x06, 0x000000, 3, AD7124_RO}, /* AD7124_Error */
	//不用ERROR功能
	{0x07, 0x000000, 3, AD7124_RW}, /* AD7124_Error_En */
	{0x08,     0x00, 1, AD7124_RO}, /* AD7124_Mclk_Count */
	//使能通道0、选择Setup0配置组、输入脚分配AIN0->AINP,AIN1->AINM
	{0x09,   0x8001, 2, AD7124_RW}, /* AD7124_Channel_0 */
	//使能通道1、选择Setup1配置组、输入脚分配AIN2->AINP,AIN3->AINM
	{0x0A,   0x9043, 2, AD7124_RW}, /* AD7124_Channel_1 */
	//使能通道2、选择Setup2配置组、输入脚分配AIN4->AINP,AIN5->AINM
	{0x0B,   0xA085, 2, AD7124_RW}, /* AD7124_Channel_2 */
	//使能通道3、选择Setup3配置组、输入脚分配AIN6->AINP,AIN7->AINM
	{0x0C,   0xB0C7, 2, AD7124_RW}, /* AD7124_Channel_3 */
	{0x0D,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_4 */
	{0x0E,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_5 */
	{0x0F,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_6 */
	{0x10,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_7 */
	{0x11,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_8 */
	{0x12,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_9 */
	{0x13,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_10 */
	{0x14,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_11 */
	{0x15,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_12 */
	{0x16,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_13 */
	{0x17,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_14 */
	{0x18,   0x0000, 2, AD7124_RW}, /* AD7124_Channel_15 */
	//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=128
	{0x19,   0x01F7, 2, AD7124_RW}, /* AD7124_Config_0 */
	//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=16
	{0x1A,   0x01F4, 2, AD7124_RW}, /* AD7124_Config_1 */
	//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=4
	{0x1B,   0x01F2, 2, AD7124_RW}, /* AD7124_Config_2 */
	//使能单极性、REF_BUF、AIN_BUF缓冲和REF_SEL内部基准、PGA=1
	{0x1C,   0x01F0, 2, AD7124_RW}, /* AD7124_Config_3 */
	{0x1D,   0x09F0, 2, AD7124_RW}, /* AD7124_Config_4 */
	{0x1E,   0x09F0, 2, AD7124_RW}, /* AD7124_Config_5 */
	{0x1F,   0x09F0, 2, AD7124_RW}, /* AD7124_Config_6 */
	{0x20,   0x09F0, 2, AD7124_RW}, /* AD7124_Config_7 */
	{0x21, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_0 */
	{0x22, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_1 */
	{0x23, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_2 */
	{0x24, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_3 */
	{0x25, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_4 */
	{0x26, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_5 */
	{0x27, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_6 */
	{0x28, 0x160180, 3, AD7124_RW}, /* AD7124_Filter_7 */
	{0x29, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_0 */
	{0x2A, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_1 */
	{0x2B, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_2 */
	{0x2C, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_3 */
	{0x2D, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_4 */
	{0x2E, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_5 */
	{0x2F, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_6 */
	{0x30, 0x800000, 3, AD7124_RW}, /* AD7124_Offset_7 */
	//增益寄存器
	{0x31, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_0 */
	//增益寄存器
	{0x32, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_1 */
	//增益寄存器
	{0x33, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_2 */
	//增益寄存器
	{0x34, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_3 */
	{0x35, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_4 */
	{0x36, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_5 */
	{0x37, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_6 */
	{0x38, 0x500000, 3, AD7124_RW}, /* AD7124_Gain_7 */
};
/*! AD7124 registers list*/
enum ad7124_registers 
{
	AD7124_Status = 0x00,
	AD7124_ADC_CONTROL,
	AD7124_Data,
	AD7124_IOCONTROL_1,
	AD7124_IOCONTROL_2,
	AD7124_ID,
	AD7124_Error,
	AD7124_ERROR_EN,
	AD7124_MCLK_COUNT,
	AD7124_CHANNEL_0,
	AD7124_CHANNEL_1,
	AD7124_CHANNEL_2,
	AD7124_CHANNEL_3,
	AD7124_CHANNEL_4,
	AD7124_CHANNEL_5,
	AD7124_CHANNEL_6,
	AD7124_CHANNEL_7,
	AD7124_CHANNEL_8,
	AD7124_CHANNEL_9,
	AD7124_CHANNEL_10,
	AD7124_CHANNEL_11,
	AD7124_CHANNEL_12,
	AD7124_CHANNEL_13,
	AD7124_CHANNEL_14,
	AD7124_CHANNEL_15,
	AD7124_CONFIG_0,
	AD7124_CONFIG_1,
	AD7124_CONFIG_2,
	AD7124_CONFIG_3,
	AD7124_CONFIG_4,
	AD7124_CONFIG_5,
	AD7124_CONFIG_6,
	AD7124_CONFIG_7,
	AD7124_FILTER_0,
	AD7124_FILTER_1,
	AD7124_FILTER_2,
	AD7124_FILTER_3,
	AD7124_FILTER_4,
	AD7124_FILTER_5,
	AD7124_FILTER_6,
	AD7124_FILTER_7,
	AD7124_OFFSET_0,
	AD7124_OFFSET_1,
	AD7124_OFFSET_2,
	AD7124_OFFSET_3,
	AD7124_OFFSET_4,
	AD7124_OFFSET_5,
	AD7124_OFFSET_6,
	AD7124_OFFSET_7,
	AD7124_GAIN_0,
	AD7124_GAIN_1,
	AD7124_GAIN_2,
	AD7124_GAIN_3,
	AD7124_GAIN_4,
	AD7124_GAIN_5,
	AD7124_GAIN_6,
	AD7124_GAIN_7,
	AD7124_REG_END
};
#endif /* __AD7124_H__ */

 Device Drivers  --->
 [*] Network device support  --->
 [*]   Ethernet (10 or 100Mbit)  ---> 
 <*>   CS8900 support  

#ifndef CS8900_H
#define CS8900_H

/*
 * linux/drivers/net/cs8900.h
 *
 * Author: Abraham van der Merwe <abraham at 2d3d.co.za>
 *
 * A Cirrus Logic CS8900A driver for Linux
 * based on the cs89x0 driver written by Russell Nelson,
 * Donald Becker, and others.
 *
 * This source code is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

/*
 * Ports
 */

#define PP_Address  0x0a /* PacketPage Pointer Port (Section 4.10.10) */
#define PP_Data   0x0c /* PacketPage Data Port (Section 4.10.10) */

/*
 * Registers
 */

#define PP_ProductID  0x0000 /* Section 4.3.1   Product Identification Code */
#define PP_MemBase   0x002c /* Section 4.9.2   Memory Base Address Register */
#define PP_IntNum   0x0022 /* Section 3.2.3   Interrupt Number */
#define PP_EEPROMCommand 0x0040 /* Section 4.3.11  EEPROM Command */
#define PP_EEPROMData  0x0042 /* Section 4.3.12  EEPROM Data */
#define PP_RxCFG   0x0102 /* Section 4.4.6   Receiver Configuration */
#define PP_RxCTL   0x0104 /* Section 4.4.8   Receiver Control */
#define PP_TxCFG   0x0106 /* Section 4.4.9   Transmit Configuration */
#define PP_BufCFG   0x010a /* Section 4.4.12  Buffer Configuration */
#define PP_LineCTL   0x0112 /* Section 4.4.16  Line Control */
#define PP_SelfCTL   0x0114 /* Section 4.4.18  Self Control */
#define PP_BusCTL   0x0116 /* Section 4.4.20  Bus Control */
#define PP_TestCTL   0x0118 /* Section 4.4.22  Test Control */
#define PP_ISQ    0x0120 /* Section 4.4.5   Interrupt Status Queue */
#define PP_TxEvent   0x0128 /* Section 4.4.10  Transmitter Event */
#define PP_BufEvent   0x012c /* Section 4.4.13  Buffer Event */
#define PP_RxMISS   0x0130 /* Section 4.4.14  Receiver Miss Counter */
#define PP_TxCOL   0x0132 /* Section 4.4.15  Transmit Collision Counter */
#define PP_SelfST   0x0136 /* Section 4.4.19  Self Status */
#define PP_BusST   0x0138 /* Section 4.4.21  Bus Status */
#define PP_TxCMD   0x0144 /* Section 4.4.11  Transmit Command */
#define PP_TxLength   0x0146 /* Section 4.5.2   Transmit Length */
#define PP_IA    0x0158 /* Section 4.6.2   Individual Address (IEEE Address) */
#define PP_RxStatus   0x0400 /* Section 4.7.1   Receive Status */
#define PP_RxLength   0x0402 /* Section 4.7.1   Receive Length (in bytes) */
#define PP_RxFrame   0x0404 /* Section 4.7.2   Receive Frame Location */
#define PP_TxFrame   0x0a00 /* Section 4.7.2   Transmit Frame Location */

/*
 * Values
 */

/* PP_IntNum */
#define INTRQ0   0x0000
#define INTRQ1   0x0001
#define INTRQ2   0x0002
#define INTRQ3   0x0003

/* PP_ProductID */
#define EISA_REG_CODE 0x630e
#define REVISION(x)  (((x) & 0x1f00) >> 8)
#define VERSION(x)  ((x) & ~0x1f00)

#define CS8900A   0x0000
#define REV_B   7
#define REV_C   8
#define REV_D   9

/* PP_RxCFG */
#define Skip_1   0x0040
#define StreamE   0x0080
#define RxOKiE   0x0100
#define RxDMAonly  0x0200
#define AutoRxDMAE  0x0400
#define BufferCRC  0x0800
#define CRCerroriE  0x1000
#define RuntiE   0x2000
#define ExtradataiE  0x4000

/* PP_RxCTL */
#define IAHashA   0x0040
#define PromiscuousA 0x0080
#define RxOKA   0x0100
#define MulticastA  0x0200
#define IndividualA  0x0400
#define BroadcastA  0x0800
#define CRCerrorA  0x1000
#define RuntA   0x2000
#define ExtradataA  0x4000

/* PP_TxCFG */
#define Loss_of_CRSiE 0x0040
#define SQErroriE  0x0080
#define TxOKiE   0x0100
#define Out_of_windowiE 0x0200
#define JabberiE  0x0400
#define AnycolliE  0x0800
#define T16colliE  0x8000

/* PP_BufCFG */
#define SWint_X   0x0040
#define RxDMAiE   0x0080
#define Rdy4TxiE  0x0100
#define TxUnderruniE 0x0200
#define RxMissiE  0x0400
#define Rx128iE   0x0800
#define TxColOvfiE  0x1000
#define MissOvfloiE  0x2000
#define RxDestiE  0x8000

/* PP_LineCTL */
#define SerRxON   0x0040
#define SerTxON   0x0080
#define AUIonly   0x0100
#define AutoAUI_10BT 0x0200
#define ModBackoffE  0x0800
#define PolarityDis  0x1000
#define L2_partDefDis 0x2000
#define LoRxSquelch  0x4000

/* PP_SelfCTL */
#define RESET   0x0040
#define SWSuspend  0x0100
#define HWSleepE  0x0200
#define HWStandbyE  0x0400
#define HC0E   0x1000
#define HC1E   0x2000
#define HCB0   0x4000
#define HCB1   0x8000

/* PP_BusCTL */
#define ResetRxDMA  0x0040
#define DMAextend  0x0100
#define UseSA   0x0200
#define MemoryE   0x0400
#define DMABurst  0x0800
#define IOCHRDYE  0x1000
#define RxDMAsize  0x2000
#define EnableRQ  0x8000

/* PP_TestCTL */
#define DisableLT  0x0080
#define ENDECloop  0x0200
#define AUIloop   0x0400
#define DisableBackoff 0x0800
#define FDX    0x4000

/* PP_ISQ */
#define RegNum(x) ((x) & 0x3f)
#define RegContent(x) ((x) & ~0x3d)

#define RxEvent   0x0004
#define TxEvent   0x0008
#define BufEvent  0x000c
#define RxMISS   0x0010
#define TxCOL   0x0012

/* PP_RxStatus */
#define IAHash   0x0040
#define Dribblebits  0x0080
#define RxOK   0x0100
#define Hashed   0x0200
#define IndividualAdr 0x0400
#define Broadcast  0x0800
#define CRCerror  0x1000
#define Runt   0x2000
#define Extradata  0x4000

#define HashTableIndex(x) ((x) >> 0xa)

/* PP_TxCMD */
#define After5   0
#define After381  1
#define After1021  2
#define AfterAll  3
#define TxStart(x) ((x) << 6)

#define Force   0x0100
#define Onecoll   0x0200
#define InhibitCRC  0x1000
#define TxPadDis  0x2000

/* PP_BusST */
#define TxBidErr  0x0080
#define Rdy4TxNOW  0x0100

/* PP_TxEvent */
#define Loss_of_CRS  0x0040
#define SQEerror  0x0080
#define TxOK   0x0100
#define Out_of_window 0x0200
#define Jabber   0x0400
#define T16coll   0x8000

#define TX_collisions(x) (((x) >> 0xb) & ~0x8000)

/* PP_BufEvent */
#define SWint   0x0040
#define RxDMAFrame  0x0080
#define Rdy4Tx   0x0100
#define TxUnderrun  0x0200
#define RxMiss   0x0400
#define Rx128   0x0800
#define RxDest   0x8000

/* PP_RxMISS */
#define MissCount(x) ((x) >> 6)

/* PP_TxCOL */
#define ColCount(x) ((x) >> 6)

/* PP_SelfST */
#define T3VActive  0x0040
#define INITD   0x0080
#define SIBUSY   0x0100
#define EEPROMpresent 0x0200
#define EEPROMOK  0x0400
#define ELpresent  0x0800
#define EEsize   0x1000

/* PP_EEPROMCommand */
#define EEWriteEnable   0x00F0
#define EEWriteDisable  0x0000
#define EEWriteRegister 0x0100
#define EEReadRegister 0x0200
#define EEEraseRegister 0x0300
#define ELSEL   0x0400

#endif /* #ifndef CS8900_H */

/*
 * linux/drivers/net/cs8900.c
 *
 * Author: Abraham van der Merwe <abraham at 2d3d.co.za>
 *
 * A Cirrus Logic CS8900A driver for Linux
 * based on the cs89x0 driver written by Russell Nelson,
 * Donald Becker, and others.
 *
 * This source code is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * History:
 *    22-May-2002  Initial version (Abraham vd Merwe)
 *    30-May-2002  Added char device support for eeprom (Frank Becker)
 *    24-Jan-2004  Fixups for 2.6 (Frank Becker)
 *   15-July-2004 Modified for SMDK2410 (Roc Wu pwu at jadechip.com)
 */
 
#define VERSION_STRING "Cirrus Logic CS8900A driver for Linux (Modified for SMDK2410)"

/*
 * At the moment the driver does not support memory mode operation.
 * It is trivial to implement this, but not worth the effort.
 */

/*
 * TODO:
 *
 *   1. Sort out ethernet checksum
 *   2. If !ready in send_start(), queue buffer and send it in interrupt handler
 *      when we receive a BufEvent with Rdy4Tx, send it again. dangerous!
 *   3. how do we prevent interrupt handler destroying integrity of get_stats()?
 *   4. Change reset code to check status.
 *   5. Implement set_mac_address and remove fake mac address
 *   7. Link status detection stuff
 *   8. Write utility to write EEPROM, do self testing, etc.
 *   9. Implement DMA routines (I need a board w/ DMA support for that)
 *  10. Power management
 *  11. Add support for multiple ethernet chips
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/irq.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/fs.h>

// Added BSt
#include <asm/mach-types.h>

 

#ifdef CONFIG_ARCH_SMDK2410
#include "asm/arch-s3c2410/regs-irq.h"
#include "asm/arch/regs-mem.h"
//#include "asm/arch/smdk2410.h"
#include "asm/plat-s3c24xx/common-smdk.h"
#endif

#include "cs8900.h"

//#define FULL_DUPLEX
//#define DEBUG

typedef struct {
 struct net_device_stats stats;
 u16 txlen;
 int char_devnum;

        spinlock_t lock;
} cs8900_t;

int cs8900_probe (struct net_device *dev);
static struct net_device *cs8900_dev ;


/*
 * There seems to be no way to determine the exact size of the eeprom,
 * so we use the largest size.
 * FIXME: Verify it's safe to read/write past the end of a 64/128
 *        byte eeprom.
 *
 * Possible eeprom sizes:
 * Cx46 -  64 bytes
 * Cx56 - 128 bytes
 * Cx66 - 256 bytes
 */
#define MAX_EEPROM_SIZE  256

 

/*
 * I/O routines
 */

static inline u16 cs8900_read (struct net_device *dev,u16 reg)
{
 outw (reg,dev->base_addr + PP_Address);
 return (inw (dev->base_addr + PP_Data));
}

static inline void cs8900_write (struct net_device *dev,u16 reg,u16 value)
{
 outw (reg,dev->base_addr + PP_Address);
 outw (value,dev->base_addr + PP_Data);
}

static inline void cs8900_set (struct net_device *dev,u16 reg,u16 value)
{
 cs8900_write (dev,reg,cs8900_read (dev,reg) | value);
}

static inline void cs8900_clear (struct net_device *dev,u16 reg,u16 value)
{
 cs8900_write (dev,reg,cs8900_read (dev,reg) & ~value);
}

static inline void cs8900_frame_read (struct net_device *dev,struct sk_buff *skb,u16 length)
{
 insw (dev->base_addr,skb_put (skb,length),(length + 1) / 2);
}

static inline void cs8900_frame_write (struct net_device *dev,struct sk_buff *skb)
{
 outsw (dev->base_addr,skb->data,(skb->len + 1) / 2);
}

/*
 * Debugging functions
 */

#ifdef DEBUG
static inline int printable (int c)
{
 return ((c >= 32 && c <= 126) ||
   (c >= 174 && c <= 223) ||
   (c >= 242 && c <= 243) ||
   (c >= 252 && c <= 253));
}

static void dump16 (struct net_device *dev,const u8 *s,size_t len)
{
 int i;
 char str[128];

 if (!len) return;

 *str = '\0';

 for (i = 0; i < len; i++) {
  if (i && !(i % 4)) strcat (str," ");
  sprintf (str,"%s%.2x ",str,s[i]);
 }

 for ( ; i < 16; i++) {
  if (i && !(i % 4)) strcat (str," ");
  strcat (str,"   ");
 }

 strcat (str," ");
 for (i = 0; i < len; i++) sprintf (str,"%s%c",str,printable (s[i]) ? s[i] : '.');

 printk (KERN_DEBUG "%s:     %s\n",dev->name,str);
}

static void hexdump (struct net_device *dev,const void *ptr,size_t size)
{
 const u8 *s = (u8 *) ptr;
 int i;
 for (i = 0; i < size / 16; i++, s += 16) dump16 (dev,s,16);
 dump16 (dev,s,size % 16);
}

static void dump_packet (struct net_device *dev,struct sk_buff *skb,const char *type)
{
 printk (KERN_INFO "%s: %s %d byte frame %.2x:%.2x:%.2x:%.2x:%.2x:%.2x to %.2x:%.2x:%.2x:%.2x:%.2x:%.2x type %.4x\n",
   dev->name,
   type,
   skb->len,
   skb->data[0],skb->data[1],skb->data[2],skb->data[3],skb->data[4],skb->data[5],
   skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11],
   (skb->data[12] << 8) | skb->data[13]);
 if (skb->len < 0x100) hexdump (dev,skb->data,skb->len);
}


#endif /* #ifdef DEBUG */

/*
 * Driver functions
 */

static void cs8900_receive (struct net_device *dev)
{
 cs8900_t *priv = (cs8900_t *) dev->priv;
 struct sk_buff *skb;
 u16 status,length;

 status = cs8900_read (dev,PP_RxStatus);
 length = cs8900_read (dev,PP_RxLength);

 if (!(status & RxOK)) {
  priv->stats.rx_errors++;
  if ((status & (Runt | Extradata))) priv->stats.rx_length_errors++;
  if ((status & CRCerror)) priv->stats.rx_crc_errors++;
  return;
 }

 if ((skb = dev_alloc_skb (length + 4)) == NULL) {
  priv->stats.rx_dropped++;
  return;
 }

 skb->dev = dev;
 skb_reserve (skb,2);

 cs8900_frame_read (dev,skb,length);

#ifdef FULL_DUPLEX
 dump_packet (dev,skb,"recv");
#endif /* #ifdef FULL_DUPLEX */

 skb->protocol = eth_type_trans (skb,dev);

 netif_rx (skb);
 dev->last_rx = jiffies;

 priv->stats.rx_packets++;
 priv->stats.rx_bytes += length;
}

static int cs8900_send_start (struct sk_buff *skb,struct net_device *dev)
{
 cs8900_t *priv = (cs8900_t *) dev->priv;
 u16 status;

 spin_lock_irq(&priv->lock);
 netif_stop_queue (dev);

 cs8900_write (dev,PP_TxCMD,TxStart (After5));
 cs8900_write (dev,PP_TxLength,skb->len);

 status = cs8900_read (dev,PP_BusST);

 if ((status & TxBidErr)) {
  spin_unlock_irq(&priv->lock);
  printk (KERN_WARNING "%s: Invalid frame size %d!\n",dev->name,skb->len);
  priv->stats.tx_errors++;
  priv->stats.tx_aborted_errors++;
  priv->txlen = 0;
  return (1);
 }

 if (!(status & Rdy4TxNOW)) {
  spin_unlock_irq(&priv->lock);
  printk (KERN_WARNING "%s: Transmit buffer not free!\n",dev->name);
  priv->stats.tx_errors++;
  priv->txlen = 0;
  /* FIXME: store skb and send it in interrupt handler */
  return (1);
 }

 cs8900_frame_write (dev,skb);
 spin_unlock_irq(&priv->lock);

#ifdef DEBUG
 dump_packet (dev,skb,"send");
#endif /* #ifdef DEBUG */

 dev->trans_start = jiffies;

 dev_kfree_skb (skb);

 priv->txlen = skb->len;

 return (0);
}

static irqreturn_t cs8900_interrupt (int irq,void *id)
{
 struct net_device *dev = (struct net_device *) id;
 cs8900_t *priv;
 volatile u16 status;
  irqreturn_t handled = 0;


 if (dev->priv == NULL) {
  printk (KERN_WARNING "%s: irq %d for unknown device.\n",dev->name,irq);
  return 0;
 }

 priv = (cs8900_t *) dev->priv;
 
 while ((status = cs8900_read (dev, PP_ISQ))) {
  handled = 1;
  switch (RegNum (status)) {
  case RxEvent:
   cs8900_receive (dev);
   break;

  case TxEvent:
   priv->stats.collisions += ColCount (cs8900_read (dev,PP_TxCOL));
   if (!(RegContent (status) & TxOK)) {
    priv->stats.tx_errors++;
    if ((RegContent (status) & Out_of_window)) priv->stats.tx_window_errors++;
    if ((RegContent (status) & Jabber)) priv->stats.tx_aborted_errors++;
    break;
   } else if (priv->txlen) {
    priv->stats.tx_packets++;
    priv->stats.tx_bytes += priv->txlen;
   }
   priv->txlen = 0;
   netif_wake_queue (dev);
   break;

  case BufEvent:
   if ((RegContent (status) & RxMiss)) {
    u16 missed = MissCount (cs8900_read (dev,PP_RxMISS));
    priv->stats.rx_errors += missed;
    priv->stats.rx_missed_errors += missed;
   }
   if ((RegContent (status) & TxUnderrun)) {
    priv->stats.tx_errors++;
    priv->stats.tx_fifo_errors++;

    priv->txlen = 0;
    netif_wake_queue (dev);
   }
   /* FIXME: if Rdy4Tx, transmit last sent packet (if any) */
   break;

  case TxCOL:
   priv->stats.collisions += ColCount (cs8900_read (dev,PP_TxCOL));
   break;

  case RxMISS:
   status = MissCount (cs8900_read (dev,PP_RxMISS));
   priv->stats.rx_errors += status;
   priv->stats.rx_missed_errors += status;
   break;
  }
 }
 return IRQ_RETVAL(handled);
}

static void cs8900_transmit_timeout (struct net_device *dev)
{
 cs8900_t *priv = (cs8900_t *) dev->priv;
 priv->stats.tx_errors++;
 priv->stats.tx_heartbeat_errors++;
 priv->txlen = 0;
 netif_wake_queue (dev);
}

static int cs8900_start (struct net_device *dev)
{
 int result;

 set_irq_type(dev->irq, IRQT_RISING);

 /* enable the ethernet controller */
 cs8900_set (dev,PP_RxCFG,RxOKiE | BufferCRC | CRCerroriE | RuntiE | ExtradataiE);
 cs8900_set (dev,PP_RxCTL,RxOKA | IndividualA | BroadcastA);
 cs8900_set (dev,PP_TxCFG,TxOKiE | Out_of_windowiE | JabberiE);
 cs8900_set (dev,PP_BufCFG,Rdy4TxiE | RxMissiE | TxUnderruniE | TxColOvfiE | MissOvfloiE);
 cs8900_set (dev,PP_LineCTL,SerRxON | SerTxON);
 cs8900_set (dev,PP_BusCTL,EnableRQ);

#ifdef FULL_DUPLEX
 cs8900_set (dev,PP_TestCTL,FDX);
#endif /* #ifdef FULL_DUPLEX */
 udelay(200); 
 /* install interrupt handler */
 if ((result = request_irq (dev->irq, &cs8900_interrupt, 0, dev->name, dev)) < 0) {
  printk (KERN_ERR "%s: could not register interrupt %d\n",dev->name, dev->irq);
  return (result);
 }
 
 /* start the queue */
 netif_start_queue (dev);

 return (0);
}

static int cs8900_stop (struct net_device *dev)
{
 /* disable ethernet controller */
 cs8900_write (dev,PP_BusCTL,0);
 cs8900_write (dev,PP_TestCTL,0);
 cs8900_write (dev,PP_SelfCTL,0);
 cs8900_write (dev,PP_LineCTL,0);
 cs8900_write (dev,PP_BufCFG,0);
 cs8900_write (dev,PP_TxCFG,0);
 cs8900_write (dev,PP_RxCTL,0);
 cs8900_write (dev,PP_RxCFG,0);

 /* uninstall interrupt handler */
 free_irq (dev->irq,dev);

 /* stop the queue */
 netif_stop_queue (dev);

 return (0);
}

static struct net_device_stats *cs8900_get_stats (struct net_device *dev)
{
 cs8900_t *priv = (cs8900_t *) dev->priv;
 return (&priv->stats);
}

static void cs8900_set_receive_mode (struct net_device *dev)
{
 if ((dev->flags & IFF_PROMISC))
  cs8900_set (dev,PP_RxCTL,PromiscuousA);
 else
  cs8900_clear (dev,PP_RxCTL,PromiscuousA);

 if ((dev->flags & IFF_ALLMULTI) && dev->mc_list)
  cs8900_set (dev,PP_RxCTL,MulticastA);
 else
  cs8900_clear (dev,PP_RxCTL,MulticastA);
}

 

 

/*
 * Driver initialization routines
 */

int __init cs8900_probe (struct net_device *dev)
{
 static cs8900_t priv;
 int i,result;
 u16 value;

 printk (VERSION_STRING"\n");

 memset (&priv,0,sizeof (cs8900_t));

 //+kevin
// __raw_writel(0x2211d110,S3C2410_BWSCON);
// __raw_writel(0x1f7c,S3C2410_BANKCON3);

 

#if defined(CONFIG_ARCH_SMDK2410)
 dev->dev_addr[0] = 0x00;
 dev->dev_addr[1] = 0x00;
 dev->dev_addr[2] = 0x3e;
 dev->dev_addr[3] = 0x26;
 dev->dev_addr[4] = 0x0a;
 dev->dev_addr[5] = 0x00;

#endif

 dev->if_port   = IF_PORT_10BASET;
 dev->priv      = (void *) &priv;

 spin_lock_init(&priv.lock);

 //hejiasheng SET_MODULE_OWNER (dev);

 

 

#if defined(CONFIG_ARCH_SMDK2410)
 dev->base_addr = vSMDK2410_ETH_IO + 0x300;
 dev->irq = IRQ_EINT9;
#endif /* #if defined(CONFIG_ARCH_SMDK2410) */

 

 if ((result = check_mem_region (dev->base_addr, 16))) {
  printk (KERN_ERR "%s: can't get I/O port address 0x%lx\n",dev->name,dev->base_addr);
  return (result);
 }
 request_mem_region (dev->base_addr, 16, dev->name);
 
     /* verify EISA registration number for Cirrus Logic */
 if ((value = cs8900_read (dev,PP_ProductID)) != EISA_REG_CODE) {
  printk (KERN_ERR "%s: incorrect signature 0x%.4x\n",dev->name,value);
  return (-ENXIO);
 }

 /* verify chip version */
 value = cs8900_read (dev,PP_ProductID + 2);
 if (VERSION (value) != CS8900A) {
  printk (KERN_ERR "%s: unknown chip version 0x%.8x\n",dev->name,VERSION (value));
  return (-ENXIO);
 }
 /* setup interrupt number */
 cs8900_write (dev,PP_IntNum,0);


 printk (KERN_INFO "%s: CS8900A rev %c at %#lx irq=%d",
  dev->name,'B' + REVISION (value) - REV_B, dev->base_addr, dev->irq);

 for (i = 0; i < ETH_ALEN; i += 2)
  cs8900_write (dev,PP_IA + i,dev->dev_addr[i] | (dev->dev_addr[i + 1] << 8));

 printk (", addr:");
 for (i = 0; i < ETH_ALEN; i += 2)
 {
  u16 mac = cs8900_read (dev,PP_IA + i);
  printk ("%c%02X:%2X", (i==0)?' ':':', mac & 0xff, (mac >> 8));
 }
 printk ("\n");

 return (0);
}

static int __init cs8900_init (void)
{
 struct net_device *ndev;

        ndev = alloc_etherdev(sizeof (cs8900_t));
        if (!ndev) {
                printk("%s: could not allocate device.\n", "cs8900");
                return -ENOMEM;
        }

 cs8900_dev = ndev;
 cs8900_dev->init = cs8900_probe;
 ether_setup (ndev);

 ndev->open               = cs8900_start;
 ndev->stop               = cs8900_stop;
 ndev->hard_start_xmit    = cs8900_send_start;
 ndev->get_stats          = cs8900_get_stats;
 ndev->set_multicast_list = cs8900_set_receive_mode;
 ndev->tx_timeout         = cs8900_transmit_timeout;
 ndev->watchdog_timeo     = HZ;

 

 return (register_netdev (cs8900_dev));
}

static void __exit cs8900_cleanup (void)
{
 cs8900_t *priv = (cs8900_t *) cs8900_dev->priv;
 if( priv->char_devnum)
 {
  unregister_chrdev(priv->char_devnum,"cs8900_eeprom");
 }
 release_mem_region (cs8900_dev->base_addr,16);
 unregister_netdev (cs8900_dev);
}

MODULE_AUTHOR ("Abraham van der Merwe <abraham at 2d3d.co.za>");
MODULE_DESCRIPTION (VERSION_STRING);
MODULE_LICENSE ("GPL");

module_init (cs8900_init);
module_exit (cs8900_cleanup);

/*******************************************************************************
 *
 * Filename: xmodem.c
 *
 * change from KB9202 , yuanxihua@21cn.com
 ******************************************************************************/

#include <common.h>

extern int xmodem_rx(char *dest);

/* Line control codes */
#define SOH   0x01 /* start of header for Xmodem protocol  */
#define STX   0x02 /* start of header for 1K xmodem protocol*/
#define ACK   0x06 /* Acknowledge */
#define NAK   0x15 /* Negative acknowledge */
#define CAN   0x18 /* Cancel */
#define EOT   0x04 /* end of text */
#define TIMEOUT 2
#define TIMEOUT_LONG 10
#define XMODEM_DATA_SIZE_SOH 128  /* for Xmodem protocol */
#define XMODEM_DATA_SIZE_STX 1024 /* for 1K xmodem protocol */

enum {
 INVALID_STATE = 0,
 WAITING_START,
 WAIT_HEAD,
 RX_PACKET,
 RX_EOT,
 SEND_NAK
};

static char packetNumber;
static int PACKET_SIZE;
static char HEAD;

#define TransitionState(x, y) (x = y)

void DebugPutc(char cValue)
{
 putc (cValue & 0x1FF);
}
int WaitForChar(char *cPtr, int seconds)
{
   unsigned long counter = 0;
   
   seconds = seconds * 1000 ;  /* delay 1000 * 50 * 20us */
   
   while (!tstc () && (counter < seconds * 50 ))
    {
      udelay (20);
      counter++;
    }
  if (tstc ())
    {
      *cPtr = getc ();
      return 1;
    }
  return 0;
}
static int GetRecord(char blocknum, char *dest) {
 int  size;
 char  nextChar;
 unsigned chk, j;

 chk = 0;

 if (!WaitForChar(&nextChar, TIMEOUT)) {
  return (0);
 }

 if ((char)nextChar != (char)~blocknum) {
  return (0);
 }

 for (size = 0; size < PACKET_SIZE; ++size) {
  if (!WaitForChar(&nextChar, TIMEOUT)) {
   return (0);
  }
  chk = chk ^(int)nextChar << 8;
  for (j = 0; j < 8; ++j) {
   if (chk & 0x8000)
    chk = chk << 1 ^ 0x1021;
   else
    chk = chk << 1;
  }
  *dest++ = nextChar;
 }

 chk &= 0xFFFF;

 if ((!WaitForChar(&nextChar, TIMEOUT)) || (nextChar != ((chk >> 8) & 0xFF))) {
  return (0);
 }

 if ((!WaitForChar(&nextChar, TIMEOUT)) || (nextChar != (chk & 0xFF))) {
  return (0);
 }

 DebugPutc(ACK);

 return (1);
}
int xmodem_rx(char *dest) {

 int  state;
 char  nextChar, *startAddress = dest;

 packetNumber = 1;
 state = WAITING_START;
 PACKET_SIZE = XMODEM_DATA_SIZE_SOH;
 HEAD = SOH;
      
 while (1) {

  if (state == WAITING_START) {
   DebugPutc('C');
   if (WaitForChar(&nextChar, TIMEOUT)) {
    if (nextChar == SOH)
    {
      PACKET_SIZE = XMODEM_DATA_SIZE_SOH;
      HEAD = SOH;
      TransitionState(state, RX_PACKET);
    }
    else
    if (nextChar == STX)
    {
      PACKET_SIZE = XMODEM_DATA_SIZE_STX;
      HEAD = STX;
      TransitionState(state, RX_PACKET);
    }
   }
  }

  if (state == WAIT_HEAD) {
   if (!WaitForChar(&nextChar, TIMEOUT_LONG)) {
    return (-1);
   }

/*   if (nextChar == HEAD) {
    TransitionState(state, RX_PACKET);
   }
*/
    if (nextChar == SOH)
    {
      PACKET_SIZE = XMODEM_DATA_SIZE_SOH;
      HEAD = SOH;
      TransitionState(state, RX_PACKET);
    }
    else
    if (nextChar == STX)
    {
      PACKET_SIZE = XMODEM_DATA_SIZE_STX;
      HEAD = STX;
      TransitionState(state, RX_PACKET);
    }
    
   if (nextChar == EOT) {
    // TransitionState(state, RX_EOT);
    DebugPutc(ACK);
    return (dest - startAddress);
   }
  }

  if (state == RX_PACKET) {
   if (!WaitForChar(&nextChar, TIMEOUT)) {
    return (-1);
   }

   if (nextChar != packetNumber) {
    // TransitionState(state, SEND_NAK);
    DebugPutc(NAK);
    return (-1);
   }

   if (GetRecord(packetNumber, dest)) {
    dest += PACKET_SIZE;
    ++packetNumber;
    TransitionState(state, WAIT_HEAD);
   } else {
    return (-1);
   }
  }
 }

 // the loop above should return in all cases
 return (-1);
}

#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>

static ulong load_xmodem_bin(ulong *);
static char *bin_start_address;

int do_xmodem(cmd_tbl_t *cmdtp,int flag,int argc, char *argv[])
{
 DECLARE_GLOBAL_DATA_PTR;

 ulong offset = 0;
 ulong addr;
 int load_baudrate, current_baudrate;
 int rcode = 0;
 char *s;

 /* pre-set offset from CFG_LOAD_ADDR */
 offset = CFG_LOAD_ADDR;

 /* pre-set offset from $loadaddr */
 if ((s = getenv("loadaddr")) != NULL) {
  offset = simple_strtoul(s, NULL, 16);
 }

 load_baudrate = current_baudrate = gd->baudrate;

 if (argc >= 2) {
  offset = simple_strtoul(argv[1], NULL, 16);
 }
 if (argc == 3) {
  load_baudrate = (int)simple_strtoul(argv[2], NULL, 10);

  /* default to current baudrate */
  if (load_baudrate == 0)
   load_baudrate = current_baudrate;
 }

 if (load_baudrate != current_baudrate) {
  printf ("## Switch baudrate to %d bps and press ENTER ...\n",
   load_baudrate);
  udelay(50000);
  gd->baudrate = load_baudrate;
  serial_setbrg ();
  udelay(50000);
  for (;;) {
   if (getc() == '\r')
    break;
  }
 }

 printf ("## Ready for binary (xmodem) download "
  "to 0x%08lX at %d bps...\n",
  offset,
  load_baudrate);

 addr = load_xmodem_bin((ulong *) offset);
 
 if (addr == ~0) {
  load_addr = 0;
  printf ("## Binary (xmodem) download aborted\n");
  rcode = 1;
 } else {
  printf ("## Start Addr      = 0x%08lX\n", addr);
  load_addr = addr;
 }

 if (load_baudrate != current_baudrate) {
  printf ("## Switch baudrate to %d bps and press ESC ...\n",
   current_baudrate);
  udelay (50000);
  gd->baudrate = current_baudrate;
  serial_setbrg ();
  udelay (50000);
  for (;;) {
   if (getc() == 0x1B) /* ESC */
    break;
  }
 }

#ifdef CONFIG_AUTOSCRIPT
 if (load_addr) {
  char *s;

  if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) {
   printf("Running autoscript at addr 0x%08lX ...\n", load_addr);
   rcode = autoscript (load_addr);
  }
 }
#endif
 return rcode;
}

static ulong load_xmodem_bin(unsigned long *addr)
{
 int size, i;
 char buf[32];
 ulong offset;
 
// set_kerm_bin_mode ((ulong *) offset);
// size = k_recv ();
  offset = addr;
  bin_start_address = (char *) addr;
  size = xmodem_rx(bin_start_address);

 /*
  * Gather any trailing characters (for instance, the ^D which
  * is sent by 'cu' after sending a file), and give the
  * box some time (100 * 1 ms)
  */
 for (i=0; i<100; ++i) {
  if (tstc()) {
   (void) getc();
  }
  udelay(1000);
 }

 flush_cache (offset, size);

 printf("## Total Size      = 0x%08x = %d Bytes\n", size, size);
 sprintf(buf, "%X", size);
 setenv("filesize", buf);

 return offset;
}

U_BOOT_CMD(
  rx,    3,    0,     do_xmodem,
 "rx      - load binary file over serial line (xmodem)\n",
 "[ off ] [ baud ]\n"
 "    - load binary file over serial line"
 " with offset 'off' and baudrate 'baud'\n"
);

 

 config I2C_AT91
  tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
  depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
  help
    This supports the use of the I2C interface on Atmel AT91
    processors.
 
    This driver is BROKEN because the controller which it uses
    will easily trigger RX overrun and TX underrun errors.  Using
    low I2C clock rates may partially work around those issues
    on some systems.  Another serious problem is that there is no
    documented way to issue repeated START conditions, as needed
    to support combined I2C messages.  Use the i2c-gpio driver
    unless your system can cope with those limitations.
 

 Device Drivers  --->   
 <*> I2C support  --->  
 <*>   I2C device interface
    
       I2C Hardware Bus support  --->  
   <*> GPIO-based bitbanging I2C

//i2ctest.c

#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <errno.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>

#define CHIP_ADDR 0x50   //24C64
#define PAGE_SIZE 32
#define I2C_DEV  "/dev/i2c-0"

static int read_eeprom(int fd,char buff[],int addr,int count)
{
 int res;

 if (write(fd,&addr,1)!=1)
 {
  printf("Can't write %s's addr %d\n",I2C_DEV,addr);
  return -1;
 }
 res = read(fd,buff,count);
 printf("read %d bytes at 0x%02x\n\r",res,addr);
 return res;
}
static int write_eeprom(int fd,char buff[],int addr,int count)
{
 int res;
 int i;
 static char sendbuffer[PAGE_SIZE+1];

 memcpy(sendbuffer+1,buff,count);
 sendbuffer[0]=addr;
 
 res = write(fd,&addr,count+1);
 printf("write %d bytes at 0x%02x\n\r",res,addr);
 return res;
}

int main(void)
{
 int fd,i,res;
 unsigned char buf[PAGE_SIZE];
 
 printf("I2C Test version 1.0-9g9260 (yuanxihua@21cn.com) Buile on %s %s\n\r",__DATE__,__TIME__);
 
 fd=open(I2C_DEV,O_RDWR);
 if(fd<0)
 {
  printf("Can't Open %s !!!\n\r",I2C_DEV);
  return -1;
 }
 
 res = ioctl(fd,I2C_TENBIT,0);
 res = ioctl(fd,I2C_SLAVE,CHIP_ADDR);
 
 for(i=0;i<sizeof(buf);i++)
 {
//  write_eeprom(fd,buf,i,1);
 } 
 for(i=0;i<sizeof(buf);i++)
 {
  read_eeprom (fd,buf+i,i,1);
  printf("buf[0x%02x] = 0x%02x\n\r",i,buf[i]);
 }

 close(fd);
 return 0;
}

 /*
  * NAND flash
  */
 static struct mtd_partition __initdata ek_nand_partition[] = {
  {
   .name   = "Bootstrap",
   .offset = 0,
   .size   = 0x20000,
  },
  {
   .name   = "U-boot",
   .offset = 0x20000,
   .size   = 0xe0000,
  },
  {
   .name   = "uImage",
   .offset = 0x100000,
   .size   = 0x200000,
  },
  {
   .name   = "ramdisk",
   .offset = 0x300000,
   .size   = 0x400000,
  },
  {
   .name   = "rootfs",
   .offset = 0x700000,
   .size   = 0x900000,
  },
  {
   .name   = "data",
   .offset = 16 * 1024 * 1024,
   .size   = MTDPART_SIZ_FULL,
  },
 };

 root@yuanxh-desktop:/home/yuanxh/sam9260/linux-2.6.27-9g9260# make menuconfig

    Boot options  ---> 
  (mem=64M console=ttyS0,115200 root=/dev/mtdblock4 rootfstype=jffs2 init=/linuxrc)
  
 Device Drivers  --->
 <*> Memory Technology Device (MTD) support  --->
 <*>   MTD concatenating support
 [*]   MTD partitioning support
 [*]     Command line partition table parsing
 <*>   Direct char device access to MTD devices
 -*-   Common interface to block layer for MTD 'translation layers'
 <*>   Caching block device access to MTD devices 
 <*>   NAND Device Support  --->
 <*>   Support for NAND Flash / SmartMedia on AT91 and AVR32
         ECC management for NAND Flash / SmartMedia on AT91 / AVR32 (Software ECC)  --->

 File systems  --->
 <*> Second extended fs support
 Miscellaneous filesystems  --->
 <*> Journalling Flash File System v2 (JFFS2) support 
 (0)   JFFS2 debugging verbosity (0 = quiet, 2 = noisy) 
 [*]   JFFS2 write-buffering support
 [*]   JFFS2 summary support (EXPERIMENTAL)

 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"
 #include "stdio.h"
 #include "platform_config.h"
 
 /** @addtogroup StdPeriph_Examples
   * @{
   */
 
 /** @addtogroup USART_Printf
   * @{
   */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 
 /* Private function prototypes -----------------------------------------------*/
 void RT_Configuration(void);
 
 /* Private functions ---------------------------------------------------------*/
 
 
 /**
   * @brief  Configures the different GPIO ports.
   * @param  None
   * @retval : None
   */
 void RT_Configuration(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
   USART_InitTypeDef USART_InitStructure;
 
 #if defined USE_USART2 && defined USE_STM3210B_EVAL
   /* Enable AFIO clock */
   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
 
   /* Enable the USART2 Pins Software Remapping */
   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
 #endif
 
   /* Configure USARTx_Tx as alternate function push-pull */
   GPIO_InitStructure.GPIO_Pin = GPIO_TxPin;
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
   GPIO_Init(GPIOx, &GPIO_InitStructure);
 
   /* Configure USARTx_Rx as input floating */
   GPIO_InitStructure.GPIO_Pin = GPIO_RxPin;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
   GPIO_Init(GPIOx, &GPIO_InitStructure);
 
   /* USARTx configuration ------------------------------------------------------*/
   /* USARTx configured as follow:
         - BaudRate = 115200 baud 
         - Word Length = 8 Bits
         - One Stop Bit
         - No parity
         - Hardware flow control disabled (RTS and CTS signals)
         - Receive and transmit enabled
   */
   USART_InitStructure.USART_BaudRate = 115200;
   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
   USART_InitStructure.USART_StopBits = USART_StopBits_1;
   USART_InitStructure.USART_Parity = USART_Parity_No ;
   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
  
   /* Configure the USARTx */
   USART_Init(USARTx, &USART_InitStructure);
   /* Enable the USARTx */
   USART_Cmd(USARTx, ENABLE);
  
 }
 
 /**
   * @brief  Retargets the C library printf function to the USART.
   * @param  None
   * @retval : None
   */
 int fputc(int ch, FILE *f)
 {
   /* Write a character to the USART */
   USART_SendData(USARTx, (uint8_t) ch);
 
   /* Loop until the end of transmission */
   while(USART_GetFlagStatus(USARTx, USART_FLAG_TXE) == RESET)
   {
   }
 
   return ch;
 }
 /*******************************************************************************
 * Function Name  : fgetc
 * Description    : Get a key from the HyperTerminal
 * Input          : None
 * Output         : None
 * Return         : The Key Pressed
 *******************************************************************************/
 int fgetc(FILE *f)
 {
  /* Waiting for user input */
  while ( USART_GetFlagStatus(USARTx, USART_FLAG_RXNE) == RESET);
  return (uint8_t)USARTx->DR;
 }
B，修改D:\works\lccd-1.0.0\Source\main.c的int main(void)如下：
 int main(void)
 {
   /* System Clocks Configuration */
   RCC_Configuration();
 
   /* Configure the GPIO ports */
   RT_Configuration();
 
   /* Output a message on Hyperterminal using printf function */
   printf("\n\r\n\r\n\r\n\r");
   printf("*** LCCD V1.0 Build by y nxih @21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
   printf("*** LCCD V1.0 Rebooting ...\n\r");
 
   while (1)
   {
   }
 }

  DRESULT disk_ioctl (BYTE drv,BYTE ctrl, void *buff)
  {
   DRESULT res = RES_OK;
   uint32_t result;

      if (drv){ return RES_PARERR;}
   
      switch(ctrl)
      {
       case CTRL_SYNC:
           break;
    case GET_BLOCK_SIZE:
           *(DWORD*)buff = NAND_BLOCK_SIZE;
           break;
    case GET_SECTOR_COUNT:
           *(DWORD*)buff = (((NAND_MAX_ZONE/2) * NAND_ZONE_SIZE) * NAND_BLOCK_SIZE);
           break;
    case GET_SECTOR_SIZE:
           *(WORD*)buff = NAND_PAGE_SIZE;
           break;
       default:
           res = RES_PARERR;
           break;
   }
      return res;
  }

  DRESULT disk_read (BYTE drv,BYTE *buff,DWORD sector,BYTE count)
  {
   uint32_t result;

      if (drv || !count){  return RES_PARERR;}
   result = FSMC_NAND_ReadSmallPage(buff, sector, count);                                               
      if(result & NAND_READY){  return RES_OK; }
      else { return RES_ERROR;  }
  }

  #if _READONLY == 0
  DRESULT disk_write (BYTE drv,const BYTE *buff,DWORD sector,BYTE count)
  {
   uint32_t result;
   uint32_t BackupBlockAddr;
   uint32_t WriteBlockAddr;
   uint16_t IndexTmp = 0;
   uint16_t OffsetPage;
  
   /* NAND memory write page at block address*/
   WriteBlockAddr = (sector/NAND_BLOCK_SIZE);
   /* NAND memory backup block address*/
   BackupBlockAddr = (WriteBlockAddr + (NAND_MAX_ZONE/2)*NAND_ZONE_SIZE);
   OffsetPage = sector%NAND_BLOCK_SIZE;
  
      if (drv || !count){  return RES_PARERR;}
   
   /* Erase the NAND backup Block */
      result = FSMC_NAND_EraseBlock(BackupBlockAddr*NAND_BLOCK_SIZE);
  
      /* Backup the NAND Write Block to High zone*/
  
   for (IndexTmp = 0; IndexTmp < NAND_BLOCK_SIZE; IndexTmp++ )
   {
    FSMC_NAND_MoveSmallPage (WriteBlockAddr*NAND_BLOCK_SIZE+IndexTmp,BackupBlockAddr*NAND_BLOCK_SIZE+IndexTmp);
   }
  
   /* Erase the NAND Write Block */
   result = FSMC_NAND_EraseBlock(WriteBlockAddr*NAND_BLOCK_SIZE);
  
      /*return write the block  with modify*/
   for (IndexTmp = 0; IndexTmp < NAND_BLOCK_SIZE; IndexTmp++ )
   {
    if((IndexTmp>=OffsetPage)&&(IndexTmp < (OffsetPage+count)))
    {
     FSMC_NAND_WriteSmallPage((uint8_t *)buff, WriteBlockAddr*NAND_BLOCK_SIZE+IndexTmp, 1);
     buff = (uint8_t *)buff + NAND_PAGE_SIZE;
       }
    else
    {
          FSMC_NAND_MoveSmallPage (BackupBlockAddr*NAND_BLOCK_SIZE+IndexTmp,WriteBlockAddr*NAND_BLOCK_SIZE+IndexTmp);
       }
   }   
   
      if(result == NAND_READY){   return RES_OK;}
      else {   return RES_ERROR;}
  }
  #endif /* _READONLY */

  //NANDFLASH HY27UF081G2A-TPCB
  #define NAND_HY_MakerID     0xAD
  #define NAND_HY_DeviceID    0xF1
  
  /* Configure the NAND FLASH */
  void NAND_Configuration(void)
  {
   NAND_IDTypeDef NAND_ID;
   
   /* Enable the FSMC Clock */
   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
   
      /* FSMC Initialization */
   FSMC_NAND_Init();
  
   /* NAND read ID command */
   FSMC_NAND_ReadID(&NAND_ID);
    
   /* Verify the NAND ID */
   if((NAND_ID.Maker_ID == NAND_ST_MakerID) && (NAND_ID.Device_ID == NAND_ST_DeviceID))
   {
          printf("ST NANDFLASH");
   }
      else
      if((NAND_ID.Maker_ID == NAND_HY_MakerID) && (NAND_ID.Device_ID == NAND_HY_DeviceID))
   {
          printf("HY27UF081G2A-TPCB");
   }
   printf(" ID = 0x%x%x%x%x \n\r",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
  }

  void test_fatfs(void)
  {
      FATFS fs;
   FIL fl;
   FATFS *pfs;
   DWORD clust;
   unsigned int r,w,i;
   FRESULT  res;
   
  // NF_CHKDSK(0,1024);
   display_page(0,0);
   
  // for mount 
   res=f_mount(0,&fs);
   printf("f_mount=%x \n\r",res);
   
  // for format
   //res=f_mkfs(0,1,2048);  //MUST Format for New NANDFLASH !!!
   //printf("f_mkfs=%x \n\r",res);
  
  // for
   pfs=&fs;
   res = f_getfree("/", &clust, &pfs);
   printf("f_getfree=%x \n\r",res);
   printf("\n\r%lu MB total drive space."
       "\n\r%lu MB available.\n\r",
     (DWORD)(pfs->max_clust - 2) * pfs->csize /2/1024,
     clust * pfs->csize /2/1024);
   
  // for read
      res=f_open(&fl,"/test2.dat",FA_OPEN_EXISTING | FA_READ);
      printf("f_open=%x \n\r",res);
   for(i=0;i<2;i++)
   {
    for(r = 0; r < NAND_PAGE_SIZE; r++)
    {
     RxBuffer[r]= 0xff;
    }
    
    res=f_read(&fl,RxBuffer,NAND_PAGE_SIZE,&r);
    printf("f_read=%x \n\r",res);
    if(res || r == 0)break;
    for(r = 0; r < NAND_PAGE_SIZE; r++)
       {
           printf("D[%08x]=%02x ",(i*NAND_PAGE_SIZE+r),RxBuffer[r]);
           if((r%8)==7)
           {printf("\n\r");}
       }
      
   }
   f_close(&fl);
  // for write
   res=f_open(&fl,"/test2.dat",FA_CREATE_ALWAYS | FA_WRITE);
   printf("f_open=%x \n\r",res);
   for(i=0;i<2;i++)
   {
    for(w = 0; w < NAND_PAGE_SIZE; w++)
    {
     TxBuffer[w]=((w<<0)&0xff);
    }
          res=f_write(&fl,TxBuffer,NAND_PAGE_SIZE,&w);
          printf("f_write=%x \n\r",res);
    if(res || w<NAND_PAGE_SIZE)break;
    
   }
   f_close(&fl);
   
  // for umount
   f_mount(0,NULL);
  }

  /* Includes ------------------------------------------------------------------*/
  #include "fsmc_nand.h"
  #include "stm32f10x_conf.h"
  
  /** @addtogroup StdPeriph_Examples
    * @{
    */
  
  /** @addtogroup FSMC_NAND
    * @{
    */
  
  /* Private typedef -----------------------------------------------------------*/
  /* Private define ------------------------------------------------------------*/
  
  #define FSMC_Bank_NAND     FSMC_Bank2_NAND
  #define Bank_NAND_ADDR     Bank2_NAND_ADDR
  #define Bank2_NAND_ADDR    ((uint32_t)0x70000000)
  
  /* Private macro -------------------------------------------------------------*/
  /* Private variables ---------------------------------------------------------*/
  /* Private function prototypes -----------------------------------------------*/
  /* Private functions ---------------------------------------------------------*/
  
  /**
    * @brief  Configures the FSMC and GPIOs to interface with the NAND memory.
    *   This function must be called before any write/read operation
    *   on the NAND.
    * @param  None
    * @retval : None
    */
  void FSMC_NAND_Init(void)
  {
    GPIO_InitTypeDef GPIO_InitStructure;
    FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
    FSMC_NAND_PCCARDTimingInitTypeDef  p;
   
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
                           RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
   
  /*-- GPIO Configuration ------------------------------------------------------*/
  /* CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
    GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 | 
                                   GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
                                   GPIO_Pin_7;                                 
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
  
    GPIO_Init(GPIOD, &GPIO_InitStructure);
  
  /* D4->D7 NAND pin configuration  */ 
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
  
    GPIO_Init(GPIOE, &GPIO_InitStructure);
  
  
  /* NWAIT NAND pin configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;          
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
  
    GPIO_Init(GPIOD, &GPIO_InitStructure);
  
  /* INT2 NAND pin configuration */ 
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;          
    GPIO_Init(GPIOG, &GPIO_InitStructure);
  
    /*-- FSMC Configuration ------------------------------------------------------*/
    p.FSMC_SetupTime = 0x1;
    p.FSMC_WaitSetupTime = 0x3;
    p.FSMC_HoldSetupTime = 0x2;
    p.FSMC_HiZSetupTime = 0x1;
  
    FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
    FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
    FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
    FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
    FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
    FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
    FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
    FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
    FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
  
    FSMC_NANDInit(&FSMC_NANDInitStructure);
  
    /* FSMC NAND Bank Cmd Test */
    FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
  }
   
  /**
    * @brief  Reads NAND memory's ID.
    * @param  NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
    *                  the Manufacturer and Device ID. 
    * @retval : None
    */
  void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
  {
    uint32_t data = 0;
  
    /* Send Command to the command area */  
    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA)  = NAND_CMD_READID;
    /* Send Address to the address area */
    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = NAND_CMD_IDADDR;
  
     /* Sequence to read ID from NAND flash */ 
     data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
  
     NAND_ID->Maker_ID   = DATA_1st_CYCLE (data);
     NAND_ID->Device_ID  = DATA_2nd_CYCLE (data);
     NAND_ID->Third_ID   = DATA_3rd_CYCLE (data);
     NAND_ID->Fourth_ID  = DATA_4th_CYCLE (data); 
  }
  /**
    * @brief  This routine is for move one 2048 Bytes Page size to an other 2048 Bytes Page.
    *         the copy-back program is permitted just between odd address pages or even address pages.
    * @param  SourcePageAddress: Source page address
    * @param  TargetPageAddress: Target page address
    * @retval : New status of the NAND operation. This parameter can be:
    *              - NAND_TIMEOUT_ERROR: when the previous operation generate
    *                a Timeout error
    *              - NAND_READY: when memory is ready for the next operation
    *                And the new status of the increment address operation. It can be:
    *              - NAND_VALID_ADDRESS: When the new address is valid address
    *              - NAND_INVALID_ADDRESS: When the new address is invalid address 
    */
  uint32_t FSMC_NAND_MoveSmallPage(uint32_t SourcePageAddress, uint32_t TargetPageAddress)
  {
    uint32_t status = NAND_READY ;
    uint32_t data = 0xff;
  
      /* Page write command and address */
      *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_MOVE0;
  
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(SourcePageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(SourcePageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(SourcePageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(SourcePageAddress);
  
      *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_MOVE1;
  
      while( GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0 );
  
       *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_MOVE2;
  
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(TargetPageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(TargetPageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(TargetPageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(TargetPageAddress);
  
      *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_MOVE3;
  
      while( GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0 );  
  
      /* Check status for successful operation */
      status = FSMC_NAND_GetStatus();
     
   data = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
   if(!(data&0x1)) status = NAND_READY;
     
   return (status);
  }
  /**
    * @brief  This routine is for writing one or several 2048 Bytes Page size.
    * @param  pBuffer: pointer on the Buffer containing data to be written
    * @param  PageAddress: First page address
    * @param  NumPageToWrite: Number of page to write 
    * @retval : New status of the NAND operation. This parameter can be:
    *              - NAND_TIMEOUT_ERROR: when the previous operation generate
    *                a Timeout error
    *              - NAND_READY: when memory is ready for the next operation
    *                And the new status of the increment address operation. It can be:
    *              - NAND_VALID_ADDRESS: When the new address is valid address
    *              - NAND_INVALID_ADDRESS: When the new address is invalid address 
    */
  
  uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, uint32_t PageAddress, uint32_t NumPageToWrite)
  {
    uint32_t index = 0x00, numpagewritten = 0x00,addressstatus = NAND_VALID_ADDRESS;
    uint32_t status = NAND_READY, size = 0x00;
    uint32_t data = 0xff;
  
    while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
    {
      /* Page write command and address */
      *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
  
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(PageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(PageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(PageAddress); 
      *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(PageAddress);
     
      /* Calculate the size */
      size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
  
      /* Write data */
      for(; index < size; index++)
      {
        *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
      }
     
      *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE1;
  
      while( GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0 );
     
      /* Check status for successful operation */
      status = FSMC_NAND_GetStatus();
     
   data = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
   if(!(data&0x1)) status = NAND_READY;
     
      if(status == NAND_READY)
      {
        numpagewritten++; NumPageToWrite--;
  
        /* Calculate Next small page Address */
        if(PageAddress++ > (NAND_MAX_ZONE*NAND_ZONE_SIZE*NAND_BLOCK_SIZE))
        { addressstatus = NAND_INVALID_ADDRESS;} 
      }   
    }
   
    return (status | addressstatus);
  }
   
  /**
    * @brief  This routine is for sequential read from one or several
    *         2048 Bytes Page size. 
    * @param  pBuffer: pointer on the Buffer to fill
    * @param  PageAddress: First page address
    * @param  NumPageToRead: Number of page to read 
    * @retval : New status of the NAND operation. This parameter can be:
    *              - NAND_TIMEOUT_ERROR: when the previous operation generate
    *                a Timeout error
    *              - NAND_READY: when memory is ready for the next operation
    *                And the new status of the increment address operation. It can be:
    *              - NAND_VALID_ADDRESS: When the new address is valid address
    *              - NAND_INVALID_ADDRESS: When the new address is invalid address
    */
   
   
  uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pBuffer, uint32_t PageAddress, uint32_t NumPageToRead)
  {
    uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
    uint32_t status = NAND_READY, size = 0x00;
  
   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ1;
     
   while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
     {   
       /* Page Read command and page address */
    
    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(PageAddress);
       *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(PageAddress);
       *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(PageAddress);
       *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(PageAddress);
         
       *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_READ2;
  
       while( GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0 );
      
       /* Calculate the size */
       size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
      
       /* Get Data into Buffer */   
       for(; index < size; index++)
       {
         pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
       }
   
       numpageread++; NumPageToRead--;
  
       /* Calculate page address */              
    if(PageAddress++ > (NAND_MAX_ZONE*NAND_ZONE_SIZE*NAND_BLOCK_SIZE))
    { addressstatus = NAND_INVALID_ADDRESS;}
   }
  
     status = FSMC_NAND_GetStatus();
   
     return (status | addressstatus);
  }
   
  /**
    * @brief  This routine erase complete block from NAND FLASH
    * @param  PageAddress: Any address into block to be erased
    * @retval :New status of the NAND operation. This parameter can be:
    *              - NAND_TIMEOUT_ERROR: when the previous operation generate
    *                a Timeout error
    *              - NAND_READY: when memory is ready for the next operation
    */
   
  uint32_t FSMC_NAND_EraseBlock(uint32_t PageAddress)
  {
   uint32_t data = 0xff, status = NAND_ERROR;
   
    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
  
    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(PageAddress);
    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_4th_CYCLE(PageAddress);
    
    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
  
    while( GPIO_ReadInputDataBit(GPIOG, GPIO_Pin_6) == 0 );
  
    /* Read status operation ------------------------------------ */ 
    FSMC_NAND_GetStatus();
  
    data = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
   
    if(!(data&0x1)) status = NAND_READY;
     
    return (status);
  }
  
  /**
    * @brief  This routine reset the NAND FLASH
    * @param  None
    * @retval :NAND_READY
    */
  
  uint32_t FSMC_NAND_Reset(void)
  {
    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
  
    return (NAND_READY);
  }
  
  /**
    * @brief  Get the NAND operation status
    * @param  None
    * @retval :New status of the NAND operation. This parameter can be:
    *              - NAND_TIMEOUT_ERROR: when the previous operation generate
    *                a Timeout error
    *              - NAND_READY: when memory is ready for the next operation   
    */
   
   
  uint32_t FSMC_NAND_GetStatus(void)
  {
    uint32_t timeout = 0x1000000, status = NAND_READY;
  
    status = FSMC_NAND_ReadStatus();
  
    /* Wait for a NAND operation to complete or a TIMEOUT to occur */
    while ((status != NAND_READY) &&( timeout != 0x00))
    {
       status = FSMC_NAND_ReadStatus();
       timeout --;     
    }
  
    if(timeout == 0x00)
    {         
      status =  NAND_TIMEOUT_ERROR;     
    }
  
    /* Return the operation status */
    return (status);     
  }
   
  /**
    * @brief  Reads the NAND memory status using the Read status command
    * @param  None
    * @retval :The status of the NAND memory. This parameter can be:
    *              - NAND_BUSY: when memory is busy
    *              - NAND_READY: when memory is ready for the next operation   
    *              - NAND_ERROR: when the previous operation gererates error    
    */
   
  uint32_t FSMC_NAND_ReadStatus(void)
  {
    uint32_t data = 0x00, status = NAND_BUSY;
  
    /* Read status operation ------------------------------------ */
    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
    data = *(__IO uint8_t *)(Bank_NAND_ADDR);
  
    if((data & NAND_ERROR) == NAND_ERROR)
    {
      status = NAND_ERROR;
    }
    else if((data & NAND_READY) == NAND_READY)
    {
      status = NAND_READY;
    }
    else
    {
      status = NAND_BUSY;
    }
   
    return (status);
  }

  /* Define to prevent recursive inclusion -------------------------------------*/
  #ifndef __FSMC_NAND_H
  #define __FSMC_NAND_H
  
  /* Includes ------------------------------------------------------------------*/
  #include "stm32f10x.h"
  
  /* Exported types ------------------------------------------------------------*/
  typedef struct
  {
    uint8_t Maker_ID;
    uint8_t Device_ID;
    uint8_t Third_ID;
    uint8_t Fourth_ID;
  }NAND_IDTypeDef;
  
  typedef struct
  {
    uint16_t Zone;
    uint16_t Block;
    uint16_t Page;
  } NAND_ADDRESS;
  
  /* Exported constants --------------------------------------------------------*/
  /* NAND Area definition  for STM3210E-EVAL Board RevD */
  #define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE high */
  #define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
  #define DATA_AREA                  ((uint32_t)0x00000000)
  
  /* FSMC NAND memory command */
  #define NAND_CMD_READ1             ((uint8_t)0x00)
  #define NAND_CMD_READ2            ((uint8_t)0x30)
  
  #define NAND_CMD_WRITE0            ((uint8_t)0x80)
  #define NAND_CMD_WRITE1            ((uint8_t)0x10)
  
  #define NAND_CMD_MOVE0             ((uint8_t)0x00)
  #define NAND_CMD_MOVE1             ((uint8_t)0x35)
  #define NAND_CMD_MOVE2             ((uint8_t)0x85)
  #define NAND_CMD_MOVE3             ((uint8_t)0x10)
   
  #define NAND_CMD_ERASE0            ((uint8_t)0x60)
  #define NAND_CMD_ERASE1            ((uint8_t)0xD0) 
  
  #define NAND_CMD_READID            ((uint8_t)0x90)
  #define NAND_CMD_IDADDR            ((uint8_t)0x00)
   
  #define NAND_CMD_STATUS            ((uint8_t)0x70)
  #define NAND_CMD_RESET             ((uint8_t)0xFF)
  
  /* NAND memory status */
  #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
  #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
  #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
  #define NAND_BUSY                  ((uint32_t)0x00000000)
  #define NAND_ERROR                 ((uint32_t)0x00000001)
  #define NAND_READY                 ((uint32_t)0x00000040)
  
  /* FSMC NAND memory parameters */
  //#define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
  //#define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
  //#define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
  //#define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
  //#define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
  
  /* FSMC NAND memory HY27UF081G2A-TPCB parameters */
  #define NAND_PAGE_SIZE             ((uint16_t)0x0800) /* 2048 bytes per page w/o Spare Area */
  #define NAND_BLOCK_SIZE            ((uint16_t)0x0040) /* 64x2048 bytes pages per block */
  #define NAND_ZONE_SIZE             ((uint16_t)0x0200) /* 512 Block per zone */
  #define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0040) /* last 64 bytes as spare area */
  #define NAND_MAX_ZONE              ((uint16_t)0x0002) /* 2 zones of 1024 block */
  
  /* FSMC NAND memory data computation */
  #define DATA_1st_CYCLE(DATA)       (uint8_t)((DATA)& 0xFF)               /* 1st data cycle */
  #define DATA_2nd_CYCLE(DATA)       (uint8_t)(((DATA)& 0xFF00) >> 8)      /* 2nd data cycle */
  #define DATA_3rd_CYCLE(DATA)       (uint8_t)(((DATA)& 0xFF0000) >> 16)   /* 3rd data cycle */
  #define DATA_4th_CYCLE(DATA)       (uint8_t)(((DATA)& 0xFF000000) >> 24) /* 4th data cycle */
  
  /* FSMC NAND memory HY27UF081G2A-TPCB address computation */
  #define ADDR_1st_CYCLE(PADDR)       (uint8_t)(0x0)          /* 1st addressing cycle */
  #define ADDR_2nd_CYCLE(PADDR)       (uint8_t)(0x0)     /* 2nd addressing cycle */
  #define ADDR_3rd_CYCLE(PADDR)       (uint8_t)(PADDR & 0xFF)      /* 3rd addressing cycle */
  #define ADDR_4th_CYCLE(PADDR)       (uint8_t)((PADDR>>8) & 0xFF) /* 4th addressing cycle */
  
  /* Exported macro ------------------------------------------------------------*/
  /* Exported functions ------------------------------------------------------- */
  void FSMC_NAND_Init(void);
  void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID);
  uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, uint32_t Address, uint32_t NumPageToWrite);
  uint32_t FSMC_NAND_ReadSmallPage (uint8_t *pBuffer, uint32_t Address, uint32_t NumPageToRead);
  uint32_t FSMC_NAND_MoveSmallPage (uint32_t SourcePageAddress, uint32_t TargetPageAddress);
  //uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
  //uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
  uint32_t FSMC_NAND_EraseBlock(uint32_t Address);
  uint32_t FSMC_NAND_Reset(void);
  uint32_t FSMC_NAND_GetStatus(void);
  uint32_t FSMC_NAND_ReadStatus(void);
  //uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address);
  
  #endif /* __FSMC_NAND_H */

 #include <stdio.h>
 #include <stdint.h>
 #include <Nuvoton\iomini51.h>
 
 int main(void)
 {
     uint32_t i=0;
    
     /* Output a message on Hyperterminal using printf function */
  printf("\n\r\n\r");
  printf("*** 9G-MINI51 V1.00 Build by yuanxihua@21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
  printf("*** 9G-MINI51 V1.00 Rebooting ...\n\r\n\r");
 
     GPIO_P0_PMD = 0X5555;
     GPIO_P1_PMD = 0X5555;
     GPIO_P2_PMD = 0X5555;
     GPIO_P3_PMD = 0X5555;
     GPIO_P4_PMD = 0X5555;
     GPIO_P5_PMD = 0X5555;
 
     while(1)
     {
         for(uint32_t j = 0; j <800000; j++);
         GPIO_P0_DOUT = 0x5E; /* switch on LEDs                    */
   GPIO_P1_DOUT = 0xCA;
   GPIO_P2_DOUT = 0xAB;
   GPIO_P3_DOUT = 0x9A;
   GPIO_P4_DOUT = 0x55;//NO USE
         GPIO_P5_DOUT = 0XE2;
         for(uint32_t j = 0; j <800000; j++);
         GPIO_P0_DOUT = 0xAD; /* switch off LEDs                    */
   GPIO_P1_DOUT = 0xF7;
   GPIO_P2_DOUT = 0xD7;
   GPIO_P3_DOUT = 0xED;
   GPIO_P4_DOUT = 0xAA;//NO USE
         GPIO_P5_DOUT = 0XDD;
        
         printf("*** 9G-MINI51 V1.00 Running %d Times...\n\r",i++);
     }
 }

“sim900a.c ”文件源码如下：

#include <stdio.h>
#include <M051Series.h>

#include "Driver\DrvUART.h"
#include "Driver\DrvGPIO.h"
#include "Driver\DrvSYS.h"

#define PWRKEY   E_PORT2, E_PIN1
#define NRESET  E_PORT4, E_PIN3
#define STATUS   E_PORT2, E_PIN3
#define RI   E_PORT3, E_PIN2
#define CTS   E_PORT0, E_PIN0
/*
_________________________________________________
| M0516LAN      SIM900A  |
|            |
| P21  PWRKEY  ---->  PWRKEY  |
| P43  NRESET  ---->  NRESET  |
| P23  STATUS  <----  STATUS  |
| P32  RI   <----  RI   |
| P00  CTS1  <----  CTS   |
| P13  TXD1  ---->  RXD   |
| P12  RXD1  <----  TXD   |
|_______________________________________________|
*/
int UART1_init(void)
{
 STR_UART_T sParam;

 /* Set UART1 Pin */
 DrvGPIO_InitFunction(E_FUNC_UART1);
// outpw(&SYS->P1_MFP, (inpw(&SYS->P1_MFP) | (0x3<<10)) & ~(0x3<<2));
// outpw(&SYS->P0_MFP, (inpw(&SYS->P0_MFP) | (0x3<<8)) & ~(0x3<<0));

 /* Select UART1 Clock Source From 12Mhz*/
 DrvSYS_SelectIPClockSource(E_SYS_UART_CLKSRC,0);

 /* UART1 Setting */
    sParam.u32BaudRate   = 9600;
    sParam.u8cDataBits   = DRVUART_DATABITS_8;
    sParam.u8cStopBits   = DRVUART_STOPBITS_1;
    sParam.u8cParity   = DRVUART_PARITY_NONE;
    sParam.u8cRxTriggerLevel= DRVUART_FIFO_1BYTES;

 if(DrvUART_Open(UART_PORT1,&sParam) != E_SUCCESS)
 {
  printf("UART1 open failed\n");
  return FALSE;
 }
 /* Enable Interrupt and install the call back function */
// DrvUART_EnableInt(UART_PORT1, (DRVUART_RLSINT | DRVUART_RDAINT),UART1_INT_HANDLE);
  
 /* Disable Interrupt */
// DrvUART_DisableInt(UART_PORT1,DRVUART_RLSINT | DRVUART_THREINT | DRVUART_RDAINT);

 return TRUE;
}

int SIM900A_Open(void)
{
 int dly;

 DrvGPIO_ClrBit(PWRKEY);
 for(dly=0;dly<2000;dly++) DrvSYS_Delay(1000); //delay 1S
 DrvGPIO_SetBit(PWRKEY);

 for(dly=0;dly<3000;dly++) DrvSYS_Delay(1000); //delay 3S
 if(DrvGPIO_GetBit(STATUS))
 {
  printf("SIM900A Open Success!!!\n\r");
  return 1;
 }
 else
 { 
  printf("SIM900A Open Failure!!!\n\r");
  return 0;
 }
}

int SIM900A_Close(void)
{
 int dly;

 DrvGPIO_ClrBit(PWRKEY);
 for(dly=0;dly<6000;dly++) DrvSYS_Delay(1000); //delay 1S-5S
 DrvGPIO_SetBit(PWRKEY);

 for(dly=0;dly<4000;dly++) DrvSYS_Delay(1000); //delay 2S

 if(DrvGPIO_GetBit(STATUS))
 { 
  printf("SIM900A Close Failure!!!\n\r");
  return 1;
 }
 else
 { 
  printf("SIM900A Close Success!!!\n\r"); 
  return 0;
 }
}

int SIM900A_Reset(void)
{
 int dly;

 DrvGPIO_ClrBit(NRESET);
 DrvSYS_Delay(100);       //delay 20uS-50uS
 DrvGPIO_SetBit(NRESET);

 for(dly=0;dly<2000;dly++) DrvSYS_Delay(1000); //delay 2S
 if(DrvGPIO_GetBit(STATUS)==1)
  return 1;
 else
  return 0;
}
int SIM900A_init(void)
{
    int  ret =0;

 DrvGPIO_Open(STATUS,  E_IO_INPUT);
 DrvGPIO_Open(RI,   E_IO_INPUT);
 DrvGPIO_Open(CTS,   E_IO_INPUT);
 DrvGPIO_Open(PWRKEY,  E_IO_OUTPUT);
 DrvGPIO_Open(NRESET,  E_IO_OUTPUT);

 DrvGPIO_SetBit(PWRKEY);
 DrvGPIO_SetBit(NRESET);

 ret = SIM900A_Open();
 UART1_init();

 return ret;
}

int SIM900A_gets(char *buf)
{
 int ret=0;
 int dly=3000000;   // delay 3S

 while(dly-->1) 
 {
  if(UART1->FSR.RX_EMPTY == 0 )
  {
   *buf++ =UART1->DATA;//printf("%c",*(buf-1));
   ret++;dly=10000; //delay  10ms
  }
  DrvSYS_Delay(1);   //delay 1us
 }
 return ret;
}

void SIM900A_puts(const char *buf)
{
 while(*buf)
 {
  while(UART1->FSR.TX_FULL == 1); 
  UART1->DATA =(*buf++)&0xff;//printf("%c",*(buf-1));
 }
}

// AT+CPOWD=1   //Power down
// AT+CFUN=x    //Power Saving
// AT+CBC  //monitor the supply voltage
// AT+IPR=x  //fixed baud rate ,“RDY” is received
// AT+CSCLK=1 //enable the SLEEP mode
// AT+CMIC  //adjust the input gain level of microphone
// AT+SIDET  //set the side-tone level
// AT+CLVL  //adjust the output gain level
// AT+CADC  //read the voltage value on ADC 

void SIM900A_test(void)
{
 char buffer[128];

 printf("\n\r\n\r");
 printf("*** 9G-M0516 V1.00 Build by yuanxihua@21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
 printf("*** 9G-M0516 V1.00 Rebooting ...\n\r\n\r");

 SIM900A_init();
 
 printf("SIM900A_test Send AT COMMAND @ 9600 bps !!!\n\r");

// SIM900A_puts("ATI\r");
 SIM900A_puts("AT+GMM\r");
 if(SIM900A_gets(buffer)>0)
 {printf("\n\r%s\n\r",buffer);}
}

//源码完毕。－－缥缈九哥调试通过。

半主机的调试信息如下：

*** 9G-M0516 V1.00 Build by yuanxihua@21cn.com on (Jan  3 2012 - 13:16:32)
*** 9G-M0516 V1.00 Rebooting ...

SIM900A Open Success!!!
SIM900A_test Send AT COMMAND @ 9600 bps !!!

AT+GMM
SIMCOM_SIM900A

OK

－－缥缈九哥验证


读SIM卡电话本。
 
SIM900A_puts("AT+CPBS=\"SM\"\r");
读第一条电话本记录
  
//get SIM no.1 phoneid
SIM900A_puts("AT+CPBR=1,1\r");
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
for(i=0;i<11;i++)
{
//AT+CPBR=1,1
//+CPBR: 1,"13925101136",129,"yuanxihua"
// printf("\n\r%c",buffer[24+i]);
callphoneid[i]= buffer[24+i];
}
//
 
 
发中文短信。
SIM900A_puts("AT+CMGF=1\r"); //TEXT Mode
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
SIM900A_puts("AT+CSCS=\"UCS2\"\r"); //for CHINESE
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0)
{printf("\n\r%s\n\r",buffer);}
//不用配置短信服务中心号码
/*
SIM900A_puts("AT+CSCA=\"002B0038003600310033003800300030003200300030003500300030\",145\r"); //+8613800200500 短信中心号码
memset(buffer,'\0',sizeof(buffer));
if(SIM900A_gets(buffer)>0)
{printf("\n\r%s\n\r",buffer);}
*/
SIM900A_puts("AT+CSMP=17,167,0,25\r");
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0)
{printf("\n\r%s\n\r",buffer);}
// SIM900A_puts("AT+CMGS=\"00310033003900320035003100300031003100330036\"\r"); //13925101136 被叫号码，不固定，从SIM卡读。
SIM900A_puts("AT+CMGS=\"");
for(i=0;i<11;i++)
{
SIM900A_puts("003");
SIM900A_putchar(callphoneid[i]);
}
SIM900A_puts("\"\r");
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
SIM900A_puts("4F60597D ");
//你好   短信内容，UNICODE格式；
SIM900A_putchar(26); //<Ctrl+Z>
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0);
{printf("\n\r%s\n\r",buffer);}
打电话 
 
printf("SIM900A Phone a call  by AT-commond @ 9600 bps !!!\n\r");
// Call a phone
SIM900A_puts("ATD");
for(i=0;i<11;i++)
{
SIM900A_putchar(callphoneid[i]);
}
SIM900A_puts(";\r");
memset(buffer,'\0',sizeof(buffer)); 
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
发英文短信 
 
printf("SIM900A Send a English SMS  by AT-commond @ 9600 bps !!!\n\r");
//init SIM900A for SMS
SIM900A_puts("AT+CMGF=1\r"); //TEXT Mode
memset(buffer,'\0',sizeof(buffer));
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
SIM900A_puts("AT+CSCS=\"GSM\"\r");
memset(buffer,'\0',sizeof(buffer));
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
//prepore config SIM900A for sendding a SMS
SIM900A_puts("AT+CMGS=\"+86");
for(i=0;i<11;i++)
{
SIM900A_putchar(callphoneid[i]);
}
SIM900A_puts("\"\r");
memset(buffer,'\0',sizeof(buffer));
if(SIM900A_gets(buffer)>0) 
{printf("\n\r%s\n\r",buffer);}
//send a SMS to SIM900A
SIM900A_puts("This a report from yuanxihua@21cn.com!!!\x1a");// \x1a = <Ctrl+Z>
memset(buffer,'\0',sizeof(buffer));
if(SIM900A_gets(buffer)>0)
{printf("\n\r%s\n\r",buffer);}

#include "SH88F516.h"
#include <stdio.h>                /* prototype declarations for I/O functions */

#define  U2DIN    P1_5
#define  U2SCLK    P1_6
#define  U1DIN    P3_7
#define  U1SCLK    P3_6
#define  TM1640_DELAY  1

//0 1 2 3 4 5 6 7 8 9 A B C D E F
const unsigned char code TM1640_CODE[16]={0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x07, 0x7F, 0x6F, 0x77, 0X7F, 0x39, 0x3F, 0x79, 0x71};

const unsigned char code TM1640_CODEA[16] _at_ 0xe000;

void tm1640_display(unsigned char *led_data);

void tm1640_delay(unsigned int delay)
{
 unsigned int i;
 for(i=0;i<delay;i++);
}
void tm1640_start(void)
{
 U1DIN  = U2DIN  = 1;
 U1SCLK = U2SCLK = 1; tm1640_delay(TM1640_DELAY);
 U1DIN  = U2DIN  = 0; tm1640_delay(TM1640_DELAY);
 U1SCLK = U2SCLK = 0; tm1640_delay(TM1640_DELAY);
}

void tm1640_end(void)
{
 U1SCLK = U2SCLK = 0;
 U1DIN  = U2DIN  = 0; tm1640_delay(TM1640_DELAY);
 U1SCLK = U2SCLK = 1; tm1640_delay(TM1640_DELAY);
 U1DIN  = U2DIN  = 1;   tm1640_delay(TM1640_DELAY);
}

void tm1640_byte(unsigned char data1,unsigned char data2)
{
 unsigned int i;

 for(i=0;i<8;i++)
 {
  data1 = data1 >>1;   U1DIN =CY;
  data2 = data2 >>1;
  U2DIN =CY;    tm1640_delay(TM1640_DELAY);
  U1SCLK = U2SCLK = 1; tm1640_delay(TM1640_DELAY);
  U1SCLK = U2SCLK = 0; tm1640_delay(TM1640_DELAY);
 }
}

void tm1640_display(unsigned char *led_data)
{
 unsigned int i;

 P1M0 &= ~(1<<6 ); P1M1 |= 1<<6; //
 P1M0 &= ~(1<<5 ); P1M1 |= 1<<5; //
 P3M0 &= ~(1<<6 ); P3M1 |= 1<<6; //
 P3M0 &= ~(1<<7 ); P3M1 |= 1<<7; //


 tm1640_end();
 tm1640_start();
 tm1640_byte(0x40,0x40); // command1
 tm1640_end();

 tm1640_start();
 tm1640_byte(0xc0,0xc0); // command2
 for(i=0;i<16;i++)
 {
  tm1640_byte(TM1640_CODE[led_data[i]],TM1640_CODE[led_data[16+i]]);
 }
 tm1640_end();

 tm1640_start();
 tm1640_byte(0x8b,0x8b); // command3
 tm1640_end();
}

/**************************************************************************//**
* @file fm25640c.c
* @version V1.00
* $author: yuanxihua@21cn.com
* $Date:  2013/01/03 11:33a $
* @brief  NUC123 Series FM25640C Driver Sample Code
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include "NUC123Series.h"
/*
_________________________________________________
| NUC123SD4AN0     FM25640C |
|            |
| PC8  SS10  ---->  CS   |
| PC9  SPICLK1  ---->  SCK   |
| PC10 MISO10  <----  SO   |
| PC11 MOSI10  ---->  SI   |
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
//#define  FM25640C_CS   PC8
#define  FM25640C_SIZE  8*1024
//FM25640C命令
#define   FM25640C_WREN  0x06
#define   FM25640C_WRDI  0x04
#define   FM25640C_RDSR  0x05ff
#define   FM25640C_WRSR  0x0100
#define   FM25640C_READ  0x030000FF
#define   FM25640C_WRITE  0x02000000
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
void FM25640C_Init(void);
void FM25640C_Write_Byte(uint32_t addr,uint8_t wrdata);
void FM25640C_Write_Status_Register(uint8_t wrdata);
uint8_t FM25640C_Read_Byte(uint32_t addr);
uint8_t FM25640C_Read_Status_Register(void);
void SPI1_Send_Data(uint32_t wrdata,uint8_t bits);
/* Private functions ---------------------------------------------------------*/
/**
  * @brief  Main program.
  * @param  None
  * @retval None
  */
void FM25640C_Test(void)
{
uint32_t i;
/* Configure the FM25640C */
FM25640C_Init();
while(0)
{
//  SPI1_Send_Data(0x55, 8);
//  SPI_SET_SS0(SPI1); SPI1_Send_Data(0x55, 8);SPI_CLR_SS0(SPI1); //写0x55测试SPI接口
//  FM25640C_Write_Byte(0xCC, 0x55);
//  FM25640C_Read_Byte (0xCC);
//  FM25640C_Read_Status_Register();
}
FM25640C_Write_Status_Register(0x00);
printf("FM25640C_Read_Status_Register() = 0x%02x \n\r",FM25640C_Read_Status_Register());
FM25640C_Write_Byte(0xAA, 0x55);
FM25640C_Write_Byte(0x55, 0xAA);
printf("FM25640C_Read_Byte(0xAA) = 0x%02x \n\r",FM25640C_Read_Byte(0xAA));
printf("FM25640C_Read_Byte(0x55) = 0x%02x \n\r",FM25640C_Read_Byte(0x55));
while(1)
{
  for(i=0;i<FM25640C_SIZE;i++)
  {FM25640C_Write_Byte(i, i&0xff);}
  SYS_SysTickDelay(300000);
  for(i=0;i<FM25640C_SIZE;i++)
  {
   //for display
   if((i%16)== 0){printf("\n\r%08xh:",i);}
   printf(" %02x",FM25640C_Read_Byte(i));
   if((i%16)==15){printf(" ;");}
   //display  end
  }
  SYS_SysTickDelay(300000);
}
}
// SPI1_Send_Data(FM25640C_WREN,8);
// SPI1_Send_Data(FM25640C_WRDI,8);
uint8_t FM25640C_Read_Byte(uint32_t addr)
{
uint32_t rddata,tmpdata=FM25640C_READ;
tmpdata |= (addr << 8);  
SPI1_Send_Data(tmpdata,32);
rddata = SPI_GET_RX0_DATA(SPI1);
return (uint8_t)rddata;
}
void FM25640C_Write_Byte(uint32_t addr, uint8_t wrdata)
{
uint32_t tmpdata=FM25640C_WRITE;
SPI1_Send_Data(FM25640C_WREN,8);    //中:使能写操作//Write Enable
tmpdata |= (addr << 8) + wrdata;
SPI1_Send_Data(tmpdata,32);
}
uint8_t FM25640C_Read_Status_Register(void)
{
uint32_t rddata;
SPI1_Send_Data(FM25640C_RDSR,16);
rddata = SPI_GET_RX0_DATA(SPI1);
return (uint8_t)rddata;
}
void FM25640C_Write_Status_Register(uint8_t wrdata)
{
uint16_t dat=FM25640C_WRSR | wrdata;
SPI1_Send_Data(FM25640C_WREN,8);    //中:使能写操作//Write Enable
SPI1_Send_Data(dat,16);
}
void SPI1_Send_Data(uint32_t wrdata, uint8_t bits)
{
SPI1->CNTRL = (SPI1->CNTRL&0xFFFFFF07) | ((bits&0x1f) <<3);
SPI_WRITE_TX0(SPI1, wrdata);     //中:待发数据//en:data waiting for sending
SPI_SET_GO(SPI1);        //中:启动发送//en: Start Transfer
while(SPI_IS_BUSY(SPI1) !=0);     //中:等待发送结束//en:waiting for sending finished
}
void SPI1_Init(void)
{
/* Enable IP clock */         
    SET_SPI1_CLKSRC(CLK_SPI1_HCLK);        //En:Select SPI1 clock source
    GPIO_SPI1();                                //中:配置PC8~11为SPI功能//Set PC11~PC8 as SPI1 pin. PC8=SPISS10,PC9=SPICLK1,PC10=MISO10,PC11=MOSI10
DrvSPI_Init(SPI1, SPI_MASTER, SPI_TYPE0, 32);
  SPI_SET_DIVIDER(SPI1, 1);                       //中:设置SPI的分频值//en:Set divider of SPI_CLK  SPIclk = Pclk/((DIVIDER+1)*2)
    SPI_SET_MSB_FIRST(SPI1);        //En:MSB first
SPI_SET_SS(SPI1, SPI_SS_LOW_TRIGGER, SPI_AUTO_SS);//中:自动片选选择//en:Slave Select auto
SPI_SET_SS0(SPI1);        //中:置片选有效//En:active SS1
}
void FM25640C_Init(void)
{
SPI1_Init();
}

---------------------------------------------------------------------------------------------------------*/
#include <string.h>
#include <stdio.h>

#define MX (z>>5^y<<2) + (y>>3^z<<4)^(sum^y) + (k[p&3^e]^z)

//注意：delta的取值是随机的，但是为了避免不良的取值，采取的是
//黄金分割数（根号5－2）/2与2的32次方的乘积。为0x9e3779b9。  
//在解密中，sum＝delta×round，如：delta×32＝13C6EF3720
  
//v表示为运算的长整型数据的首地址
//k为长整型的密钥的首地址
//n表示以32bit为基本单位的要运算的组元个数，正表示加密，负表示解密

long xxtea(long* v, long n, long* k);

long xxtea(long* v, long n, long* k)
{
 unsigned long z=v[n-1], y=v[0], sum=0, e, DELTA=0x9e3779b9;
 long p, q;

 if(n > 1)
 {/* 加密过程 */
  q = 6 + 52/n;
  while(q-- > 0)
  {
   sum += DELTA; e = (sum >> 2) & 3;
   for (p=0; p<n-1; p++) y = v[p+1], z = v[p] += MX;
   y = v[0]; z = v[n-1] += MX;
  }
  return 0;
 }
 else
 if(n < -1)
 {/* 解密过程 */
  n = -n; q = 6 + 52/n; sum = q*DELTA;
  while(sum != 0)
  {
   e = (sum >> 2) & 3;
   for (p=n-1; p>0; p--) z = v[p-1], y = v[p] -= MX;
   z = v[n-1]; y = v[0] -= MX; sum -= DELTA;
  }
  return 0;
 } 
 return 1;
}

void  xxtea_test(void)
{
 unsigned long buff[4];
 unsigned long test[4]={0x11223344,0x55667788,0x99AABBCC,0xDDEEFF00};
 unsigned long keys[4]={0x12345678,0x9ABCDEF0,0x12345678,0x9ABCDEF0};
 
 while(1)
 {
  printf("\n\rxxtea test: \n\r");
  memcpy(buff,test,16); printf("0x%08x,0x%08x,0x%08x,0x%08x\n\r",buff[0],buff[1],buff[2],buff[3]);
  xxtea( buff, 4,keys); printf("0x%08x,0x%08x,0x%08x,0x%08x\n\r",buff[0],buff[1],buff[2],buff[3]);
  xxtea( buff,-4,keys); printf("0x%08x,0x%08x,0x%08x,0x%08x\n\r",buff[0],buff[1],buff[2],buff[3]);
  
  while(1);
 }
}

//SDRAM.ini
/******************************************************************************/
/* Dbg_RAM.ini: Initialization Script for Debugging in SDRAM                  */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools.                    */
/* Copyright (c) 2011 Keil Software. All rights reserved.                     */
/* This software may only be used under the terms of a valid, current,        */
/* end user licence from KEIL for a compatible version of KEIL software       */
/* development tools. Nothing else gives you the right to use this software.  */
/******************************************************************************/
DEFINE INT  Entry;
DEFINE LONG GCR_BA;
DEFINE LONG CLK_BA;
DEFINE LONG SDIC_BA;
DEFINE LONG GP_BA;
Entry  = 0x00008000;
GCR_BA  = 0xB0000000;
CLK_BA = 0xB0000200;
SDIC_BA = 0xB0003000;
GP_BA = 0xB8001000;
FUNC void Clock_Setup (void)
{
}
FUNC void SDRAM_Setup(void)
{
_WDWORD(0xb0003000, 0x00130456); // SDOPM Init DDR
_WDWORD(0xb0003030, 0x00001010); // DQSODS
_WDWORD(0xb0003010, 0x00000005); // SDSIZE0
_WDWORD(0xb0003004, 0x00000021); // SDCMD
_WDWORD(0xb0003004, 0x00000023); // SDCMD
_WDWORD(0xb0003004, 0x00000027); // SDCMD
_WDWORD(0xb000301C, 0x00001002); // SDEMR
_WDWORD(0xb0003018, 0x00000122); // SDMR
_WDWORD(0xb0003004, 0x00000027); // SDCMD
_WDWORD(0xb0003004, 0x0000002B); // SDCMD
_WDWORD(0xb0003004, 0x0000002B); // SDCMD
_WDWORD(0xb0003018, 0x00000022); // SDMR
_WDWORD(0xb0003004, 0x00000020); // SDCMD
_WDWORD(0xb0003034, 0x00AAAA00); // CKDQSDS
_WDWORD(0xb0003008, 0x0000805A); // SDREF
_WDWORD(0xb00000A0, 0x00000000); // MISCPCR
_WDWORD(0xb0000224, 0x0000447E); // UPLLCON PLL=192MHz
_WDWORD(0xb000020C, 0x00000018); // CLKDIV0 Divider
_WDWORD(0xb000021C, 0x00000000); // CLKDIV4
_WDWORD(0xb0003028, 0x094E7549); // SDTIME Sdram Timing
    _sleep_(10);
_WDWORD(0xb8001010, 0x00000008); // GPIOB_OMD  PB3=OUTPUT
_WDWORD(0xb8001018, 0x00000008); // GPIOB_DOUT PB3=HIGH
    _sleep_(10);
}
FUNC void Remap (void)
{
}
FUNC void Download (void)
{
    exec("load %L incremental");
}
FUNC void PC_Setup (void)
{
    PC = Entry;
}
FUNC void GoMain (void)
{
    exec("g,main");
}
//Clock_Setup();
SDRAM_Setup();
//Remap();
Download();
PC_Setup();
GoMain();
//main.c文件
#include <stdio.h>
#include "wblib.h"
#define DebugCom 0x100
void Delay(UINT32 k)
{
volatile int j=k*36000;
while(j--);
}
void InitDebugCom(void)
{
WB_UART_T *uart;
//Nornal Speed UART
outp32(REG_GPAFUN, inp32(REG_GPAFUN) | (MF_GPA11 | MF_GPA10));
outp32(REG_APBCLK, inp32(REG_APBCLK) | UART1_CKE);
uart->uiFreq = (((inp32(REG_CHIPCFG)&0xC)==0x8)?12000:27000)*1000; /*Use external clock*/
    uart->uiBaudrate = 115200;
    uart->uiDataBits = WB_DATA_BITS_8;
    uart->uiStopBits = WB_STOP_BITS_1;
    uart->uiParity = WB_PARITY_NONE;
    uart->uiRxTriggerLevel = LEVEL_1_BYTE;
   
/* Reset the TX/RX FIFOs */
outpw(REG_UART_FCR+DebugCom, 0x07);
/* Setup baud rate */
outpw(REG_UART_BAUD+DebugCom, ((0x30<<24)|((uart->uiFreq / uart->uiBaudrate)-2)));
/* Set the modem control register. Set DTR, RTS to output to LOW,
and set INT output pin to normal operating mode */
//outpb(UART_MCR, (WB_DTR_Low | WB_RTS_Low | WB_MODEM_En));
/* Setup parity, data bits, and stop bits */
outpw(REG_UART_LCR+DebugCom,(uart->uiParity | uart->uiDataBits | uart->uiStopBits));
/* Timeout if more than ??? bits xfer time */
outpw(REG_UART_TOR+DebugCom, 0x80+0x20);
/* Setup Fifo trigger level and enable FIFO */
outpw(REG_UART_FCR+DebugCom, uart->uiRxTriggerLevel|0x01);
}
int fputc(int ch, FILE *f)
{
/* Wait until the transmitter buffer is empty */  
while (!(inpw(REG_UART_FSR+DebugCom)&0x400000));
/* Transmit the character */
outpb(REG_UART_THR+DebugCom, ch);
return ch;
}
int fgetc(FILE *f)
{
while((inpw(REG_UART_ISR+DebugCom)&0x01)==0);
return(inpb(REG_UART_RBR+DebugCom));
}
int main(void)
{
int i=0;
InitDebugCom();
printf("\n\r\n\r");
printf("*** 9G-N32905 V1.00 Build by yuanxihua@21cn.com on ("__DATE__ " - " __TIME__ ")\n\r");
printf("*** 9G-N32905 V1.00 Running ...\n\r\n\r");
outp32(REG_GPIOC_OMD,0x0000FFFF);
outp32(REG_GPIOE_OMD,0x0000FFFF);
while(1)
{
  printf("run times %d\n\r",i++);
  outp32(REG_GPIOC_DOUT,0x0000FFFF);
  outp32(REG_GPIOE_DOUT,0x0000FFFF);
  Delay(500);
  outp32(REG_GPIOC_DOUT,0x00000000);
  outp32(REG_GPIOE_DOUT,0x00000000);
  Delay(500);   
}
}

/******************************************************************************
* @file     ir.c
* @brief    The Driver code for VS1838A with MINI54FDE
* @version  1.0.0
* @date     22, August, 2014
*
* @note
* Copyright (C) 2000-2014 PM9GZY by yuanxihua@21cn.com. All rights reserved.
******************************************************************************/
#include <stdio.h>
#include "Mini51Series.h"
/*
    红外线编码是数据传输和家用电器遥控常用的一种通讯方法，
其实质是一种脉宽调制的串行通讯。
    家电遥控中常用的红外线编码电路有μPD6121G型HT622型和7461型等。
μPD6121G遥控器的红外遥控系统的编码格式
    二进制“0”由0.56ms的间隔加0.565ms的脉冲表示；
    二进制“1”由0.56ms的间隔加1.685ms的脉冲表示。
每次发送的32位二进制码可分成两部分，其中
        前16位是遥控器辨识码，主要用于区别不同遥控器，
        后16位是操作码。这两个部分的后8位都是前8位的反码，用作数据校验。
每帧数据以9ms的间隔加4.5ms的脉冲作为数据头header信号。
    当键盘按下长达108ms时，发射端开始发送连续信号，与单次发送一样，
只是数据头header信号是由9ms的间隔加2.5ms的脉冲组成的。
*/
/*
_________________________________________________
|        MINI54FDE                                                LED                        |
|                                                                                                |
|        P25                                        <---                VS1838A                |
|        P24                                        --->                RED-LED                |
|_______________________________________________|
*/
#pragma anon_unions
#define TIME_INTERRUPT_PERIOD_US        128                //定时中断时间，用于计算下降沿到下降沿之间时间，也就是一个脉冲+间隙的时间
#define TIME_INFRARED_HEAD_US                13500        //数据头的时间：TH=9+4.5=13.5ms
#define TIME_INFRARED_REPEAT_US                11500        //当键盘按下长达108ms时，发送连续信号的数据头的时间：TH=9+2.5=11.5ms
#define TIME_INFRARED_ZERO_US                1125        //数据“0”的时间：T0=0.565+0.56=1.125ms
#define TIME_INFRARED_ONE_US                2245        //数据“1”的时间：T1=1.685+0.56=2.245ms
typedef enum  {IDLE=1,HEAD,DATA} irstatus_t;
typedef union {uint32_t data;struct {uint8_t data0;uint8_t data1;uint16_t address;};}irdata_t;
irdata_t ir;
uint32_t irticks=0,ircount=0,ledcount=0;
irstatus_t irwork=IDLE;
uint8_t disp_flag=0;
// The Timer1 default IRQ, declared in startup_Mini51.s.
void TMR1_IRQHandler(void)
{
        irticks++;ledcount++;
        TIMER_ClearIntFlag(TIMER1);
}
// The Port2/Port3/Port4 default IRQ, declared in startup_Mini51.s.
void GPIO234_IRQHandler(void)
{
        uint8_t irdata;
    if (P2->ISRC & BIT5)
    {    /* To check if P2.5 interrupt occurred */
                switch(irwork)
                {
                        case IDLE: irwork=HEAD;
                                break;
                        case HEAD: irwork=(irticks>((TIME_INFRARED_HEAD_US+TIME_INFRARED_REPEAT_US)/2)/TIME_INTERRUPT_PERIOD_US)?DATA:IDLE;
                                ir.data=0;ircount=0;
                                break;
                        case DATA: irdata=(irticks>((TIME_INFRARED_ZERO_US+TIME_INFRARED_ONE_US   )/2)/TIME_INTERRUPT_PERIOD_US)?1:0;
                                ir.data<<=1;ir.data|=irdata;ircount++;
                                if(ircount>=32){irwork=IDLE;disp_flag=1;}
                                break;
                }       
                irticks=0;        P2->ISRC = BIT5;
    }else
    {   /* Un-expected interrupt. Just clear all PORT2, PORT3 and PORT4 interrupts */
        P2->ISRC = P2->ISRC;        P3->ISRC = P3->ISRC;        P4->ISRC = P4->ISRC;
        printf("Un-expected interrupts. \n\r");
    }
}
void IR_test(void)
{
    /*Configure P24 for LED control */
    GPIO_SetMode(P2, BIT4, GPIO_PMD_OUTPUT);
       
        /*  Configure P2.5 as Quasi-bidirection mode and enable interrupt by falling edge trigger */
    GPIO_SetMode(P2, BIT5, GPIO_PMD_QUASI);
    GPIO_EnableInt(P2, 5, GPIO_INT_FALLING);
    NVIC_EnableIRQ(GPIO234_IRQn);
       
        // Enable IP clock
        CLK_EnableModuleClock(TMR1_MODULE);       
    // Select Timer 1 clock source from internal 22.1184MHz RC clock.
        CLK_SetModuleClock(TMR1_MODULE,CLK_CLKSEL1_TMR1_S_IRC22M,1);
        // configure timer to operate in specified mode.
        TIMER_Open(TIMER1, TIMER_PERIODIC_MODE, 7812);        //7.8125K = 0.128MS = 128US
        // start Timer counting
        TIMER_Start(TIMER1);
        // enable the Timer time-out interrupt function.
        TIMER_EnableInt(TIMER1);
    // Enable timer interrupt
    NVIC_EnableIRQ(TMR1_IRQn);
       
        while(1)
        {
                if(disp_flag)
                {
                        printf("ir.data=0x%x, ADDR=%04x DATA1=%02x /DATA1=%02x DATA0=%02x \n\r",
                                        ir.data,ir.address,ir.data1,0xff-ir.data1,ir.data0);
                        if((0xff-ir.data0)==ir.data1){P24^=1;}
                        disp_flag=0;
                }
        }
}

/******************************************************************************
* @file     ssd1963.c
* @brief    The Driver code for 480*272 16 Color LCD with NANO120KE3BN
* @version  1.0.0
* @date     05, December, 2013
*
* @note
* Copyright (C) 2000-2013 PM9GZY by yuanxihua@21cn.com. All rights reserved.
******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include "nano1xx.h"
#include "nano1xx_gpio.h"
#include "nano1xx_ebi.h"
#include "stdlib.h"
#include "core_cmInstr.h"
#include "rfid.h"
/*
_________________________________________________
| NANO120KE3BN     SSD1963  |
|            |
| EBIAD0- EBIAD15  <--->  DB0-DB15 |
| EBIWR PA10  ---->  WR#   |
| EBIRD PA11  ---->  RD#   |
| EBICS PB7   ---->  CS#   |
| PB6  EBIALE  ---->  D/C#  |
| PA8  EBIPA8  ---->  RESET#  |
| PA9  EBIPA9  ---->  LEDA  |
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define LCD_LEDA  GPIOA, 9  /* PA9=High,BackLight ON; Low,BackLight OFF */
#define LCD_RESET  GPIOA, 8  /* PA8=Low,LCD Reset;PA8=High,LCD Working   */
#define LCD_DCMD  GPIOB, 6  /* PB6=High,DATA mode; PB6=Low,COMMAND mode */
#define LCD_RESET_DELAY 100    /* LCD_RESET=Low,LCD_RESET_DELAY>=100us  */
#define BLACK         0x0000        /* 黑色：  0  , 0  , 0   */        
#define NAVY          0x000F         /* 深蓝色： 0  , 0  , 128   */        
#define DGREEN        0x03E0          /* 深绿色： 0  , 128, 0     */      
#define DCYAN         0x03EF         /* 深青色： 0  , 128, 128   */      
#define MAROON        0x7800          /* 深红色： 128, 0  , 0     */      
#define PURPLE       0x780F          /* 紫色：  128, 0  , 128   */        
#define OLIVE         0x7BE0         /* 橄榄绿： 128, 128, 0     */     
#define LGRAY         0xC618         /* 灰白色： 192, 192, 192   */      
#define DGRAY         0x7BEF          /* 深灰色： 128, 128, 128   */      
#define BLUE          0x001F          /* 蓝色：  0  , 0  , 255   */         
#define GREEN         0x07E0          /* 绿色：  0  , 255, 0     */         
#define CYAN          0x07FF          /* 青色：  0  , 255, 255   */         
#define RED           0xF800          /* 红色：  255, 0  , 0     */         
#define MAGENTA       0xF81F          /* 品红：  255, 0  , 255   */        
#define YELLOW        0xFFE0         /* 黄色：  255, 255, 0     */      
#define WHITE         0xFFFF          /* 白色：  255, 255, 255  */
#define SSD1963_HDP  0xDF01   /* HDP=479=0x01DF  */
#define SSD1963_HT  0x1302   /* HT =531=0x0213  */
#define SSD1963_HPS  0x2B00   /* HPS=43 =0x002B */
#define SSD1963_LPS  0x0800   /* LPS=8  =0x0008 */
#define SSD1963_HPW  10    /* HPW=10 =0x0A  */
#define SSD1963_VDP  0x0F01   /* VDP=271=0x010F */
#define SSD1963_VT  0x2001   /* VT =288=0x0120  */
#define SSD1963_VPS  0x0C00   /* VPS=12 =0x000C */
#define SSD1963_FPS  0x0100   /* FPS=1  =0x0001 */
#define SSD1963_VPW  10    /* VPW=10 =0x0A  */
/* Private macro -------------------------------------------------------------*/
/*  Command      Hex Code Description */
#define SSD1963_nop      0x00 /* No operation */
#define SSD1963_soft_reset     0x01 /* Software Reset */
#define SSD1963_get_power_mode    0x0A /* Get the current power mode */
#define SSD1963_get_address_mode   0x0B /* Get the frame buffer to the display panel read order */
#define SSD1963_Reserved0c     0x0C /* Reserved */
#define SSD1963_get_display_mode   0x0D /* The SSD1963 returns the Display Image Mode. */
#define SSD1963_get_tear_effect_status  0x0E /* Get the Tear Effect status */
#define SSD1963_Reserved0f     0x0F /* Reserved */
#define SSD1963_enter_sleep_mode   0x10 /* Turn off the panel. This command will pull low the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. */
#define SSD1963_exit_sleep_mode   0x11 /* Turn on the panel. This command will pull high the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. */
#define SSD1963_enter_partial_mode   0x12 /* Part of the display area is used for image display. */
#define SSD1963_enter_normal_mode   0x13 /* The whole display area is used for image display. */
#define SSD1963_exit_invert_mode   0x20 /* Displayed image colors are not inverted. */
#define SSD1963_enter_invert_mode   0x21 /* Displayed image colors are inverted. */
#define SSD1963_set_gamma_curve   0x26 /* Selects the gamma curve used by the display panel. */
#define SSD1963_set_display_off   0x28 /* Blanks the display panel */
#define SSD1963_set_display_on    0x29 /* Show the image on the display panel */
#define SSD1963_set_column_address   0x2A /* Set the column address */
#define SSD1963_set_page_address   0x2B /* Set the page address */
#define SSD1963_write_memory_start   0x2C /* Transfer image information from the host processor interface to the SSD1963 starting at the location provided by set_column_address and set_page_address  */
#define SSD1963_read_memory_start   0x2E /* Transfer image data from the SSD1963 to the host processor interface starting at the location provided by set_column_address and set_page_address  */
#define SSD1963_set_partial_area   0x30 /* Defines the partial display area on the display panel */
#define SSD1963_set_scroll_area   0x33 /* Defines the vertical scrolling and fixed area on display area */
#define SSD1963_set_tear_off    0x34 /* Synchronization information is not sent from the SSD1963 to the host processor */
#define SSD1963_set_tear_on    0x35 /* Synchronization information is sent from the SSD1963 to the host processor at the start of VFP */
#define SSD1963_set_address_mode   0x36 /* Set the read order from frame buffer to the display panel */
#define SSD1963_set_scroll_start   0x37 /* Defines the vertical scrolling starting point */
#define SSD1963_exit_idle_mode    0x38 /* Full color depth is used for the display panel */
#define SSD1963_enter_idle_mode   0x39 /* Reduce color depth is used on the display panel. */
#define SSD1963_Reserved3a     0x3A /* Reserved */
#define SSD1963_write_memory_continue  0x3C /* Transfer image information from the host processor interface to the SSD1963 from the last written location */
#define SSD1963_read_memory_continue  0x3E /* Read image data from the SSD1963 continuing after the last read_memory_continue or read_memory_start */
#define SSD1963_set_tear_scanline   0x44 /* Synchronization information is sent from the SSD1963 to the host processor when the display panel refresh reaches the provided scanline  */
#define SSD1963_get_scanline    0x45 /* Get the current scan line */
#define SSD1963_read_ddb     0xA1 /* Read the DDB from the provided location */
#define SSD1963_Reserveda8     0xA8 /* Reserved */
#define SSD1963_set_lcd_mode   0xB0 /* Set the LCD panel mode and resolution */
#define SSD1963_get_lcd_mode    0xB1 /* Get the current LCD panel mode, pad strength and resolution */
#define SSD1963_set_hori_period   0xB4 /* Set front porch */
#define SSD1963_get_hori_period   0xB5 /* Get current front porch settings */
#define SSD1963_set_vert_period   0xB6 /* Set the vertical blanking interval between last scan line and next LFRAME pulse */
#define SSD1963_get_vert_period   0xB7 /* Set the vertical blanking interval between last scan line and next LFRAME pulse */
#define SSD1963_set_gpio_conf    0xB8 /* Set the GPIO configuration. If the GPIO is not used for LCD, set the direction. Otherwise, they are toggled with LCD signals. */
#define SSD1963_get_gpio_conf    0xB9 /* Get the current GPIO configuration */
#define SSD1963_set_gpio_value    0xBA /* Set GPIO value for GPIO configured as output  */
#define SSD1963_get_gpio_status   0xBB /* Read current GPIO status. If the individual GPIO was configured as input, the value is the status of the corresponding pin. Otherwise, it is the programmed value. */
#define SSD1963_set_post_proc    0xBC /* Set the image post processor */
#define SSD1963_get_post_proc    0xBD /* Set the image post processor */
#define SSD1963_set_pwm_conf    0xBE /* Set the image post processor */
#define SSD1963_get_pwm_conf    0xBF /* Set the image post processor */
#define SSD1963_set_lcd_gen0    0xC0 /* Set the rise, fall, period and toggling properties of LCD signal generator 0 */
#define SSD1963_get_lcd_gen0    0xC1 /* Get the current settings of LCD signal generator 0 */
#define SSD1963_set_lcd_gen1    0xC2 /* Set the rise, fall, period and toggling properties of LCD signal generator 1 */
#define SSD1963_get_lcd_gen1    0xC3 /* Get the current settings of LCD signal generator 1 */
#define SSD1963_set_lcd_gen2    0xC4 /* Set the rise, fall, period and toggling properties of LCD signal generator 2 */
#define SSD1963_get_lcd_gen2    0xC5 /* Get the current settings of LCD signal generator 2 */
#define SSD1963_set_lcd_gen3    0xC6 /* Set the rise, fall, period and toggling properties of LCD signal generator 3 */
#define SSD1963_get_lcd_gen3    0xC7 /* Get the current settings of LCD signal generator 3  */
#define SSD1963_set_gpio0_rop    0xC8 /* Set the GPIO0 with respect to the LCD signal generators using ROP operation. No effect if the GPIO0 is configured as general GPIO. */
#define SSD1963_get_gpio0_rop    0xC9 /* Get the GPIO0 properties with respect to the LCD signal generators. */
#define SSD1963_set_gpio1_rop    0xCA /* Set the GPIO1 with respect to the LCD signal generators using ROP operation. No effect if the GPIO1 is configured as general GPIO. */
#define SSD1963_get_gpio1_rop    0xCB /* Get the GPIO1 properties with respect to the LCD signal generators.  */
#define SSD1963_set_gpio2_rop    0xCC /* Set the GPIO2 with respect to the LCD signal generators using ROP operation. No effect if the GPIO2 is configured as general GPIO. */
#define SSD1963_get_gpio2_rop    0xCD /* Get the GPIO2 properties with respect to the LCD signal generators. */
#define SSD1963_set_gpio3_rop    0xCE /* Set the GPIO3 with respect to the LCD signal generators using ROP operation. No effect if the GPIO3 is configured as general GPIO. */
#define SSD1963_get_gpio3_rop    0xCF /* Get the GPIO3 properties with respect to the LCD signal generators. */
#define SSD1963_set_dbc_conf    0xD0 /* Set the dynamic back light configuration 0xD1 get_dbc_conf Get the current dynamic back light configuration  */
#define SSD1963_set_dbc_th     0xD4 /* Set the threshold for each level of power saving */
#define SSD1963_get_dbc_th     0xD5 /* Get the threshold for each level of power saving */
#define SSD1963_set_pll     0xE0 /* Start the PLL. Before the start, the system was operated with the crystal oscillator or clock input */
#define SSD1963_set_pll_mn     0xE2 /* Set the PLL */
#define SSD1963_get_pll_mn     0xE3 /* Get the PLL settings */
#define SSD1963_get_pll_status    0xE4 /* Get the current PLL status */
#define SSD1963_set_deep_sleep    0xE5 /* Set deep sleep mode */
#define SSD1963_set_lshift_freq   0xE6 /* Set the LSHIFT (pixel clock) frequency */
#define SSD1963_get_lshift_freq   0xE7 /* Get current LSHIFT (pixel clock) frequency setting */
#define SSD1963_Reservede8     0xE8 /* Reserved */
#define SSD1963_Reservede9     0xE9 /* Reserved */
#define SSD1963_set_pixel_data_interface 0xF0 /* Set the pixel data format of the parallel host processor interface */
#define SSD1963_get_pixel_data_interface 0xF1 /* Get the current pixel data format settings */
#define SSD1963_Reservedff     0xFF /* Reserved */
/* Private variables ---------------------------------------------------------*/
void SSD1963_Fill(uint16_t color);
extern void SYS_Delay(uint32_t us);
void Delay_ms(uint32_t ms)
{
for(uint32_t i=0;i<ms;i++){SYS_Delay(1000);}
}
// Enable EBI function with 16-bit data width
void NANOEBI_Init(void)
{
EBI_TIMING_T sEBITiming;
UNLOCKREG();
/* Enable EBI clock  */
    CLK->AHBCLK |= CLK_AHBCLK_EBI_EN;
/* EBI function enable */
EBI->EBICON |= EBI_EBICON_ExtEN;
EBI->EBICON |= EBI_EBICON_ExtBW16;
// Enable EBIAD15-0, GPIOPA9-8
GCR->PA_L_MFP = (GCR->PA_L_MFP & 0x0000000f) | 0x22222220; //PA7_MFP-PA1_MFP = EBI AD[6]-EBI AD[12]
GCR->PA_H_MFP = (GCR->PA_H_MFP & 0xf0000000) | 0x02222200; //PA14_MFP-PA12_MFP = EBI AD[15]-EBI AD[13] PA11_MFP-PA10_MFP = EBIWR-EBIRD PA9_MFP-PA8_MFP = PA9-PA8
GCR->PB_L_MFP = (GCR->PB_L_MFP & 0x00ffffff) | 0x20000000; //PB7_MFP-PB6_MFP = EBICS-PB6
GCR->PB_H_MFP = (GCR->PB_H_MFP & 0xff00ffff) | 0x00220000; //PB13_MFP-PB12_MFP = EBI AD[1]-EBI AD[0]
GCR->PC_L_MFP = (GCR->PC_L_MFP & 0x00ffffff) | 0x22000000; //PC15_MFP-PC14_MFP = EBI AD[3]-EBI AD[2]
GCR->PC_H_MFP = (GCR->PC_H_MFP & 0x00ffffff) | 0x22000000; //PC7_MFP-PC6_MFP = EBI AD[5]-EBI AD[4]
sEBITiming.eMCLKDIV = E_EBI_MCLKDIV_1;  //OK!!! 480NS 2.083MHZ
  sEBITiming.u8ExttALE=sEBITiming.u8ExtIR2R=sEBITiming.u8ExtIR2W = 0;
sEBITiming.u8ExtIW2X=sEBITiming.u8ExttAHD=sEBITiming.u8ExttACC = 0;
EBI_SetBusTiming(sEBITiming);
*(volatile uint16_t*)EBI_BASE_ADDR=0xFFFF;  //Set D0-D15 to HIGH
GPIO_Open(GPIOA, GPIO_PMD_PMD8_OUTPUT, GPIO_PMD_PMD8_MASK);
GPIO_Open(GPIOA, GPIO_PMD_PMD9_OUTPUT, GPIO_PMD_PMD9_MASK);
GPIO_Open(GPIOB, GPIO_PMD_PMD6_OUTPUT, GPIO_PMD_PMD6_MASK);
GPIO_SetBit(LCD_LEDA);      //PA9=High,BackLight ON; Low,BackLight OFF
GPIO_SetBit(LCD_DCMD);      //PB6=High,DATA mode; PB6=Low,COMMAND mode
GPIO_SetBit(LCD_RESET);      //PA8=Low,LCD Reset;PA8=High,LCD Working
SYS_Delay(LCD_RESET_DELAY);
GPIO_ClrBit(LCD_RESET);
SYS_Delay(LCD_RESET_DELAY);
GPIO_SetBit(LCD_RESET);
// LOCKREG();
}
static void EBI_test(void) {while(1) {*(volatile uint16_t*)EBI_BASE_ADDR=0x5555;*(volatile uint16_t*)EBI_BASE_ADDR=0xAAAA;}}
static __INLINE void SSD1963_WrPAR(uint8_t *data, uint8_t len){while(len--){EBI_WRITE_DATA16(0, *data++);}}
static __INLINE void SSD1963_WrCMD(uint8_t cmd, uint8_t *data, uint8_t len){GPIO_ClrBit(LCD_DCMD);EBI_WRITE_DATA16(0, cmd);GPIO_SetBit(LCD_DCMD);SSD1963_WrPAR(data, len);}
static __INLINE void SSD1963_WrRAM(uint16_t *data, uint32_t len){while(len--){EBI_WRITE_DATA16(0, *data++);}}
void SSD1963_Init(void)
{
uint32_t Parameter;
Parameter=0x04021d;   //PLL multiplier, set PLL clock to 120M N=0x36 for 6.5M, 0x23 for 10M crystal
SSD1963_WrCMD(SSD1963_set_pll_mn,(uint8_t*)&Parameter, 3);
Parameter=0x01;    //Enable PLL
SSD1963_WrCMD(SSD1963_set_pll,(uint8_t*)&Parameter, 1);
Delay_ms(1);
Parameter=0x03;    //Use PLL output as system clock
SSD1963_WrCMD(SSD1963_set_pll,(uint8_t*)&Parameter, 1);
Delay_ms(5);
SSD1963_WrCMD(SSD1963_soft_reset,(uint8_t*)&Parameter, 0); //software reset
Delay_ms(5);
Parameter=0x16D900;   //PLL setting for PCLK, depends on resolution
SSD1963_WrCMD(SSD1963_set_lshift_freq,(uint8_t*)&Parameter, 3);
Parameter=0x0020;   //LCD SPECIFICATION
SSD1963_WrCMD(SSD1963_set_lcd_mode,(uint8_t*)&Parameter, 2);
Parameter=SSD1963_HDP;  //Set HDP
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
Parameter=SSD1963_VDP;  //Set VDP
SSD1963_WrPAR((uint8_t*)&Parameter, 3);
Parameter=SSD1963_HT;  //Set HT HSYNC
SSD1963_WrCMD(SSD1963_set_hori_period,(uint8_t*)&Parameter, 2);
Parameter=SSD1963_HPS;  //Set HPS
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
Parameter=SSD1963_HPW;  //Set HPW
SSD1963_WrPAR((uint8_t*)&Parameter, 1);
Parameter=SSD1963_LPS;  //Set LPS
SSD1963_WrPAR((uint8_t*)&Parameter, 3);
Parameter=SSD1963_VT;  //Set VT VSYNC
SSD1963_WrCMD(SSD1963_set_vert_period,(uint8_t*)&Parameter, 2);
Parameter=SSD1963_VPS;  //Set VPS
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
Parameter=SSD1963_VPW;  //Set VPW
SSD1963_WrPAR((uint8_t*)&Parameter, 1);
Parameter=SSD1963_FPS;  //Set FPS
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
Parameter=0x05;   //0x000F;    //GPIO[3:0] out 1
SSD1963_WrCMD(SSD1963_set_gpio_value,(uint8_t*)&Parameter, 1);
Parameter=0x0107;   //GPIO0 normal GPIO3=input, GPIO[2:0]=output
SSD1963_WrCMD(SSD1963_set_gpio_conf,(uint8_t*)&Parameter, 2);
Parameter=0x00;   //rotation
SSD1963_WrCMD(SSD1963_set_address_mode,(uint8_t*)&Parameter, 1);
Delay_ms(50);
Parameter=0x8006;  //set PWM for B/L
SSD1963_WrCMD(SSD1963_set_pwm_conf,(uint8_t*)&Parameter, 2);
Parameter=0x0000f001;
SSD1963_WrPAR((uint8_t*)&Parameter, 4);
Parameter=0x0d;   //设置动态背光控制配置
SSD1963_WrCMD(SSD1963_set_dbc_conf,(uint8_t*)&Parameter, 1);
   
Parameter=0x03;   //03:16-bit (565 format)
SSD1963_WrCMD(SSD1963_set_pixel_data_interface,(uint8_t*)&Parameter, 1);
// SSD1963_WrCMD(SSD1963_enter_invert_mode,(uint8_t*)&Parameter, 0); //进入图形颜色翻转模式
// Parameter=0x01808080; //处理机允许  饱和度值  亮度 对比度
// SSD1963_WrCMD(SSD1963_set_post_proc,(uint8_t*)&Parameter, 4);
SSD1963_Fill(BLACK);
SSD1963_WrCMD(SSD1963_set_display_on,(uint8_t*)&Parameter, 0); //display on
Delay_ms(5);
}
void SSD1963_Fill(uint16_t color)
{
uint32_t Parameter;
Parameter=0;
SSD1963_WrCMD(SSD1963_set_column_address,(uint8_t*)&Parameter, 2);
Parameter=SSD1963_HDP;
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
Parameter=0;
SSD1963_WrCMD(SSD1963_set_page_address,(uint8_t*)&Parameter, 2);
Parameter=SSD1963_VDP;
SSD1963_WrPAR((uint8_t*)&Parameter, 2);
SSD1963_WrCMD(SSD1963_write_memory_start,(uint8_t*)&Parameter, 0);
for(uint32_t i=0;i<130560;i++){SSD1963_WrRAM(&color, 1);}
}
void LCD_test(void)
{
uint16_t i=0,color[]={BLACK, NAVY, DGREEN, DCYAN, MAROON, PURPLE, OLIVE, LGRAY, DGRAY, BLUE, GREEN, CYAN, RED, MAGENTA, YELLOW, WHITE};
while(1)
{
  if(i++>(sizeof(color)/sizeof(color[0])))i=0;
  SSD1963_Fill(color);Delay_ms(5000);
}
}
void LCD_Configuration(void)
{
NANOEBI_Init();
SSD1963_Init();
printf("REVSH(0x1234)=0x%04x\n\r",__REVSH(0x1234));
LCD_test();
EBI_test();
}

/******************************************************************************
 * @file     pcf8563.c
 * @brief    The Driver code for PCF8563 with NUC123ZD4AN0
 * @version  1.0.0
 * @date     22, June, 2018
 *
 * @note
 * Copyright (C) 2000-2016 PM9GZY by yuanxihua@21cn.com. All rights reserved.
 ******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/*
_________________________________________________
| NUC123ZD4AN0     PCF8563  |
|            |
| SDA1 - PA10  <--->  SDA   |
| SCL1 - PA11   --->  SCL   |
| INT0 -  PB14  <---  INT   |
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
typedef enum {START=0,STOP,ACK,NAK}i2c_status_t;
typedef struct
{
 uint8_t CTL_status[2];
 uint8_t VL_second;
 uint8_t TM_minute;
 uint8_t TM_hour;
 uint8_t TM_day;
 uint8_t TM_weekday;
 uint8_t CTY_month;
 uint8_t TM_year;
 uint8_t AL_minute;
 uint8_t AL_hour;
 uint8_t AL_day;
 uint8_t AL_weekday;
 uint8_t CTL_clkout;
 uint8_t CTL_timer;
 uint8_t TM_timer;
}pcf8563_t;

//#define pbcd_to_byte(x)  (((((x)>>4)&0x0f)*10)+((x)&0x0f))
//#define byte_to_pbcd(x)  (((((x)/10)&0x0f)<<4)+(((x)%10)&0x0f))
/* Private define ------------------------------------------------------------*/
#define PCF8563_SLAVEADDR          0xA2    /* Clock i2c slave address */
#define PCF8563_CLK_HZ           100000    /* Clock i2c speed */
#define PCF8563_I2C_WAIT_US      100000    /* Clock wait time */
/* Private macro -------------------------------------------------------------*/
void PCF8563_Get_Time(struct tm *Time);
void PCF8563_Set_Time(struct tm Time);
/* Private variables ---------------------------------------------------------*/
uint8_t pbcd_to_byte(uint8_t pbcd)
{
 uint8_t msb,lsb;
 msb = (pbcd >> 4);
 lsb = pbcd & 0xf;
 if((msb>9)||(lsb>9)){return(99);}
 else{return((10*msb)+lsb);}
}  
uint8_t byte_to_pbcd(uint8_t bin)
{
 if(bin>=99){return(0x99);}/* overflow? */
 else{return(((bin/10)<<4)|(bin%10));}
}
 
static void CLK_SysTickDelayMs(uint32_t ms)
{
 for(uint32_t i=0;i<ms;i++){CLK_SysTickDelay(1000);}
}
void I2C1_Configuration(void)
{
 /* Unlock protected registers */
    SYS_UnlockReg();
 
    /* Set GPA multi-function pins for I2C1 SDA and SCL */
 SYS->GPA_MFP &= ~(SYS_GPA_MFP_PA10_Msk | SYS_GPA_MFP_PA11_Msk);
    SYS->GPA_MFP |= (SYS_GPA_MFP_PA10_I2C1_SDA | SYS_GPA_MFP_PA11_I2C1_SCL);
    SYS->ALT_MFP &= ~(SYS_ALT_MFP_PA10_Msk | SYS_ALT_MFP_PA11_Msk);
    SYS->ALT_MFP |= (SYS_ALT_MFP_PA10_I2C1_SDA | SYS_ALT_MFP_PA11_I2C1_SCL);
 
 /* Enable I2C1 module clock */
    CLK_EnableModuleClock(I2C1_MODULE);

 /* reset I2C1 modules */
 SYS_ResetModule(I2C1_RST);
  
 /* Get I2C1 clock */
// DBG_PRINTF("I2C1 clock %d Hz\n", I2C_GetClockFreq(I2C1));
 /* Lock protected registers */
    SYS_LockReg();
}

static void I2C_SEND_STATUS(I2C_T *i2c,i2c_status_t status)  
{
 uint32_t i=PCF8563_I2C_WAIT_US;
 if(status==START){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_STA_SI); }else   //set start
 if(status==STOP ){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_STO_SI); }else  //set stop
 if(status==ACK  ){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI_AA); }else  //set ack
 if(status==NAK  ){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI);  }else{;} //set nack
 while((I2C_GetIntFlag(i2c)==0)&&(i--)){CLK_SysTickDelay(1);};
// DBG_PRINTF("I2C_SS STATUS=0x%02x\n\r",I2C_GET_STATUS(i2c));
}

static void I2C_SEND_DATA(I2C_T *i2c,uint8_t data,i2c_status_t ack)  
{
 uint32_t i=PCF8563_I2C_WAIT_US;
 I2C_SET_DATA(i2c, data);
 if(ack==ACK){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI_AA);  }else  //ACK
 if(ack==NAK){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI);  }else{;} //NACK
 while((I2C_GetIntFlag(i2c)==0)&&(i--)){CLK_SysTickDelay(1);};
// DBG_PRINTF("I2C_SD=0x%02x STATUS=0x%02x\n\r",data,I2C_GET_STATUS(i2c));
}

static uint8_t I2C_READ_DATA(I2C_T *i2c,i2c_status_t ack)  
{
 uint32_t i=PCF8563_I2C_WAIT_US;
 while((I2C_GetIntFlag(i2c)==0)&&(i--)){CLK_SysTickDelay(1);};
 uint8_t data=I2C_GET_DATA(i2c);
 if(ack==ACK){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI_AA);  }else  //ACK
 if(ack==NAK){I2C_SET_CONTROL_REG(i2c, I2C_I2CON_SI);  }else{;} //NACK
// DBG_PRINTF("I2C_RD STATUS=0x%02x\n\r",I2C_GET_STATUS(i2c));
 return data;
}

void PCF8563_Get_Time(struct tm *Time)
{
 uint8_t buf[16],i;
 
 I2C1_Configuration();
 //i2c bus open 
 I2C_Open(I2C1, PCF8563_CLK_HZ);
 
 //send i2c start
 I2C_SEND_STATUS(I2C1,START);
    //send slave address & writer command
 I2C_SEND_DATA(I2C1,0xa2,ACK);
 //send register address
 I2C_SEND_DATA(I2C1,0x00,ACK);
   
 //send i2c start
 I2C_SEND_STATUS(I2C1,START);
 //send slave address & read command
 I2C_SEND_DATA(I2C1,0xa3,ACK);

 uint8_t tmp=I2C_READ_DATA(I2C1,ACK);
 for(i=0;i<15;i++)
 {
  //receive data with ack
  buf[i]= I2C_READ_DATA(I2C1,ACK);
  CLK_SysTickDelay(100);
 }
 //receive data with nak
 buf[i]= I2C_READ_DATA(I2C1,NAK);

 //send i2c stop
 I2C_SEND_STATUS(I2C1,STOP);
 
 CLK_SysTickDelay(100);    
 I2C_Close(I2C1);
// DBG_PRINTF("\n\rGETBUF:");for(i=0;i<16;i++){printf("%02x ",buf[i]);}

// memset(Time,0,sizeof(struct tm));
 Time->tm_sec  = pbcd_to_byte(buf[2]&0x7f);
 Time->tm_min  = pbcd_to_byte(buf[3]&0x7f);
 Time->tm_hour  = pbcd_to_byte(buf[4]&0x3f);
 Time->tm_mday  = pbcd_to_byte(buf[5]&0x3f);
 Time->tm_mon  = pbcd_to_byte(buf[7]&0x1f)-1; 
 Time->tm_year  = pbcd_to_byte(buf[8])+100;
}
void PCF8563_Set_Time(struct tm Time)
{
 uint8_t buf[16],i;
 
 buf[0]=0;
 buf[1]=0;
 buf[2]=byte_to_pbcd(Time.tm_sec);
 buf[3]=byte_to_pbcd(Time.tm_min);
 buf[4]=byte_to_pbcd(Time.tm_hour);
 buf[5]=byte_to_pbcd(Time.tm_mday);
 buf[7]=byte_to_pbcd(Time.tm_mon)+1;
 buf[8]=byte_to_pbcd(Time.tm_year%100);
 
// DBG_PRINTF("\n\rSETBUF:");for(i=0;i<16;i++){printf("%02x ",buf[i]);}
 I2C1_Configuration(); 
 //i2c bus open 
 I2C_Open(I2C1, PCF8563_CLK_HZ);
 
 //send i2c start
 I2C_SEND_STATUS(I2C1,START);
    //send slave address & writer command
 I2C_SEND_DATA(I2C1,0xa2,ACK);
 //send register address
 I2C_SEND_DATA(I2C1,0x00,ACK);
 
 for(i=0;i<15;i++)
 {
  //send data with ack
  I2C_SEND_DATA(I2C1,buf[i],ACK);
  CLK_SysTickDelay(100);
 }
 //send data with nak
 I2C_SEND_DATA(I2C1,buf[i],NAK);
    
    //send i2c stop
 I2C_SEND_STATUS(I2C1,STOP);
  
 CLK_SysTickDelay(100);
 I2C_Close(I2C1);
}
uint8_t PCF8563_Chk_Time(struct tm *t)
{
 uint32_t year=t->tm_year, month=t->tm_mon, day=t->tm_mday;   //防止修改指针
 uint32_t hour=t->tm_hour, minute=t->tm_min, second=t->tm_sec;  //防止修改指针
 if((year<2010)||(year>2030)){return 0;}
 if((month<1)||(month>12)){return 0;}
 if((day<1)||(day>31)){return 0;}
 if((month==4||month==6||month==9||month==11)&&(day>30)){return 0;}
 if(month==2){if(year%4){if(day>28){return 0;}}else{if(day>29){return 0;}}}
 if((hour>23)||(minute>59)||(second>60)){return 0;}
 return 1;
}

void PCF8563_test(void)
{
 __align(4) struct tm Time;
  
#if 0
 const char Month[12][4]= {"Jan","Feb","Mar","Apr","May","Jun","Jul","Aug","Sep","Oct","Nov","Dec"};char sMonth[4]= {0};
 const char *DataStr = __DATE__; //Aug 20 2016
 const char *TimeStr = __TIME__; //20:12:38
    sscanf(DataStr, "%s %d %d", sMonth, &Time.tm_mday, &Time.tm_year);
    sscanf(TimeStr, "%d:%d:%d", &Time.tm_hour, &Time.tm_min, &Time.tm_sec);
 for(int i=0;i<12;i++){if(strncmp(sMonth, Month[i],3)==0){Time.tm_mon=i;break;}}

 Time.tm_year  -= 1900;  /* years since 1900 */
// Time.tm_mon  = 8-1;   /* months since January, 0 to 11 */
// Time.tm_mday  = 20;   /* day of the month, 1 to 31 */
// Time.tm_hour  = 18;   /* hours since midnight, 0 to 23 */
// Time.tm_min  = 43;   /* minutes after the hour, 0 to 59 */
 Time.tm_sec  +=10;   /* seconds after the minute, 0 to 60
         (0 - 60 allows for the occasional leap second) */
 PCF8563_Set_Time(Time);

 while(1)
#endif
 {
  PCF8563_Get_Time(&Time);
  time_t t=mktime(&Time); // printf("t=%d %s",t, ctime(&t));
  printf("%s", asctime(&Time));

  char str[80]; strftime(str,100,"GET Time:%F %H:%M:%S\n\r",&Time); printf("%s", str);     
  CLK_SysTickDelayMs(1000);
  
  struct tm a;
  a.tm_year  = 100;  /* years since 1900 */
  a.tm_mon  = 0;  /* months since January, 0 to 11 */
  a.tm_mday  = 1;  /* day of the month, 1 to 31 */
  a.tm_hour  = 0;  /* hours since midnight, 0 to 23 */
  a.tm_min  = 0;  /* minutes after the hour, 0 to 59 */
  a.tm_sec  = 0;  /* seconds after the minute, 0 to 60 */
  
  time_t p=mktime(&a);
  printf("p=0x%08x = %d , %s",p,p,ctime(&p));
  //p=0x386d4380 = 946684800 , Sat Jan  1 00:00:00 2000
  t=0x1F4DC49F+p;//1986-08-23 14:11:43
  printf("t=0x%08x = %d , %s",t,t,ctime(&t));
  //t=1471875103 Mon Aug 22 14:11:43 2016
 }
 
}

/* Includes ------------------------------------------------------------------*/
#ifdef GAME
#include "stm32f10x.h"
#include "stdio.h"
/** @addtogroup STM32F10x_StdPeriph_Examples
  * @{
  */

/** @addtogroup GPIO_JTAG_Remap
  * @{
  */
/*
_________________________________________________
|	STM32F103						TM1629		|
|												|
|	PC0-3	CSA-CSD		---->		STB 		|
|	PE14	MISO		<----		MISO		|
|	PC6		SCLK		---->		SCLK		|
|	PC7		MOSI		---->		MOSI		|
|	PC4		KEYLED		---->		KEYLED		|
|	PC5		CPULED		---->		CPULED		|
|_______________________________________________|
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
//TM1629片选 			//STB
#define	TM1629_STB		GPIOC 					/* PC0-PC3			*/
#define	TM1629_CSA		GPIOC, GPIO_Pin_0
#define	TM1629_CSB		GPIOC, GPIO_Pin_1
#define	TM1629_CSC		GPIOC, GPIO_Pin_2
#define	TM1629_CSD		GPIOC, GPIO_Pin_3
//TM1629信号脚
#define	TM1629_SCLK		GPIOC, GPIO_Pin_6		/*PC6	SCLK*/
#define	TM1629_MOSI		GPIOC, GPIO_Pin_7		/*PC7	DIN*/
#define	TM1629_MISO		GPIOE, GPIO_Pin_14		/*PE14	DOUT*/
//键盘指示灯使能
#define	KEY_LAMP_EN		GPIOC, GPIO_Pin_4		/*PC4	RESVIN*/
#define	CPU_LAMP_EN		GPIOC, GPIO_Pin_5		/*PC5	LAMP*/
//TM1629命令
#define	TM1629_ADDR_INC			0x40
#define	TM1629_ADDR_FIXED		0x44
#define	TM1629_ADDR_BASE		0xc0
#define	TM1629_DISP_OFF			0x80
#define	TM1629_DISP_MINON		0x88
#define	TM1629_DISP_MAXON		0x8f
#define	TM1629_DISP_ONX			7
#define	TM1629_DISP_ON			(0x88+TM1629_DISP_ONX)
#define	TM1629_KEY_READ			0x42
//TM1629延时
#define	TM1629_DELAY			2				/* 640ns	*/
//TM1629应用
#define	TM1629_LED_DARK			0x00
#define	TM1629_LED_BRIGHT		0x7F
#define	TM1629_LED_BRIGHT_DOT	0xFF
#define	TM1629_CS_MASK			0xFFF0

#ifdef PART5
#define	TM1629_CS_NONE			7
#else
#define	TM1629_CS_NONE			0
#endif
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
const unsigned char TM1629_CODE[16]=
/*0x0	0x1   0x2   0x3   0x4   0x5   0x6   0x7   0x8   0x9   0xA   0xb   0xC   0xd   0xE   0xF*/
{0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x07, 0x7F, 0x6F, 0x77, 0X7C, 0x39, 0x5E, 0x79, 0x71};
const unsigned char TM1629_CODE_LED[16]=
/*0x0	0x1   0x2   0x3   0x4   0x5   0x6   0x7   0x8   0x9   0xA   0xB   0xC   0xD   0xE   0xF*/
{0xBF, 0x86, 0xDB, 0xCF, 0xE6, 0xED, 0xFD, 0x87, 0xFF, 0xEF, 0xF7, 0XFF, 0xB9, 0xBF, 0xF9, 0xF1};
const unsigned char TM1629_SEGMENT[8]=
/*  a     b     c     d     e     f     g     h*/
{0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
/* Private function prototypes -----------------------------------------------*/
void TM1629_Test(void);
void TM1629_Configuration(void);
void TM1629_Write_Byte(uint8_t wrdata);
void TM1629_Write_CMD(uint8_t chip,uint8_t wrdata);
void TM1629_Write_CMD2(uint8_t chip,uint8_t wrdata);
uint8_t TM1629_Read_Byte(void);
uint32_t TM1629_Read_Keys(unsigned char chip);
void TM1629_Activation(uint8_t chip); 
void TM1629_Write_Chip(uint8_t chip,uint8_t *led_data);
void TM1629_Write_Led(uint8_t chip,uint8_t led_index,uint8_t led_data);
void TM1629_Write_Leds(uint8_t chip,uint8_t index,uint32_t *data,uint8_t length);
void TM1629_Write_Digital(uint8_t chip,uint8_t led_index,uint8_t led_data);
void TM1629_Write_3Digital(uint8_t chip,uint8_t led_index,uint32_t led_data);
void TM1629_Write_Digitals(uint8_t chip,uint8_t led_index,uint32_t led_data,uint8_t digit_limit);
void TM1629_Write_Segment(uint8_t chip,uint8_t led_index,uint8_t led_data);
extern void SEND_RS485_STRING(char *s);
extern void Delay(__IO uint32_t nTime);
/* Private functions ---------------------------------------------------------*/

/**
  * @brief  Main program.
  * @param  None
  * @retval None
  */
void TM1629_Configuration(void)
{
	GPIO_InitTypeDef GPIO_InitStructure;
	uint32_t i,j;
	
	/* Enable GPIOC, GPIOE and AFIO clocks */
	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE);

	/* Enable GPIOC PC0-PC7 output */
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 ;
	GPIO_Init(GPIOC, &GPIO_InitStructure);	

	GPIO_ResetBits(KEY_LAMP_EN);
	GPIO_ResetBits(CPU_LAMP_EN);
	TM1629_Activation(TM1629_CS_NONE); 
	
	/* Enable GPIOE PE14 input */
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14 ;
	GPIO_Init(GPIOE, &GPIO_InitStructure);
	//全部熄灭
	for(i=1;i<=8;i++)
	{for(j=0;j<16;j++){TM1629_Write_Led(i,j,TM1629_LED_DARK);}}
	GPIO_ResetBits(KEY_LAMP_EN);
}

void TM1629_Write_Byte(uint8_t wrdata)
{
	uint8_t i; uint32_t j;

	for(i=0;i<8;i++)
	{
		GPIO_ResetBits(TM1629_SCLK);		//拉低时钟
		if(wrdata&0x01) 					//最低位判断
		{GPIO_SetBits(TM1629_MOSI);	 }		//最低位为1，则写1到DIN口
  		else
  		{GPIO_ResetBits(TM1629_MOSI);}		//最低位为0，则写0到DIN口
		for(j=0;j<TM1629_DELAY;j++){;}		//delay		
		GPIO_SetBits(TM1629_SCLK);			//拉高时钟		
		for(j=0;j<TM1629_DELAY;j++){;}		//delay
  		wrdata>>=1; 						//数据移到下一位
  	}
}
uint8_t TM1629_Read_Byte(void)
{
	uint8_t i,rddata=0x0; uint32_t j;

	for(i=0;i<8;i++)
	{
		GPIO_ResetBits(TM1629_SCLK);		//拉低时钟
		for(j=0;j<TM1629_DELAY;j++){;}		//delay
		GPIO_SetBits(TM1629_SCLK);			//拉高时钟
		rddata>>=1; 						//数据移到下一位
  		//DOUT为1，最高位付值为1
		if(GPIO_ReadInputDataBit(TM1629_MISO))	//最高位判断	
		{rddata|=0x80;}
		//DOUT为0，最高位付值为0
		for(j=0;j<TM1629_DELAY;j++){;}		//delay
  	}
  	return rddata;
}
void TM1629_Activation(uint8_t chip)
{
	uint16_t temp = (GPIO_ReadOutputData(TM1629_STB)&TM1629_CS_MASK)+chip;
	GPIO_Write(TM1629_STB, temp);
}
void TM1629_Write_CMD(uint8_t chip,uint8_t wrdata)
{	uint32_t j;
	TM1629_Activation(TM1629_CS_NONE); 
	for(j=0;j<TM1629_DELAY;j++){;}//delay
	TM1629_Activation(chip);
	TM1629_Write_Byte(wrdata);
}
void TM1629_Write_CMD2(uint8_t chip,uint8_t wrdata)
{
	TM1629_Write_CMD(chip,wrdata);
	TM1629_Activation(TM1629_CS_NONE); 
}
void TM1629_Write_Led(uint8_t chip,uint8_t led_index,uint8_t led_data)
{
	TM1629_Write_CMD(chip,TM1629_ADDR_FIXED);  
	TM1629_Write_CMD(chip,TM1629_ADDR_BASE+led_index);
	TM1629_Write_Byte(led_data);
	TM1629_Write_CMD2(chip,TM1629_DISP_ON);
}
void TM1629_Write_Digital(uint8_t chip,uint8_t led_index,uint8_t led_data)
{TM1629_Write_Led(chip,led_index,TM1629_CODE[led_data]);}

void TM1629_Write_Segment(uint8_t chip,uint8_t led_index,uint8_t led_data)
{TM1629_Write_Led(chip,led_index,TM1629_SEGMENT[led_data]);}

void TM1629_Write_Leds(uint8_t chip,uint8_t index,uint32_t *data,uint8_t length)
{
	uint8_t i;
	
	TM1629_Write_CMD(chip,TM1629_ADDR_INC);  
	TM1629_Write_CMD(chip,TM1629_ADDR_BASE+index);
	for(i=0;i<length;i++){TM1629_Write_Byte(data[i]);}
	TM1629_Write_CMD2(chip,TM1629_DISP_ON); 
}

void TM1629_Write_3Digital(uint8_t chip,uint8_t led_index,uint32_t led_data)
{
	TM1629_Write_CMD(chip,TM1629_ADDR_INC);  
	TM1629_Write_CMD(chip,TM1629_ADDR_BASE+led_index);
	TM1629_Write_Byte(TM1629_CODE[(led_data%   10)/   1]);
	TM1629_Write_Byte(TM1629_LED_DARK);
	if(led_data>99)TM1629_Write_Byte(TM1629_CODE[(led_data% 1000)/ 100]);
	else TM1629_Write_Byte(TM1629_LED_DARK);
	if(led_data> 9)TM1629_Write_Byte(TM1629_CODE[(led_data%  100)/  10]);
	else TM1629_Write_Byte(TM1629_LED_DARK);
	TM1629_Write_CMD2(chip,TM1629_DISP_ON); 
}
void TM1629_Write_Digitals(uint8_t chip,uint8_t led_index,uint32_t led_data,uint8_t digit_limit)
{
	uint8_t i,data[16];

	data[0]=TM1629_CODE[0];
	for(i=1;i<digit_limit;i++){data[i]=0x0;}
	for(i=0;(led_data>0)&&(i<digit_limit);led_data/=10)
	{data[i++]=TM1629_CODE[led_data%10];}
	
	TM1629_Write_CMD(chip,TM1629_ADDR_INC);  
	TM1629_Write_CMD(chip,TM1629_ADDR_BASE+led_index);
	for(i=0;i<digit_limit;i++)
	{TM1629_Write_Byte(data[i]);}
	TM1629_Write_CMD2(chip,TM1629_DISP_ON); 
}

void TM1629_Write_Chip(uint8_t chip,uint8_t *led_data)
{
	uint8_t i;
	TM1629_Write_CMD(chip,TM1629_ADDR_INC);  
	TM1629_Write_CMD(chip,TM1629_ADDR_BASE);
	for(i=0;i<16;i++){TM1629_Write_Byte(led_data[i]);}
	TM1629_Write_CMD2(chip,TM1629_DISP_ON); 
}

uint32_t TM1629_Read_Keys(uint8_t chip)
{
	uint32_t i,j;
	union {__IO uint32_t u32data;__IO uint8_t u8data[4];} data;

	TM1629_Write_CMD(chip,TM1629_KEY_READ);
	for(j=0;j<TM1629_DELAY;j++){;}//delay
	for(i=0;i<4;i++){data.u8data[i]=TM1629_Read_Byte();	}
	TM1629_Activation(TM1629_CS_NONE); 
	return data.u32data;
}
void TM1629_Clear_All(void)
{
	uint8_t i,data[16];
	for(i=0;i<16;i++){data[i]=0;}
	TM1629_Configuration();
	for(i=1;i<=9;i++)
	{TM1629_Write_Chip(i,data);}
}

#endif
/**
  * @}
  */

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/