#1 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-14 09:29:52
#2 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-11 20:38:14
#3 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-11 09:43:18
为了增强代码的可读性，将卡带的读写接口进行拆分，拆分成完全独立的cpu总线读写以及完全独立的ppu总线读写，新接口如下：
uint8_t (*cpu_read)(struct xnes_ctx_t * ctx, uint16_t addr);
void (*cpu_write)(struct xnes_ctx_t * ctx, uint16_t addr, uint8_t val);
uint8_t (*ppu_read)(struct xnes_ctx_t * ctx, uint16_t addr);
void (*ppu_write)(struct xnes_ctx_t * ctx, uint16_t addr, uint8_t val);
void (*ppu_step)(struct xnes_ctx_t * ctx);
void (*apu_step)(struct xnes_ctx_t * ctx);红白机系统里面有两条总线，一条是CPU总线，另一条是PPU总线，两者完全独立，CPU是无法直接访问PPU总线上的内容的，必须通过PPU的寄存器来间接访，因为PPU寄存器才8个，只靠这8个来通信效率肯定不太高，所有这8个寄存器里面又有个OAM DMA，可以通过DMA来提供通信效率。
顺便再导出一个ppu step接口，以及apu step接口，某些卡带里面带有音频扩展能力，虽然现在没实现，但先预留接口，增强扩展能力。
#4 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-11 09:16:08
现在的实现，虽说是精确到每一个指令的准确周期，但每一条指令都是原子化的，这就意味着，要么不干活，要干就干完，但实际情况，并不是这样，比如一条指令需要多个周期，取指周期，译码周期，执行周期，访问内存周期，跨页周期，条件跳转判断周期，每个周期都需要干特别的事情，说白了点，就是现在的实现粒度不够细，（当然对于模拟器也没必要特别细，比如精确到电路的电平及时序这种级别）。之所以会思考粒度问题，就是因为测试发现，nesdev网站上的那些刁钻的测试rom，就专门针对这种情况而设计的，要想通过测试，就必须将原子化的指令拆分出各种过程，这个任务是当前的重点任务了，比起支持更多的mapper这些来说，显得更关键了点。
网上有完全精确的模拟器实现，但是效率太低，不太实用，这个粒度的细分就需要好好考究了，要分但又不能太细，需要做好折中。估计接下来一段时间会优先考虑这些问题，估计结构上会做较大变化了。
#5 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-09 18:01:18
#6 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-09 17:54:36
#7 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-09 09:15:44
添加对mapper 66的支持，因140跟66比较接近，也顺便一起支持了
https://gitee.com/xboot/libxnes/blob/master/src/mapper66.c
https://gitee.com/xboot/libxnes/blob/master/src/mapper140.c
#8 Re: 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-08 11:42:21
#9 全志 SOC » libxnes开源了，这是一款纯C99标准拥有超强的可移植性，可读性，可玩性的高精度NES模拟器库，纯手写打造，感兴趣的可以在这帖子里恰饭。 » 2024-10-08 09:43:59
- xboot
- 回复： 33
开源网址：
https://github.com/xboot/libxnes
https://gitee.com/xboot/libxnes
编译了一个windows版，可以命令行执行，或者直接将rom拖到xnes即可运行
xnes.7z
#10 Re: 全志 SOC » 45块顺丰包邮买到的10.1寸保资LCD价签F1C200S 值不值 » 2024-09-26 01:08:17
11, SPI NAND Flash 128MB
xfel spinand
Found spi nand flash 'MX35LF1GE4AB' with 134217728 bytes12,上传一个dump固件，从0地址dump到0x03140000，后面UDISK分区没必要dump了。
blozi_0x0_0x3140000.7z
花了几个小时的初步研究成果，先贴出来，期待大家再接再厉！
#11 Re: 全志 SOC » 45块顺丰包邮买到的10.1寸保资LCD价签F1C200S 值不值 » 2024-09-26 01:01:51
补充一些有用的信息：
1,供电12V
2,调试串口uart1
3,ssd2828使用spi1来初始化
4,一些gpio
GPIOs 0-191, platform/pio, pio:
gpio-1 (lcd_reset ) out hi
gpio-130 (wlan_regon ) out hi
gpio-131 (wlan_hostwake ) in lo
gpio-133 (? ) out hiplatform/1c21000.pwm, 2 PWM devices
pwm-0 (lcd ): requested enabled
pwm-1 ((null) ):5,分区表
-total partitions:9-
-name- -start- -size-
bootlogo : 400000 80000
env : 480000 40000
boot : 4c0000 600000
rootfs : ac0000 f00000
rootfs_data : 19c0000 f00000
recovery : 28c0000 800000
misc : 30c0000 40000
private : 3100000 40000
UDISK : 3140000 0 6,LCD屏参，只跑38帧，估计怕性能不够吧
[ 0.223950] ***
[ 0.223961] *** Interface:
[ 0.223972] *** Parallel HV Panel
[ 0.223983] *** Lcd Frm to RGB666
[ 0.223992] ***
[ 0.224002] *** Timing:
[ 0.224013] *** lcd_x: 800
[ 0.224025] *** lcd_y: 1280
[ 0.224036] *** lcd_ht: 1220
[ 0.224047] *** lcd_hbp: 70
[ 0.224058] *** lcd_vt: 1315
[ 0.224069] *** lcd_vbp: 22
[ 0.224081] *** lcd_hspw: 20
[ 0.224092] *** lcd_vspw: 6
[ 0.224103] *** lcd_frame_frq: 38Hz
[ 0.224112] ***
[ 0.224125] *** WRN03: Recommend "lcd_dclk_frq = 96"
[ 0.224135] ***
[ 0.224145] *** LCD Panel Parameter Check End7.内核入口点0x80008000
8,设备树内存地址0x81000000
9,sd2828 RGB转MIPI初始化代码，可以从内核里逆向，或者直接上逻辑分析仪
[ 2.944530] ssd2828 spi1.0: ssd2828_probe
[ 2.949253] ssd2828 spi1.0: reg_value = 0x2828
[ 2.954267] ssd2828 spi1.0: ssd2828_init START
[ 3.312945] ssd2828 spi1.0: ssd2828_init SUCCESS!10, pinctrl-maps
Pinctrl maps:
device twi0
state default
type MUX_GROUP (2)
controlling device pio
group PD12
function twi0
device twi0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PD12
config 00000000
config 00000000
config 00000000
device twi0
state default
type MUX_GROUP (2)
controlling device pio
group PD0
function twi0
device twi0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PD0
config 00000000
config 00000000
config 00000000
device twi0
state sleep
type MUX_GROUP (2)
controlling device pio
group PD12
function io_disabled
device twi0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PD12
config 00140009
config 00000005
device twi0
state sleep
type MUX_GROUP (2)
controlling device pio
group PD0
function io_disabled
device twi0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PD0
config 00140009
config 00000005
device uart1
state default
type MUX_GROUP (2)
controlling device pio
group PA2
function uart1
device uart1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PA2
config 00000003
config 00000000
config 00000000
device uart1
state default
type MUX_GROUP (2)
controlling device pio
group PA3
function uart1
device uart1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PA3
config 00000003
config 00000000
config 00000000
device uart1
state sleep
type MUX_GROUP (2)
controlling device pio
group PA3
function io_disabled
device uart1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PA3
config 00140009
config 00000003
device uart1
state sleep
type MUX_GROUP (2)
controlling device pio
group PA2
function io_disabled
device uart1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PA2
config 00140009
config 00000003
device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC1
function spi0
device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC1
config 00000003
config 00000000
config 00000000
device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC0
function spi0
device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC0
config 00000000
config 00000000
config 00000000
device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC3
function spi0
device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC3
config 00000000
config 00000000
config 00000000
device spinand
state default
type MUX_GROUP (2)
controlling device pio
group PC2
function spi0
device spinand
state default
type CONFIGS_GROUP (4)
controlling device pio
group PC2
config 00000000
config 00000000
config 00000000
device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC0
function io_disabled
device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC0
config 00140009
config 00000005
device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC1
function io_disabled
device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC1
config 00140009
config 00000005
device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC2
function io_disabled
device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC2
config 00140009
config 00000005
device spinand
state sleep
type MUX_GROUP (2)
controlling device pio
group PC3
function io_disabled
device spinand
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PC3
config 00140009
config 00000005
device spi1
state default
type MUX_GROUP (2)
controlling device pio
group PE7
function spi1
device spi1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PE7
config 00000003
config 00000000
config 00000000
device spi1
state default
type MUX_GROUP (2)
controlling device pio
group PE9
function spi1
device spi1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PE9
config 00000000
config 00000000
config 00000000
device spi1
state default
type MUX_GROUP (2)
controlling device pio
group PE8
function spi1
device spi1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PE8
config 00000000
config 00000000
config 00000000
device spi1
state default
type MUX_GROUP (2)
controlling device pio
group PE10
function spi1
device spi1
state default
type CONFIGS_GROUP (4)
controlling device pio
group PE10
config 00000000
config 00000000
config 00000000
device spi1
state sleep
type MUX_GROUP (2)
controlling device pio
group PE7
function io_disabled
device spi1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PE7
config 00140009
config 00000005
device spi1
state sleep
type MUX_GROUP (2)
controlling device pio
group PE8
function io_disabled
device spi1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PE8
config 00140009
config 00000005
device spi1
state sleep
type MUX_GROUP (2)
controlling device pio
group PE9
function io_disabled
device spi1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PE9
config 00140009
config 00000005
device spi1
state sleep
type MUX_GROUP (2)
controlling device pio
group PE10
function io_disabled
device spi1
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PE10
config 00140009
config 00000005
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF0
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF0
config 00280009
config 00000003
config 00000000
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF1
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF1
config 00280009
config 00000003
config 00000000
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF2
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF2
config 00280009
config 00000003
config 00000000
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF3
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF3
config 00280009
config 00000003
config 00000000
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF4
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF4
config 00280009
config 00000003
config 00000000
device sdc0
state default
type MUX_GROUP (2)
controlling device pio
group PF5
function sdc0
device sdc0
state default
type CONFIGS_GROUP (4)
controlling device pio
group PF5
config 00280009
config 00000003
config 00000000
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF0
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF0
config 00140009
config 00000003
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF1
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF1
config 00140009
config 00000003
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF2
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF2
config 00140009
config 00000003
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF3
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF3
config 00140009
config 00000003
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF4
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF4
config 00140009
config 00000003
device sdc0
state sleep
type MUX_GROUP (2)
controlling device pio
group PF5
function io_disabled
device sdc0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PF5
config 00140009
config 00000003
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD1
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD1
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD2
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD2
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD3
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD3
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD4
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD4
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD5
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD5
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD6
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD6
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD7
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD7
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD8
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD8
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD9
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD9
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD10
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD10
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD11
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD11
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD13
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD13
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD14
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD14
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD15
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD15
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD16
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD16
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD17
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD17
config 00000005
config 00000000
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD18
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD18
config 00280009
config 00000005
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD19
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD19
config 00280009
config 00000005
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD20
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD20
config 00280009
config 00000005
config 00000000
device lcd0
state active
type MUX_GROUP (2)
controlling device pio
group PD21
function lcd0
device lcd0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PD21
config 00280009
config 00000005
config 00000000
device pwm0.0
state active
type MUX_GROUP (2)
controlling device pio
group PE12
function pwm0
device pwm0.0
state active
type CONFIGS_GROUP (4)
controlling device pio
group PE12
config 00140009
config 00000005
device pwm0.0
state sleep
type MUX_GROUP (2)
controlling device pio
group PE12
function io_disabled
device pwm0.0
state sleep
type CONFIGS_GROUP (4)
controlling device pio
group PE12
config 00140009
config 00000005#12 Re: 全志 SOC » 45块顺丰包邮买到的10.1寸保资LCD价签F1C200S 值不值 » 2024-09-26 00:47:15
我来贴个dts
/memreserve/ 0x81000000 0x10000;
/ {
model = "sun3iw1p1";
compatible = "arm,sun3iw1p1", "arm,sun3iw1p1";
interrupt-parent = <0x00000001>;
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
clocks {
compatible = "allwinner,sunxi-clk-init";
device_type = "clocks";
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
reg = <0x00000000 0x01c20000 0x00000000 0x000002d0>;
losc {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-clock";
clock-frequency = <0x00008000>;
clock-output-names = "losc";
};
hosc {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-clock";
clock-frequency = <0x016e3600>;
clock-output-names = "hosc";
linux,phandle = <0x00000008>;
phandle = <0x00000008>;
};
pll_cpu {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
assigned-clock-rates = <0x20e6da00>;
clock-output-names = "pll_cpu";
};
pll_audio {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
clock-output-names = "pll_audio";
linux,phandle = <0x00000002>;
phandle = <0x00000002>;
};
pll_video {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
assigned-clock-rates = <0x11b3dc40>;
clock-output-names = "pll_video";
linux,phandle = <0x00000003>;
phandle = <0x00000003>;
};
pll_ve {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
clock-output-names = "pll_ve";
linux,phandle = <0x0000000a>;
phandle = <0x0000000a>;
};
pll_ddr {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
assigned-clock-rates = <0x1298be00>;
clock-output-names = "pll_ddr";
};
pll_periph {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-pll-clock";
lock-mode = "none";
clock-output-names = "pll_periph";
linux,phandle = <0x00000004>;
phandle = <0x00000004>;
};
pll_audiox8 {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-factor-clock";
clocks = <0x00000002>;
clock-mult = <0x00000008>;
clock-div = <0x00000001>;
clock-output-names = "pll_audiox8";
};
pll_audiox4 {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-factor-clock";
clocks = <0x00000002>;
clock-mult = <0x00000008>;
clock-div = <0x00000002>;
clock-output-names = "pll_audiox4";
};
pll_audiox2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-factor-clock";
clocks = <0x00000002>;
clock-mult = <0x00000008>;
clock-div = <0x00000004>;
clock-output-names = "pll_audiox2";
};
pll_videox2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-factor-clock";
clocks = <0x00000003>;
clock-mult = <0x00000002>;
clock-div = <0x00000001>;
clock-output-names = "pll_videox2";
};
pll_periphx2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,fixed-factor-clock";
clocks = <0x00000004>;
clock-mult = <0x00000002>;
clock-div = <0x00000001>;
clock-output-names = "pll_periphx2";
};
cpu {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "cpu";
};
pll_periphahb {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "pll_periphahb";
};
ahb1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "ahb1";
linux,phandle = <0x0000001e>;
phandle = <0x0000001e>;
};
apb1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "apb1";
};
sdmmc0_mod {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc0_mod";
linux,phandle = <0x0000002a>;
phandle = <0x0000002a>;
};
sdmmc0_bus {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc0_bus";
linux,phandle = <0x0000002b>;
phandle = <0x0000002b>;
};
sdmmc0_rst {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc0_rst";
linux,phandle = <0x0000002c>;
phandle = <0x0000002c>;
};
sdmmc1_mod {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc1_mod";
linux,phandle = <0x0000002f>;
phandle = <0x0000002f>;
};
sdmmc1_bus {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc1_bus";
linux,phandle = <0x00000030>;
phandle = <0x00000030>;
};
sdmmc1_rst {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdmmc1_rst";
linux,phandle = <0x00000031>;
phandle = <0x00000031>;
};
spi0 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "spi0";
linux,phandle = <0x0000001f>;
phandle = <0x0000001f>;
};
spi1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "spi1";
linux,phandle = <0x00000026>;
phandle = <0x00000026>;
};
usbphy0 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "usbphy0";
linux,phandle = <0x00000043>;
phandle = <0x00000043>;
};
usbotg {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "usbotg";
linux,phandle = <0x00000044>;
phandle = <0x00000044>;
};
audio {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "audio";
linux,phandle = <0x00000045>;
phandle = <0x00000045>;
};
avs {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "avs";
};
codec {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "codec";
linux,phandle = <0x0000004b>;
phandle = <0x0000004b>;
};
spdif {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "spdif";
linux,phandle = <0x00000048>;
phandle = <0x00000048>;
};
debe {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "debe";
linux,phandle = <0x00000034>;
phandle = <0x00000034>;
};
defe {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "defe";
linux,phandle = <0x00000035>;
phandle = <0x00000035>;
};
tcon {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "tcon";
linux,phandle = <0x00000036>;
phandle = <0x00000036>;
};
deinterlace {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "deinterlace";
linux,phandle = <0x00000038>;
phandle = <0x00000038>;
};
tve_clk2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "tve_clk2";
linux,phandle = <0x00000037>;
phandle = <0x00000037>;
};
tve_clk1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "tve_clk1";
};
tvd {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "tvd";
linux,phandle = <0x00000039>;
phandle = <0x00000039>;
};
csi_m {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "csi_m";
linux,phandle = <0x00000040>;
phandle = <0x00000040>;
};
ve {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "ve";
linux,phandle = <0x0000000b>;
phandle = <0x0000000b>;
};
sdram {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "sdram";
};
dma {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "dma";
linux,phandle = <0x00000006>;
phandle = <0x00000006>;
};
pio {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "pio";
linux,phandle = <0x00000005>;
phandle = <0x00000005>;
};
uart0 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "uart0";
linux,phandle = <0x0000000c>;
phandle = <0x0000000c>;
};
uart1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "uart1";
linux,phandle = <0x0000000f>;
phandle = <0x0000000f>;
};
uart2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "uart2";
linux,phandle = <0x00000012>;
phandle = <0x00000012>;
};
twi0 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "twi0";
linux,phandle = <0x00000015>;
phandle = <0x00000015>;
};
twi1 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "twi1";
linux,phandle = <0x00000018>;
phandle = <0x00000018>;
};
twi2 {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "twi2";
linux,phandle = <0x0000001b>;
phandle = <0x0000001b>;
};
rsb {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "rsb";
};
cir {
#clock-cells = <0x00000000>;
compatible = "allwinner,sunxi-periph-clock";
clock-output-names = "cir";
linux,phandle = <0x00000009>;
phandle = <0x00000009>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
device_type = "soc";
ranges;
pinctrl@01c20800 {
compatible = "allwinner,sun3iw1p1-pinctrl";
reg = <0x00000000 0x01c20800 0x00000000 0x00000400>;
interrupts = <0x00000026 0x00000027 0x00000028>;
device_type = "pio";
clocks = <0x00000005>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x00000002>;
#size-cells = <0x00000000>;
#gpio-cells = <0x00000006>;
linux,phandle = <0x00000024>;
phandle = <0x00000024>;
ir@0 {
allwinner,function = "ir";
allwinner,muxsel = <0x00000004>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x00000007>;
phandle = <0x00000007>;
};
uart0@1 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x0000000e>;
phandle = <0x0000000e>;
};
uart1@1 {
allwinner,pins = "PA3", "PA2";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x00000011>;
phandle = <0x00000011>;
};
uart2@0 {
allwinner,pname = "uart2_tx", "uart2_rx";
allwinner,function = "uart2";
allwinner,muxsel = <0x00000003>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x00000013>;
phandle = <0x00000013>;
};
uart2@1 {
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x00000014>;
phandle = <0x00000014>;
};
twi0@1 {
allwinner,pins = "PD12", "PD0";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000017>;
phandle = <0x00000017>;
};
twi1@1 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000001a>;
phandle = <0x0000001a>;
};
twi2@1 {
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000001d>;
phandle = <0x0000001d>;
};
spi0@2 {
allwinner,pins = "PC0", "PC1", "PC2";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000022>;
phandle = <0x00000022>;
};
spi0@3 {
allwinner,pins = "PC3";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000023>;
phandle = <0x00000023>;
};
spi1@2 {
allwinner,pins = "PE7", "PE8", "PE9", "PE10";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000029>;
phandle = <0x00000029>;
};
csi0@0 {
allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10";
allwinner,pname = "csi0_hsync", "csi0_vsync", "csi0_pck", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
allwinner,function = "csi0";
allwinner,muxsel = <0x00000002>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
allwinner,data = <0x00000000>;
linux,phandle = <0x00000041>;
phandle = <0x00000041>;
};
csi0_sleep@0 {
allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10";
allwinner,pname = "csi0_hsync", "csi0_vsync", "csi0_pck", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
allwinner,data = <0x00000000>;
linux,phandle = <0x00000042>;
phandle = <0x00000042>;
};
pwm0@0 {
allwinner,pins = "PE12";
allwinner,function = "pwm0";
allwinner,muxsel = <0x00000004>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000003c>;
phandle = <0x0000003c>;
};
pwm0@1 {
allwinner,pins = "PE12";
allwinner,function = "pwm0";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000003d>;
phandle = <0x0000003d>;
};
pwm1@0 {
allwinner,function = "pwm1";
allwinner,muxsel = <0x00000003>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000003e>;
phandle = <0x0000003e>;
};
pwm1@1 {
allwinner,function = "pwm1";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000003f>;
phandle = <0x0000003f>;
};
sdc0@1 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x0000002e>;
phandle = <0x0000002e>;
};
sdc1@1 {
allwinner,pins = "PC0", "PC1", "PC2";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000001>;
linux,phandle = <0x00000033>;
phandle = <0x00000033>;
};
daudio0@0 {
allwinner,function = "iis0";
allwinner,muxsel = <0x00000004>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000046>;
phandle = <0x00000046>;
};
daudio0_sleep@0 {
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000047>;
phandle = <0x00000047>;
};
daudio0@1 {
allwinner,function = "iis0";
allwinner,muxsel = <0x00000002>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
};
spdif@0 {
allwinner,pins = "PD17";
allwinner,function = "spdif0";
allwinner,muxsel = <0x00000003>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x00000049>;
phandle = <0x00000049>;
};
spdif_sleep@0 {
allwinner,pins = "PD17";
allwinner,function = "io_disabled";
allwinner,muxsel = <0x00000007>;
allwinner,drive = <0x00000001>;
allwinner,pull = <0x00000000>;
linux,phandle = <0x0000004a>;
phandle = <0x0000004a>;
};
card0_boot_para@0 {
linux,phandle = <0x00000051>;
phandle = <0x00000051>;
allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
allwinner,function = "card0_boot_para";
allwinner,pname = "sdc_d1", "sdc_d0", "sdc_clk", "sdc_cmd", "sdc_d3", "sdc_d2";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000002>;
allwinner,data = <0xffffffff>;
};
card2_boot_para@0 {
linux,phandle = <0x00000052>;
phandle = <0x00000052>;
allwinner,pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16", "PC1";
allwinner,function = "card2_boot_para";
allwinner,pname = "sdc_clk", "sdc_cmd", "sdc_d0", "sdc_d1", "sdc_d2", "sdc_d3", "sdc_d4", "sdc_d5", "sdc_d6", "sdc_d7", "sdc_emmc_rst", "sdc_ds";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000003>;
allwinner,data = <0xffffffff>;
};
card1_boot_para@0 {
linux,phandle = <0x00000053>;
phandle = <0x00000053>;
allwinner,pins = "PC0", "PC1", "PC2";
allwinner,function = "card1_boot_para";
allwinner,pname = "sdc_clk", "sdc_cmd", "sdc_d0";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000003>;
allwinner,data = <0xffffffff>;
};
twi_para@0 {
linux,phandle = <0x00000054>;
phandle = <0x00000054>;
allwinner,pins = "PD12", "PD0";
allwinner,function = "twi_para";
allwinner,pname = "twi_scl", "twi_sda";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
uart_para@0 {
linux,phandle = <0x00000055>;
phandle = <0x00000055>;
allwinner,pins = "PA2", "PA3";
allwinner,function = "uart_para";
allwinner,pname = "uart_debug_tx", "uart_debug_rx";
allwinner,muxsel = <0x00000005>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
jtag_para@0 {
linux,phandle = <0x00000056>;
phandle = <0x00000056>;
allwinner,pins = "PH9", "PH10", "PH11", "PH12";
allwinner,function = "jtag_para";
allwinner,pname = "jtag_ms", "jtag_ck", "jtag_do", "jtag_di";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
twi0@0 {
linux,phandle = <0x00000057>;
phandle = <0x00000057>;
allwinner,pins = "PD12", "PD0";
allwinner,function = "twi0";
allwinner,pname = "twi0_scl", "twi0_sda";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
twi1@0 {
linux,phandle = <0x00000058>;
phandle = <0x00000058>;
allwinner,pins = "PB0", "PB1";
allwinner,function = "twi1";
allwinner,pname = "twi1_scl", "twi1_sda";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
twi2@0 {
linux,phandle = <0x00000059>;
phandle = <0x00000059>;
allwinner,pins = "PD15", "PD16";
allwinner,function = "twi2";
allwinner,pname = "twi2_scl", "twi2_sda";
allwinner,muxsel = <0x00000004>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
uart0@0 {
linux,phandle = <0x0000005a>;
phandle = <0x0000005a>;
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
allwinner,pname = "uart0_tx", "uart0_rx";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
uart1@0 {
linux,phandle = <0x0000005b>;
phandle = <0x0000005b>;
allwinner,pins = "PA2", "PA3";
allwinner,function = "uart1";
allwinner,pname = "uart1_tx", "uart1_rx";
allwinner,muxsel = <0x00000005>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
spi0@0 {
linux,phandle = <0x0000005c>;
phandle = <0x0000005c>;
allwinner,pins = "PC1";
allwinner,function = "spi0";
allwinner,pname = "spi0_cs0";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
spi0@1 {
linux,phandle = <0x0000005d>;
phandle = <0x0000005d>;
allwinner,pins = "PC0", "PC3", "PC2";
allwinner,function = "spi0";
allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
spi1@0 {
linux,phandle = <0x0000005e>;
phandle = <0x0000005e>;
allwinner,pins = "PE7";
allwinner,function = "spi1";
allwinner,pname = "spi1_cs0";
allwinner,muxsel = <0x00000004>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
spi1@1 {
linux,phandle = <0x0000005f>;
phandle = <0x0000005f>;
allwinner,pins = "PE9", "PE8", "PE10";
allwinner,function = "spi1";
allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
allwinner,muxsel = <0x00000004>;
allwinner,pull = <0xffffffff>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
nand0@0 {
linux,phandle = <0x00000060>;
phandle = <0x00000060>;
allwinner,pins = "PC0", "PC1", "PC2", "PC4", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
allwinner,function = "nand0";
allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000000>;
allwinner,drive = <0x00000001>;
allwinner,data = <0xffffffff>;
};
nand0@1 {
linux,phandle = <0x00000061>;
phandle = <0x00000061>;
allwinner,pins = "PC3", "PC5";
allwinner,function = "nand0";
allwinner,pname = "nand0_ce0", "nand0_rb0";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000001>;
allwinner,data = <0xffffffff>;
};
lcd0@0 {
linux,phandle = <0x00000062>;
phandle = <0x00000062>;
allwinner,pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD13", "PD14", "PD15", "PD16", "PD17";
allwinner,function = "lcd0";
allwinner,pname = "lcdd3", "lcdd4", "lcdd5", "lcdd6", "lcdd7", "lcdd10", "lcdd11", "lcdd12", "lcdd13", "lcdd14", "lcdd15", "lcdd19", "lcdd20", "lcdd21", "lcdd22", "lcdd23";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000000>;
allwinner,drive = <0xffffffff>;
allwinner,data = <0xffffffff>;
};
lcd0@1 {
linux,phandle = <0x00000063>;
phandle = <0x00000063>;
allwinner,pins = "PD18", "PD19", "PD20", "PD21";
allwinner,function = "lcd0";
allwinner,pname = "lcdclk", "lcdde", "lcdhsync", "lcdvsync";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000000>;
allwinner,drive = <0x00000003>;
allwinner,data = <0xffffffff>;
};
sdc0@0 {
linux,phandle = <0x00000064>;
phandle = <0x00000064>;
allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
allwinner,function = "sdc0";
allwinner,pname = "sdc0_d1", "sdc0_d0", "sdc0_clk", "sdc0_cmd", "sdc0_d3", "sdc0_d2";
allwinner,muxsel = <0x00000002>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000003>;
allwinner,data = <0xffffffff>;
};
sdc1@0 {
linux,phandle = <0x00000065>;
phandle = <0x00000065>;
allwinner,pins = "PC0", "PC1", "PC2";
allwinner,function = "sdc1";
allwinner,pname = "sdc1_clk", "sdc1_cmd", "sdc1_d0";
allwinner,muxsel = <0x00000003>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000002>;
allwinner,data = <0xffffffff>;
};
Vdevice@0 {
linux,phandle = <0x00000066>;
phandle = <0x00000066>;
allwinner,pins = "PC0", "PC1";
allwinner,function = "Vdevice";
allwinner,pname = "Vdevice_0", "Vdevice_1";
allwinner,muxsel = <0x00000004>;
allwinner,pull = <0x00000001>;
allwinner,drive = <0x00000002>;
allwinner,data = <0xffffffff>;
};
};
dma-controller@01c02000 {
compatible = "allwinner,sun3i-dma";
reg = <0x00000000 0x01c02000 0x00000000 0x00001000>;
interrupts = <0x00000012>;
clocks = <0x00000006>;
#dma-cells = <0x00000002>;
linux,phandle = <0x00000025>;
phandle = <0x00000025>;
};
timer@1c20c00 {
compatible = "allwinner,sunxi-timer";
device_type = "timer";
reg = <0x00000000 0x01c20c00 0x00000000 0x00000090>;
interrupts = <0x0000000d>;
clock-frequency = <0x016e3600>;
timer-prescale = <0x00000010>;
};
ir@01c22c00 {
compatible = "allwinner,ir";
reg = <0x00000000 0x01c22c00 0x00000000 0x00000400>;
interrupts = <0x00000006>;
pinctrl-names = "default";
pinctrl-0 = <0x00000007>;
clocks = <0x00000008 0x00000009>;
status = "okay";
};
ve@01c0e000 {
compatible = "allwinner,sunxi-cedar-ve";
reg = <0x00000000 0x01c0e000 0x00000000 0x00001000 0x00000000 0x01c00000 0x00000000 0x00003000 0x00000000 0x01c20000 0x00000000 0x00000800>;
interrupts = <0x00000022>;
clocks = <0x0000000a 0x0000000b>;
};
uart@01c25000 {
compatible = "allwinner,sun3i-uart";
device_type = "uart0";
reg = <0x00000000 0x01c25000 0x00000000 0x00000400>;
interrupts = <0x00000001>;
clocks = <0x0000000c>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x0000000e>;
uart0_port = <0x00000000>;
uart0_type = <0x00000002>;
status = "disabled";
pinctrl-0 = <0x0000005a>;
};
uart@01c25400 {
compatible = "allwinner,sun3i-uart";
device_type = "uart1";
reg = <0x00000000 0x01c25400 0x00000000 0x00000400>;
interrupts = <0x00000002>;
clocks = <0x0000000f>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x00000011>;
uart1_port = <0x00000001>;
uart1_type = <0x00000002>;
status = "okay";
pinctrl-0 = <0x0000005b>;
};
uart@01c25800 {
compatible = "allwinner,sun3i-uart";
device_type = "uart2";
reg = <0x00000000 0x01c25800 0x00000000 0x00000400>;
interrupts = <0x00000003>;
clocks = <0x00000012>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x00000013>;
pinctrl-1 = <0x00000014>;
uart2_port = <0x00000002>;
uart2_type = <0x00000004>;
status = "disabled";
};
twi@0x01c27000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "allwinner,sun3i-twi";
device_type = "twi0";
reg = <0x00000000 0x01c27000 0x00000000 0x00000400>;
interrupts = <0x00000007>;
clocks = <0x00000015>;
clock-frequency = <0x000186a0>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x00000017>;
status = "okay";
pinctrl-0 = <0x00000057>;
io_expand@0x38 {
compatible = "nxp,pcf8574a";
i2c-max-frequency = <0x000186a0>;
reg = <0x00000038>;
device_type = "io_expand";
};
touchscreen0@0x4A {
compatible = "atmel,mxt336t";
reg = <0x0000004a>;
atmel,suspend_mode = <0x00000000>;
};
touchscreen1@0x48 {
compatible = "ctp_icn85xx";
reg = <0x00000048>;
device_type = "touchscreen1";
};
rtc@0x51 {
compatible = "nxp,pcf8563";
i2c-max-frequency = <0x000186a0>;
reg = <0x00000051>;
};
sensor_gc0308@0x42 {
compatible = "allwinner,sensor_gc0308";
i2c-max-frequency = <0x000186a0>;
reg = <0x00000042>;
status = "okay";
};
};
twi@0x01c27400 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "allwinner,sun3i-twi";
device_type = "twi1";
reg = <0x00000000 0x01c27400 0x00000000 0x00000400>;
interrupts = <0x00000008>;
clocks = <0x00000018>;
clock-frequency = <0x00030d40>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x0000001a>;
status = "disabled";
pinctrl-0 = <0x00000058>;
};
twi@0x01c27800 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "allwinner,sun3i-twi";
device_type = "twi2";
reg = <0x00000000 0x01c27800 0x00000000 0x00000400>;
interrupts = <0x00000009>;
clocks = <0x0000001b>;
clock-frequency = <0x000186a0>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x0000001d>;
status = "disabled";
pinctrl-0 = <0x00000059>;
};
spi@01c05000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x00000000 0x01c05000 0x00000000 0x00001000>;
interrupts = <0x0000000a>;
clocks = <0x0000001e 0x0000001f>;
clock-frequency = <0x05f5e100>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x00000022 0x00000023>;
spi0_cs_number = <0x00000001>;
spi0_cs_bitmap = <0x00000001>;
sd-spi-sel = <0x00000024 0x00000000 0x00000001 0x00000001 0x00000001 0x00000000 0x00000000>;
sd-spi-act = <0x00000001>;
dmas = <0x00000025 0x00000000 0x00000004 0x00000025 0x00000000 0x00000004>;
dma-names = "rx", "tx";
status = "okay";
pinctrl-0 = <0x0000005c 0x0000005d>;
nor_flash@0 {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
compatible = "st,m25p64";
spi-max-frequency = <0x02faf080>;
reg = <0x00000000>;
};
};
spinand@01c05000 {
compatible = "allwinner,sunxi-spinand";
device_type = "spinand";
reg = <0x00000000 0x01c05000 0x00000000 0x00001000>;
interrupts = <0x0000000a>;
clocks = <0x0000001e 0x0000001f>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x0000005c 0x0000005d>;
pinctrl-1 = <0x00000022 0x00000023>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "okay";
};
spi@01c06000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "allwinner,sun8i-spi";
device_type = "spi1";
reg = <0x00000000 0x01c06000 0x00000000 0x00001000>;
interrupts = <0x0000000b>;
clocks = <0x0000001e 0x00000026>;
clock-frequency = <0x05f5e100>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x00000029>;
spi1_cs_number = <0x00000001>;
spi1_cs_bitmap = <0x00000001>;
status = "okay";
pinctrl-0 = <0x0000005e 0x0000005f>;
ssd2828@0 {
compatible = "ss,ssd2828";
spi-max-frequency = <0x017d7840>;
gpios = <0x00000024 0x00000000 0x00000001 0x00000000 0x00000001 0x00000001 0x00000001>;
reg = <0x00000000>;
};
};
sdmmc@01c0f000 {
compatible = "allwinner,sun3iw1p1-sdmmc0";
device_type = "sdc0";
reg = <0x00000000 0x01c0f000 0x00000000 0x00001000>;
interrupts = <0x00000017>;
clocks = <0x00000008 0x00000004 0x0000002a 0x0000002b 0x0000002c>;
clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x0000002e>;
max-frequency = <0x02faf080>;
bus-width = <0x00000004>;
cap-sdio-irq;
keep-power-in-suspend;
ignore-pm-notify;
status = "okay";
sdc0_buswidth = <0x00000004>;
pinctrl-0 = <0x00000064>;
sdc0_det = <0x00000024 0x00000000 0x00000001 0x00000000 0x00000001 0x00000003 0xffffffff>;
sdc0_use_wp = <0x00000000>;
sdc0_wp;
sdc0_isio = <0x00000000>;
sdc0_regulator = "none";
};
sdmmc@01c10000 {
compatible = "allwinner,sun3iw1p1-sdmmc1";
device_type = "sdc1";
reg = <0x00000000 0x01c10000 0x00000000 0x00001000>;
interrupts = <0x00000018>;
clocks = <0x00000008 0x00000004 0x0000002f 0x00000030 0x00000031>;
clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
pinctrl-names = "default", "sleep";
pinctrl-1 = <0x00000033>;
max-frequency = <0x02faf080>;
bus-width = <0x00000001>;
no-sdio;
no-sd;
non-removable;
cap-sdio-irq;
keep-power-in-suspend;
ignore-pm-notify;
sunxi-dly-52M-ddr4 = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000002>;
sunxi-dly-104M = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000001>;
sunxi-dly-208M = <0x00000001 0x00000000 0x00000000 0x00000000 0x00000001>;
status = "disabled";
sdc1_detmode = <0x00000004>;
sdc1_buswidth = <0x00000001>;
pinctrl-0 = <0x00000065>;
sdc1_det;
sdc1_use_wp = <0x00000000>;
sdc1_wp;
sdc1_isio = <0x00000001>;
sdc1_regulator = "none";
};
disp@0x01e00000 {
compatible = "allwinner,sunxi-disp";
reg = <0x00000000 0x01e00000 0x00000000 0x00020000 0x00000000 0x01c0c000 0x00000000 0x00001000 0x00000000 0x01e70000 0x00000000 0x00010000>;
interrupts = <0x0000001d 0x0000001f 0x0000001e 0x00000021>;
clocks = <0x00000034 0x00000035 0x00000036 0x00000037 0x00000038>;
status = "okay";
device_type = "disp";
disp_init_enable = <0x00000001>;
disp_mode = <0x00000000>;
screen0_output_type = <0x00000001>;
screen0_output_mode = <0x00000004>;
screen1_output_type = <0x00000001>;
screen1_output_mode = <0x00000004>;
fb0_framebuffer_num = <0x00000002>;
fb0_pixel_sequence = <0x00000000>;
fb0_scaler_mode_enable = <0x00000000>;
fb0_format = <0x00000000>;
fb0_width = <0x00000000>;
fb0_height = <0x00000000>;
fb1_framebuffer_num = <0x00000000>;
fb1_pixel_sequence = <0x00000000>;
fb1_scaler_mode_enable = <0x00000000>;
fb1_format = <0x00000000>;
fb1_width = <0x00000000>;
fb1_height = <0x00000000>;
lcd0_backlight = <0x00000032>;
lcd1_backlight = <0x00000032>;
lcd0_bright = <0x00000032>;
lcd0_contrast = <0x00000032>;
lcd0_saturation = <0x00000039>;
lcd0_hue = <0x00000032>;
lcd1_bright = <0x00000032>;
lcd1_contrast = <0x00000032>;
lcd1_saturation = <0x00000039>;
lcd1_hue = <0x00000032>;
};
tvd0@01c0b000 {
compatible = "allwinner,sunxi-tvd";
reg = <0x00000000 0x01c0b000 0x00000000 0x00001000>;
interrupts = <0x0000001b>;
clocks = <0x00000039>;
tvd_used = <0x00000001>;
tvd_if = <0x00000000>;
status = "okay";
};
lcd0@01c0c000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active", "sleep";
status = "okay";
device_type = "lcd0";
lcd_used = <0x00000001>;
lcd_driver_name = "ili6122_800x480";
lcd_if = <0x00000000>;
lcd_x = <0x00000320>;
lcd_y = <0x00000500>;
lcd_width = <0x00000087>;
lcd_height = <0x000000d8>;
lcd_dclk_freq = <0x0000003e>;
lcd_pwm_used = <0x00000001>;
lcd_pwm_ch = <0x00000000>;
lcd_pwm_freq = <0x0000c350>;
lcd_pwm_pol = <0x00000001>;
lcd_hbp = <0x00000046>;
lcd_ht = <0x000004c4>;
lcd_hspw = <0x00000014>;
lcd_vbp = <0x00000016>;
lcd_vt = <0x00000523>;
lcd_vspw = <0x00000006>;
lcd_hv_if = <0x00000000>;
lcd_hv_smode = <0x00000000>;
lcd_hv_s888_if = <0x00000000>;
lcd_hv_syuv_if = <0x00000000>;
lcd_hv_vspw = <0x00000006>;
lcd_hv_hspw = <0x00000014>;
lcd_hv_sync_polarity = <0x00000001>;
lcd_deu_mode = <0x00000001>;
lcd_lvds_if = <0x00000000>;
lcd_lvds_colordepth = <0x00000001>;
lcd_lvds_mode = <0x00000000>;
lcd_lvds_ch = <0x00000000>;
lcd_lvds_bitwidth = <0x00000000>;
lcd_lvds_io_cross = <0x00000000>;
lcd_cpu_if = <0x00000000>;
lcd_frm = <0x00000001>;
lcd_rb_swap = <0x00000001>;
lcd_io_phase = <0x00000000>;
lcd_gamma_en = <0x00000000>;
lcd_bright_curve_en = <0x00000000>;
lcd_cmap_en = <0x00000000>;
deu_mode = <0x00000000>;
lcdgamma4iep = <0x00000016>;
lcd_io_cfg0 = <0x00000000>;
smart_color = <0x0000005a>;
lcd_gpio_0 = <0x00000024 0x00000004 0x00000005 0x00000001 0x00000000 0xffffffff 0x00000000>;
pinctrl-0 = <0x00000062 0x00000063>;
};
pwm@01c21000 {
compatible = "allwinner,sunxi-pwm";
reg = <0x00000000 0x01c21000 0x00000000 0x00000008>;
pwm-number = <0x00000002>;
pwm-base = <0x00000000>;
pwms = <0x0000003a 0x0000003b>;
};
pwm0@01c21000 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
pinctrl-0 = <0x0000003c>;
pinctrl-1 = <0x0000003d>;
reg_base = <0x01c21000>;
reg_busy_offset = <0x00000000>;
reg_busy_shift = <0x0000001c>;
reg_enable_offset = <0x00000000>;
reg_enable_shift = <0x00000004>;
reg_clk_gating_offset = <0x00000000>;
reg_clk_gating_shift = <0x00000006>;
reg_bypass_offset = <0x00000000>;
reg_bypass_shift = <0x00000009>;
reg_pulse_start_offset = <0x00000000>;
reg_pulse_start_shift = <0x00000008>;
reg_mode_offset = <0x00000000>;
reg_mode_shift = <0x00000007>;
reg_polarity_offset = <0x00000000>;
reg_polarity_shift = <0x00000005>;
reg_period_offset = <0x00000004>;
reg_period_shift = <0x00000010>;
reg_period_width = <0x00000010>;
reg_active_offset = <0x00000004>;
reg_active_shift = <0x00000000>;
reg_active_width = <0x00000010>;
reg_prescal_offset = <0x00000000>;
reg_prescal_shift = <0x00000000>;
reg_prescal_width = <0x00000004>;
linux,phandle = <0x0000003a>;
phandle = <0x0000003a>;
};
pwm1@01c21000 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
pinctrl-0 = <0x0000003e>;
pinctrl-1 = <0x0000003f>;
reg_base = <0x01c21000>;
reg_busy_offset = <0x00000000>;
reg_busy_shift = <0x0000001d>;
reg_enable_offset = <0x00000000>;
reg_enable_shift = <0x00000013>;
reg_clk_gating_offset = <0x00000000>;
reg_clk_gating_shift = <0x00000015>;
reg_bypass_offset = <0x00000000>;
reg_bypass_shift = <0x00000018>;
reg_pulse_start_offset = <0x00000000>;
reg_pulse_start_shift = <0x00000017>;
reg_mode_offset = <0x00000000>;
reg_mode_shift = <0x00000016>;
reg_polarity_offset = <0x00000000>;
reg_polarity_shift = <0x00000014>;
reg_period_offset = <0x00000008>;
reg_period_shift = <0x00000010>;
reg_period_width = <0x00000010>;
reg_active_offset = <0x00000008>;
reg_active_shift = <0x00000000>;
reg_active_width = <0x00000010>;
reg_prescal_offset = <0x00000000>;
reg_prescal_shift = <0x0000000f>;
reg_prescal_width = <0x00000004>;
linux,phandle = <0x0000003b>;
phandle = <0x0000003b>;
};
deinterlace@01e70000 {
compatible = "allwinner,sunxi-deinterlace";
reg = <0x00000000 0x01e70000 0x00000000 0x00000080>;
interrupts = <0x00000021>;
clocks = <0x00000038 0x00000003>;
status = "okay";
};
csi_res@0x01cb0000 {
compatible = "allwinner,sunxi-csi";
reg = <0x00000000 0x01cb0000 0x00000000 0x00001000>;
clocks = <0x00000040 0x00000003 0x00000008>;
clocks-index = <0x00000000 0x00000001 0x00000002>;
status = "okay";
};
vfe@0 {
device_type = "csi0";
compatible = "allwinner,sunxi-vfe";
interrupts = <0x00000020>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x00000041>;
pinctrl-1 = <0x00000042>;
csi_sel = <0x00000000>;
csi0_sensor_list = <0x00000000>;
csi0_mck = <0x00000024 0x00000004 0x0000000b 0x00000002 0x00000001 0x00000003 0x00000000>;
status = "okay";
dev@1 {
csi0_dev0_mname = "gc0308";
csi0_dev0_twi_addr = <0x00000042>;
csi0_dev0_twi_id = <0x00000000>;
csi0_dev0_pos = "rear";
csi0_dev0_isp_used = <0x00000000>;
csi0_dev0_fmt = <0x00000000>;
csi0_dev0_stby_mode = <0x00000000>;
csi0_dev0_vflip = <0x00000000>;
csi0_dev0_hflip = <0x00000000>;
csi0_dev0_iovdd = <0x00000000>;
csi0_dev0_iovdd_vol = <0x00000000>;
csi0_dev0_avdd = <0x00000000>;
csi0_dev0_avdd_vol = <0x00000000>;
csi0_dev0_dvdd = <0x00000000>;
csi0_dev0_dvdd_vol = <0x00000000>;
csi0_dev0_afvdd = <0x00000000>;
csi0_dev0_afvdd_vol = <0x00000000>;
csi0_dev0_power_en;
csi0_dev0_reset = <0x000007fc>;
csi0_dev0_pwdn;
csi0_dev0_flash_en;
csi0_dev0_flash_mode;
csi0_dev0_af_pwdn;
csi0_dev0_act_used = <0x00000000>;
csi0_dev0_act_name = <0x00000000>;
csi0_dev0_act_slave = <0x00000000>;
status = "okay";
};
};
usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <0x00000000>;
usb_detect_type = <0x00000001>;
usb_detect_mode = <0x00000000>;
usb_drv_vbus_gpio = <0x000007ff>;
usb_host_init_state = <0x00000000>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0x00000000>;
usb_luns = <0x00000003>;
usb_serial_unique = <0x00000000>;
usb_serial_number = "20080411";
rndis_wceis = <0x00000001>;
status = "okay";
usb_id_gpio;
usb_det_vbus_gpio;
usb_board_sel = <0x00000001>;
usb_regulator_vol = <0x00000000>;
};
udc-controller@0x01c13000 {
compatible = "allwinner,sunxi-udc";
reg = <0x00000000 0x01c13000 0x00000000 0x00001000 0x00000000 0x01c00000 0x00000000 0x00000100>;
interrupts = <0x0000001a>;
clocks = <0x00000043 0x00000044>;
status = "okay";
};
otghci0-controller@0x01c13000 {
compatible = "allwinner,sunxi-hcd0";
reg = <0x00000000 0x01c13000 0x00000000 0x00001000 0x00000000 0x01c00000 0x00000000 0x00000100>;
interrupts = <0x0000001a>;
clocks = <0x00000043 0x00000044>;
hci_ctrl_no = <0x00000000>;
status = "okay";
};
daudio@0x01c22000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x00000000 0x01c22000 0x00000000 0x0000003c>;
clocks = <0x00000002 0x00000045>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x00000046>;
pinctrl-1 = <0x00000047>;
word_select_size = <0x00000020>;
pcm_sync_period = <0x00000020>;
pcm_lsb_first = <0x00000000>;
over_sample_rate = <0x00000080>;
slot_width_select = <0x00000010>;
pcm_sync_type = <0x00000000>;
pcm_start_slot = <0x00000000>;
tx_data_mode = <0x00000000>;
rx_data_mode = <0x00000000>;
tdm_config = <0x00000001>;
tdm_num = <0x00000000>;
dmas = <0x00000025 0x00000000 0x0000000e 0x00000025 0x00000000 0x0000000e>;
dma-names = "rx-tx", "rx-tx";
status = "okay";
linux,phandle = <0x0000004e>;
phandle = <0x0000004e>;
};
spdif-controller@0x01c21400 {
compatible = "allwinner,sunxi-spdif";
reg = <0x00000000 0x01c21400 0x00000000 0x00000038>;
clocks = <0x00000002 0x00000048>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x00000049>;
pinctrl-1 = <0x0000004a>;
dmas = <0x00000025 0x00000000 0x00000001 0x00000025 0x00000000 0x00000001>;
status = "disabled";
linux,phandle = <0x0000004f>;
phandle = <0x0000004f>;
};
codec@0x01c23c00 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x00000000 0x01c23c00 0x00000000 0x0000009c>;
clocks = <0x00000002 0x0000004b>;
gpio_shdn = <0x00000000>;
headphonevol = <0x0000003b>;
spkervol = <0x0000001b>;
maingain = <0x00000004>;
hp_dirused = <0x00000000>;
pa_sleep_time = <0x0000015e>;
status = "okay";
linux,phandle = <0x0000004d>;
phandle = <0x0000004d>;
};
cpudai0-controller@0x01c22000 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x00000000 0x01c23c00 0x00000000 0x0000009c>;
clocks = <0x0000004b>;
dmas = <0x00000025 0x00000000 0x0000000c 0x00000025 0x00000000 0x0000000c>;
dma-names = "rx-tx", "rx-tx";
status = "okay";
linux,phandle = <0x0000004c>;
phandle = <0x0000004c>;
};
sound@0 {
compatible = "allwinner,sunxi-codec-machine";
sunxi,cpudai-controller = <0x0000004c>;
sunxi,audio-codec = <0x0000004d>;
hp_detect_case = <0x00000000>;
status = "okay";
};
sound@1 {
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio0-controller = <0x0000004e>;
sunxi,snddaudio-codec = "nau8540.2-001d";
sunxi,snddaudio-codec-dai = "nau8540-hifi";
status = "okay";
};
sound@2 {
compatible = "allwinner,sunxi-spdif-machine";
sunxi,spdif-controller = <0x0000004f>;
status = "okay";
};
wlan {
compatible = "allwinner,sunxi-wlan";
wlan-reset-pin = <0x00000024 0x00000003 0x00000010 0x00000000 0x00000001 0x00000001 0x00000001>;
wlan-irq-pin = <0x00000024 0x00000003 0x0000000d 0x00000000 0x00000006 0x00000001 0x00000001>;
wlan_busnum = <0x00000000>;
status = "okay";
device_type = "wlan";
wlan_board_sel = <0x00000001>;
wlan_hostwake = <0x00000024 0x00000004 0x00000003 0x00000006 0xffffffff 0xffffffff 0x00000001>;
wlan_regon = <0x00000024 0x00000004 0x00000002 0x00000001 0x00000001 0x00000003 0x00000000>;
};
vdevice@0 {
compatible = "allwinner,sun3i-vdevice";
device_type = "Vdevice";
pinctrl-names = "default";
test-gpios = <0x00000024 0x00000003 0x00000001 0x00000001 0x00000002 0x00000002 0x00000001>;
status = "disabled";
pinctrl-0 = <0x00000066>;
};
keyboard {
compatible = "allwinner,keyboard_2000mv";
reg = <0x00000000 0x01c23400 0x00000000 0x00000400>;
interrupts = <0x00000016>;
status = "okay";
pwr-key = <0x00000024 0x00000003 0x0000000e 0x00000000 0x00000006 0x00000001 0x00000000>;
usb-sts = <0x00000024 0x00000003 0x0000000a 0x00000000 0x00000006 0x00000001 0x00000000>;
key_cnt = <0x00000006>;
key0 = <0x000000f8 0x00000073>;
key1 = <0x00000193 0x00000072>;
key2 = <0x0000024d 0x0000008b>;
key3 = <0x00000307 0x0000001c>;
key4 = <0x000003c1 0x00000066>;
key5 = <0x000004b9 0x00000067>;
};
pwr_off_ctrl {
compatible = "allwinner,pwr_off_ctrl";
status = "okay";
};
battery {
compatible = "allwinner,LRADC_battery";
reg = <0x00000000 0x01c23400 0x00000000 0x00000400>;
interrupts = <0x00000016>;
status = "okay";
};
wirelesskey@0 {
compatible = "allwinner,wireless-key";
gpio-key = <0x00000024 0x00000004 0x00000003 0x00000000 0x00000006 0x00000001 0x00000001>;
debounce = <0x00000000>;
status = "disabled";
};
tp_key@0x01c24800 {
compatible = "allwinner,tp_key";
reg = <0x00000000 0x01c24800 0x00000000 0x000000f0>;
interrupts = <0x00000014>;
key_cnt = <0x0000000a>;
key1 = <0x00000118 0x00000073>;
key2 = <0x00000230 0x00000072>;
key3 = <0x00000366 0x00000077>;
key4 = <0x0000048f 0x0000001c>;
key5 = <0x000005b4 0x00000175>;
key6 = <0x000006cd 0x00000066>;
key7 = <0x0000082f 0x00000000>;
key8 = <0x0000095f 0x00000000>;
key9 = <0x00000a78 0x00000000>;
key10 = <0x00000b87 0x00000000>;
status = "okay";
};
product {
device_type = "product";
version = "100";
machine = "evb";
};
platform {
device_type = "platform";
eraseflag = <0x00000001>;
debug_mode = <0x00000001>;
};
target {
device_type = "target";
boot_clock = <0x00000198>;
storage_type = <0x00000005>;
burn_key = <0x00000001>;
};
norflash {
device_type = "norflash";
size = <0x00000010>;
};
power_sply {
device_type = "power_sply";
dcdc1_vol = <0x00000bb8>;
dcdc2_vol = <0x000004b0>;
dcdc3_vol = <0x000004b0>;
dcdc4_vol = <0x000004b0>;
dcdc5_vol = <0x000005dc>;
aldo2_vol = <0x00000708>;
aldo3_vol = <0x00000bb8>;
};
pwr_ctrl {
device_type = "pwr_ctrl";
pwroff_gpio_is_irq = <0x00000000>;
};
card_boot {
device_type = "card_boot";
logical_start = <0x0000a000>;
sprite_gpio0;
};
pm_para {
device_type = "pm_para";
standby_mode = <0x00000001>;
};
card0_boot_para {
device_type = "card0_boot_para";
card_ctrl = <0x00000000>;
card_high_speed = <0x00000001>;
card_line = <0x00000004>;
pinctrl-0 = <0x00000051>;
};
card2_boot_para {
device_type = "card2_boot_para";
card_ctrl = <0x00000002>;
card_high_speed = <0x00000001>;
card_line = <0x00000008>;
pinctrl-0 = <0x00000052>;
};
card1_boot_para {
device_type = "card1_boot_para";
card_ctrl = <0x00000001>;
card_high_speed = <0x00000001>;
card_line = <0x00000001>;
pinctrl-0 = <0x00000053>;
};
twi_para {
device_type = "twi_para";
twi_port = <0x00000000>;
pinctrl-0 = <0x00000054>;
};
uart_para {
device_type = "uart_para";
uart_debug_port = <0x00000001>;
pinctrl-0 = <0x00000055>;
};
jtag_para {
device_type = "jtag_para";
jtag_enable = <0x00000000>;
pinctrl-0 = <0x00000056>;
};
dram {
device_type = "dram";
dram_clk = <0x000001e0>;
dram_type = <0x00000003>;
dram_zq = <0x000077bb>;
dram_odt_en = <0x00000001>;
dram_para1 = <0x004319f4>;
dram_para2 = <0x00000005>;
dram_mr0 = <0x00000620>;
dram_mr1 = <0x00000000>;
dram_mr2 = <0x00000008>;
dram_mr3 = <0x00000000>;
dram_tpr0 = <0x06141b10>;
dram_tpr1 = <0x00040416>;
dram_tpr2 = <0x03030306>;
dram_tpr3 = <0x00002006>;
dram_tpr4 = <0x05040405>;
dram_tpr5 = <0x05050302>;
dram_tpr6 = <0x90006644>;
dram_tpr7 = <0x42c21590>;
dram_tpr8 = <0xd05612c0>;
dram_tpr9 = <0x00083def>;
dram_tpr10 = <0x18082356>;
dram_tpr11 = <0x32034156>;
dram_tpr12 = <0x00000000>;
dram_tpr13 = <0x00000000>;
};
rtp_para {
device_type = "rtp_para";
rtp_used = <0x00000000>;
rtp_screen_size = <0x00000005>;
rtp_regidity_level = <0x00000005>;
rtp_press_threshold_enable = <0x00000000>;
rtp_press_threshold = <0x00001f40>;
rtp_sensitive_level = <0x0000000f>;
rtp_exchange_x_y_flag = <0x00000000>;
};
ctp {
device_type = "ctp";
status = "okay";
ctp_twi_id = <0x00000000>;
ctp_twi_addr = <0x00000048>;
ctp_screen_max_x = <0x00000320>;
ctp_screen_max_y = <0x000001e0>;
ctp_revert_x_flag = <0x00000001>;
ctp_revert_y_flag = <0x00000001>;
ctp_exchange_x_y_flag = <0x00000001>;
};
tkey_para {
device_type = "tkey_para";
tkey_used = <0x00000000>;
tkey_twi_id;
tkey_twi_addr;
tkey_int;
};
motor_para {
device_type = "motor_para";
motor_used = <0x00000000>;
};
nand0 {
device_type = "nand0";
nand0_support_2ch = <0x00000000>;
status = "disabled";
pinctrl-0 = <0x00000060 0x00000061>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
};
pwm0_para {
device_type = "pwm0_para";
pwm_used = <0x00000000>;
};
pwm1_para {
device_type = "pwm1_para";
pwm_used = <0x00000000>;
};
vip0 {
device_type = "vip0";
status = "disabled";
vip0_mname = "gc0308";
vip0_twi_addr = <0x00000042>;
vip0_twi_id = <0x00000000>;
vip0_isp_used = <0x00000000>;
vip0_fmt = <0x00000000>;
vip0_stby_mode = <0x00000000>;
vip0_vflip = <0x00000000>;
vip0_hflip = <0x00000000>;
vip0_iovdd;
vip0_iovdd_vol = <0x002ab980>;
vip0_avdd;
vip0_avdd_vol = <0x002ab980>;
vip0_dvdd;
vip0_dvdd_vol = <0x0016e360>;
vip0_afvdd;
vip0_afvdd_vol = <0x002ab980>;
vip0_power_en;
vip0_reset = <0x000007fc>;
vip0_pwdn;
vip0_flash_en;
vip0_flash_mode;
vip0_af_pwdn;
};
tvout_para {
device_type = "tvout_para";
tvout_used;
tvout_channel_num;
tv_en;
};
tvin_para {
device_type = "tvin_para";
tvin_used;
tvin_channel_num;
};
di {
device_type = "di";
status = "disabled";
};
smc {
device_type = "smc";
smc_used;
smc_rst;
smc_vppen;
smc_vppp;
smc_det;
smc_vccen;
smc_sck;
smc_sda;
};
gsensor_para {
device_type = "gsensor_para";
gsensor_used = <0x00000000>;
gsensor_twi_id = <0x00000002>;
gsensor_twi_addr = <0x00000018>;
gsensor_int1 = <0x00000024 0x00000000 0x00000009 0x00000006 0x00000001 0xffffffff 0xffffffff>;
gsensor_int2;
};
gps_para {
device_type = "gps_para";
};
gy_para {
device_type = "gy_para";
gy_used = <0x00000000>;
gy_twi_id = <0x00000002>;
gy_twi_addr = <0x0000006a>;
gy_int1 = <0x00000024 0x00000000 0x0000000a 0x00000006 0x00000001 0xffffffff 0xffffffff>;
gy_int2;
};
ls_para {
device_type = "ls_para";
ls_used = <0x00000000>;
ls_twi_id = <0x00000002>;
ls_twi_addr = <0x00000023>;
ls_int = <0x00000024 0x00000000 0x0000000c 0x00000006 0x00000001 0xffffffff 0xffffffff>;
};
compass_para {
device_type = "compass_para";
compass_used = <0x00000000>;
compass_twi_id = <0x00000002>;
compass_twi_addr = <0x0000000d>;
compass_int = <0x00000024 0x00000000 0x0000000b 0x00000006 0x00000001 0xffffffff 0xffffffff>;
};
bt_para {
device_type = "bt_para";
bt_used;
bt_uart_id;
bt_wakeup;
bt_gpio;
bt_rst;
};
audiospdif {
device_type = "audiospdif";
status = "disabled";
};
spdif_machine {
device_type = "spdif_machine";
status = "disabled";
};
audiohdmi {
device_type = "audiohdmi";
status = "disabled";
};
hdmi_machine {
device_type = "hdmi_machine";
status = "disabled";
};
pmu0 {
device_type = "pmu0";
status = "disabled";
pmu_id = <0x00000006>;
pmu_twi_addr = <0x00000034>;
pmu_twi_id = <0x00000001>;
pmu_irq_id = <0x00000000>;
pmu_chg_ic_temp = <0x00000000>;
pmu_battery_rdc = <0x00000064>;
pmu_battery_cap = <0x00000000>;
pmu_runtime_chgcur = <0x000001c2>;
pmu_suspend_chgcur = <0x000005dc>;
pmu_shutdown_chgcur = <0x000005dc>;
pmu_init_chgvol = <0x00001068>;
pmu_ac_vol = <0x00000fa0>;
pmu_ac_cur = <0x00000000>;
pmu_usbpc_vol = <0x00001130>;
pmu_usbpc_cur = <0x000001f4>;
pmu_battery_warning_level1 = <0x0000000f>;
pmu_battery_warning_level2 = <0x00000000>;
pmu_chgled_func = <0x00000000>;
pmu_chgled_type = <0x00000000>;
pmu_bat_para1 = <0x00000000>;
pmu_bat_para2 = <0x00000000>;
pmu_bat_para3 = <0x00000000>;
pmu_bat_para4 = <0x00000000>;
pmu_bat_para5 = <0x00000000>;
pmu_bat_para6 = <0x00000000>;
pmu_bat_para7 = <0x00000000>;
pmu_bat_para8 = <0x00000000>;
pmu_bat_para9 = <0x00000005>;
pmu_bat_para10 = <0x00000008>;
pmu_bat_para11 = <0x00000009>;
pmu_bat_para12 = <0x0000000a>;
pmu_bat_para13 = <0x0000000d>;
pmu_bat_para14 = <0x00000010>;
pmu_bat_para15 = <0x00000014>;
pmu_bat_para16 = <0x00000021>;
pmu_bat_para17 = <0x00000029>;
pmu_bat_para18 = <0x0000002e>;
pmu_bat_para19 = <0x00000032>;
pmu_bat_para20 = <0x00000035>;
pmu_bat_para21 = <0x00000039>;
pmu_bat_para22 = <0x0000003d>;
pmu_bat_para23 = <0x00000043>;
pmu_bat_para24 = <0x00000049>;
pmu_bat_para25 = <0x0000004e>;
pmu_bat_para26 = <0x00000054>;
pmu_bat_para27 = <0x00000058>;
pmu_bat_para28 = <0x0000005c>;
pmu_bat_para29 = <0x0000005d>;
pmu_bat_para30 = <0x0000005e>;
pmu_bat_para31 = <0x0000005f>;
pmu_bat_para32 = <0x00000064>;
pmu_bat_temp_enable = <0x00000000>;
pmu_bat_charge_ltf = <0x000008d5>;
pmu_bat_charge_htf = <0x00000184>;
pmu_bat_shutdown_ltf = <0x00000c80>;
pmu_bat_shutdown_htf = <0x000000ed>;
pmu_bat_temp_para1 = <0x00001d2a>;
pmu_bat_temp_para2 = <0x00001180>;
pmu_bat_temp_para3 = <0x00000dbe>;
pmu_bat_temp_para4 = <0x00000ae2>;
pmu_bat_temp_para5 = <0x000008af>;
pmu_bat_temp_para6 = <0x000006fc>;
pmu_bat_temp_para7 = <0x000005a8>;
pmu_bat_temp_para8 = <0x000003c9>;
pmu_bat_temp_para9 = <0x00000298>;
pmu_bat_temp_para10 = <0x000001d2>;
pmu_bat_temp_para11 = <0x00000189>;
pmu_bat_temp_para12 = <0x0000014d>;
pmu_bat_temp_para13 = <0x0000011b>;
pmu_bat_temp_para14 = <0x000000f2>;
pmu_bat_temp_para15 = <0x000000b3>;
pmu_bat_temp_para16 = <0x00000086>;
pmu_powkey_off_time = <0x00001770>;
pmu_powkey_off_func = <0x00000000>;
pmu_powkey_off_en = <0x00000001>;
pmu_powkey_long_time = <0x000005dc>;
pmu_powkey_on_time = <0x000003e8>;
};
pmu0_regu {
device_type = "pmu0_regu";
regulator_count = <0x00000017>;
regulator1 = "axp28_rtc";
regulator2 = "axp28_aldo1";
regulator3 = "axp28_aldo2";
regulator4 = "axp28_aldo3";
regulator5 = "axp28_dldo1";
regulator6 = "axp28_dldo2";
regulator7 = "axp28_dldo3";
regulator8 = "axp28_dldo4";
regulator9 = "axp28_eldo1";
regulator0 = "axp28_eldo2";
regulator11 = "axp28_eldo3";
regulator12 = "axp28_fldo1";
regulator13 = "axp28_fldo2";
regulator14 = "axp28_dcdc1";
regulator15 = "axp28_dcdc2";
regulator16 = "axp28_dcdc3";
regulator17 = "axp28_dcdc4";
regulator18 = "axp28_dcdc5";
regulator19 = "axp28_dcdc6";
regulator20 = "axp28_dcdc7";
regulator21 = "axp28_gpio0ldo";
regulator22 = "axp28_gpio1ldo";
};
dvfs_table {
device_type = "dvfs_table";
max_freq = <0x47868c00>;
min_freq = <0x1c9c3800>;
LV_count = <0x00000008>;
LV1_freq = <0x5b8d8000>;
LV1_volt = <0x000005dc>;
LV2_freq = <0x501bd000>;
LV2_volt = <0x000005b4>;
LV3_freq = <0x47868c00>;
LV3_volt = <0x00000528>;
LV4_freq = <0x3c14dc00>;
LV4_volt = <0x000004b0>;
LV5_freq = <0x30a32c00>;
LV5_volt = <0x0000044c>;
LV6_freq = <0x269fb200>;
LV6_volt = <0x00000410>;
LV7_freq = <0x00000000>;
LV7_volt = <0x00000410>;
LV8_freq = <0x00000000>;
LV8_volt = <0x00000410>;
};
fel_key {
device_type = "fel_key";
keyen_flag = <0x00000000>;
fel_key_max = <0x000001aa>;
fel_key_min = <0x00000100>;
};
partitions {
device_type = "partitions";
bootlogo {
device_type = "bootlogo";
offset = <0x00002000>;
size = <0x00000400>;
};
env {
device_type = "env";
offset = <0x00002400>;
size = <0x00000200>;
};
boot {
device_type = "boot";
offset = <0x00002600>;
size = <0x00003000>;
};
rootfs {
device_type = "rootfs";
offset = <0x00005600>;
size = <0x00007800>;
};
rootfs_data {
device_type = "rootfs_data";
offset = <0x0000ce00>;
size = <0x00007800>;
};
recovery {
device_type = "recovery";
offset = <0x00014600>;
size = <0x00004000>;
};
misc {
device_type = "misc";
offset = <0x00018600>;
size = <0x00000200>;
};
private {
device_type = "private";
offset = <0x00018800>;
size = <0x00000200>;
};
UDISK {
device_type = "UDISK";
offset = <0x00018a00>;
size = <0x00000000>;
};
};
};
aliases {
serial0 = "/soc/uart@01c25000", "/soc/uart@01c25000";
serial1 = "/soc/uart@01c25400", "/soc/uart@01c25400";
serial2 = "/soc/uart@01c25800", "/soc/uart@01c25800";
twi0 = "/soc/twi@0x01c27000", "/soc/twi@0x01c27000";
twi1 = "/soc/twi@0x01c27400", "/soc/twi@0x01c27400";
twi2 = "/soc/twi@0x01c27800", "/soc/twi@0x01c27800";
spi0 = "/soc/spi@01c05000", "/soc/spi@01c05000";
spinand = "/soc/spinand@01c05000", "/soc/spinand@01c05000";
spi1 = "/soc/spi@01c06000", "/soc/spi@01c06000";
mmc0 = "/soc/sdmmc@01c0f000", "/soc/sdmmc@01c0f000";
mmc1 = "/soc/sdmmc@01c10000", "/soc/sdmmc@01c10000";
global_timer0 = "/soc/timer@1c20c00", "/soc/timer@1c20c00";
csi_res0 = "/soc/csi_res@0x01cb0000", "/soc/csi_res@0x01cb0000";
vfe0 = "/soc/vfe@0", "/soc/vfe@0";
disp = "/soc/disp@0x01e00000", "/soc/disp@0x01e00000";
lcd0 = "/soc/lcd0@01c0c000", "/soc/lcd0@01c0c000";
tvd = "/soc/tvd0@01c0b000", "/soc/tvd0@01c0b000";
pwm = "/soc/pwm@01c21000", "/soc/pwm@01c21000";
pwm0 = "/soc/pwm0@01c21000", "/soc/pwm0@01c21000";
pwm1 = "/soc/pwm1@01c21000", "/soc/pwm1@01c21000";
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x01c25000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
linux,initrd-start = <0x00000000 0x00000000>;
linux,initrd-end = <0x00000000 0x00000000>;
};
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ejs";
reg = <0x00000000>;
};
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x00000000 0x01c00000 0x00000000 0x00000100>;
};
ion {
compatible = "allwinner,sunxi-ion";
system {
type = <0x00000000>;
};
cma {
type = <0x00000004>;
};
system_contig {
type = <0x00000001>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x02000000>;
};
interrupt-controller@01c20400 {
compatible = "allwinner,sun3i-intc";
#interrupt-cells = <0x00000001>;
#address-cells = <0x00000000>;
device_type = "intc";
interrupt-controller;
reg = <0x00000000 0x01c20400 0x00000000 0x00001000>;
linux,phandle = <0x00000001>;
phandle = <0x00000001>;
};
watchdog@01c20ca0 {
compatible = "allwinner,sun3i-wdt";
reg = <0x00000000 0x01c20ca0 0x00000000 0x00000018>;
};
};#14 Re: 全志 SOC » 全志有fel模式，瑞芯微有maskrom模式，为了给裸机开发舔砖加瓦，fel模式有xfel工具，那么maskrom模式就需要xrock工具了 » 2024-09-21 17:48:41
v1.1.2版本发布，这个版本增加了arm64核相关payload。
usage:
xrock maskrom <ddr> <usbplug> [--rc4-off] - Initial chip using ddr and usbplug in maskrom mode
xrock download <loader> - Initial chip using loader in maskrom mode
xrock ready - Show chip ready or not
xrock version - Show chip version
xrock capability - Show capability information
xrock reset [maskrom] - Reset chip to normal or maskrom mode
xrock dump <address> <length> - Dump memory region in hex format
xrock read <address> <length> <file> - Read memory to file
xrock write <address> <file> - Write file to memory
xrock exec <address> [dtb] - Call function address(Recommend to use extra command)
xrock otp <length> - Dump otp memory in hex format
xrock sn - Read serial number
xrock sn <string> - Write serial number
xrock vs dump <index> <length> [type] - Dump vendor storage in hex format
xrock vs read <index> <length> <file> [type] - Read vendor storage
xrock vs write <index> <file> [type] - Write vendor storage
xrock storage - Read storage media list
xrock storage <index> - Switch storage media and show list
xrock flash - Detect flash and show information
xrock flash erase <sector> <count> - Erase flash sector
xrock flash read <sector> <count> <file> - Read flash sector to file
xrock flash write <sector> <file> - Write file to flash sector
extra:
xrock extra maskrom --rc4 <on|off> [--sram <file> --delay <ms>] [--dram <file> --delay <ms>] [...]
xrock extra maskrom-dump-arm32 --rc4 <on|off> --uart <register> <address> <length>
xrock extra maskrom-dump-arm64 --rc4 <on|off> --uart <register> <address> <length>
xrock extra maskrom-write-arm32 --rc4 <on|off> <address> <file>
xrock extra maskrom-write-arm64 --rc4 <on|off> <address> <file>
xrock extra maskrom-exec-arm32 --rc4 <on|off> <address>
xrock extra maskrom-exec-arm64 --rc4 <on|off> <address>比如你想dump rk3588的bootrom,在maskrom模式下，执行如下指令即可，调试串口会以16进制方式打印出dump内容。
xrock extra maskrom-dump-arm64 --rc4 off --uart 0xfeb50000 0xffff0000 1024#15 Re: 全志 SOC » 全志有fel模式，瑞芯微有maskrom模式，为了给裸机开发舔砖加瓦，fel模式有xfel工具，那么maskrom模式就需要xrock工具了 » 2024-09-20 13:13:41
xrock终于突破瑞芯微的限制，瑞芯微在执行权限上，限制得比较死，要想在无flash的板子上运行程序，基本是不可能的事，都是需要将程序预先烧录到flash中，然后复位，才能实现引导，这给裸机调试带来很多麻烦，如果能直接将裸机程序烧写到ram中再执行，将大大提升开发的效率。
通过仔细研究maskrom后发现，我们完全可以在maskrom模式下编写各种payload，来实现各种骚操作。比如，初始化DDR，写程序到RAM中，指定地址执行等，还有很多其他奇淫技巧，比如开jtag，操作寄存器，你甚至都可以直接用jtag调试器来调试bootrom。
贴一个write指令的payload。
先保存maskrom上下文，再memmove，将附在此payload尾巴上的程序搬移到目的地址。最后在恢复maskrom环境，再次进去maskrom模式。
sudo xrock extra maskrom --rc4 off --sram rv1106_ddr_924MHz_v1.15.bin --delay 10
sudo xrock extra maskrom-write-arm32 --rc4 off 0x00000000 xstar.bin
sudo xrock extra maskrom-exec-arm32 --rc4 off 0x00000000上面这些命令，就是先初始化RV1106的内部DDR,再将xstar.bin程序写入到DDR空间，DDR空间从0地址开始，然后再执行0地址的程序。
这里借用了rkbin里面的ddr初始化程序。
xrock maskrom <ddr> <usbplug> [--rc4-off] - Initial chip using ddr and usbplug in maskrom mode
xrock download <loader> - Initial chip using loader in maskrom mode
xrock ready - Show chip ready or not
xrock version - Show chip version
xrock capability - Show capability information
xrock reset [maskrom] - Reset chip to normal or maskrom mode
xrock dump <address> <length> - Dump memory region in hex format
xrock read <address> <length> <file> - Read memory to file
xrock write <address> <file> - Write file to memory
xrock exec <address> [dtb] - Call function address(Recommend to use extra command)
xrock otp <length> - Dump otp memory in hex format
xrock sn - Read serial number
xrock sn <string> - Write serial number
xrock vs dump <index> <length> [type] - Dump vendor storage in hex format
xrock vs read <index> <length> <file> [type] - Read vendor storage
xrock vs write <index> <file> [type] - Write vendor storage
xrock storage - Read storage media list
xrock storage <index> - Switch storage media and show list
xrock flash - Detect flash and show information
xrock flash erase <sector> <count> - Erase flash sector
xrock flash read <sector> <count> <file> - Read flash sector to file
xrock flash write <sector> <file> - Write file to flash sector
extra:
xrock extra maskrom --rc4 <on|off> [--sram <file> --delay <ms>] [--dram <file> --delay <ms>] [...]
xrock extra maskrom-write-arm32 --rc4 <on|off> <address> <file>
xrock extra maskrom-exec-arm32 --rc4 <on|off> <address>这是完整指令说明。
#16 Re: 全志 SOC » 全志有fel模式，瑞芯微有maskrom模式，为了给裸机开发舔砖加瓦，fel模式有xfel工具，那么maskrom模式就需要xrock工具了 » 2024-09-10 16:00:57
补充一个xrock dump系统固件仅能支持32MB的问题，这问题主要出现在官方实现的uboot源码里做了限制，rockusb协议实现限制了读操作的最大范围，超过了限定区域全部返回0xCC，要修复此问题也比较简单，删除限制代码或者放宽RKUSB_READ_LIMIT_ADDR宏定义的值。看一下如下代码就了解了。
#define RKUSB_READ_LIMIT_ADDR (32 * 2048) /* 32MB */static int rkusb_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
{
struct blk_desc *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
int ret;
if ((blkstart + blkcnt) > RKUSB_READ_LIMIT_ADDR) {
memset(buf, 0xcc, blkcnt * SECTOR_SIZE);
return blkcnt;
} else {
ret = blk_dread(block_dev, blkstart, blkcnt, buf);
if (!ret)
ret = -EIO;
return ret;
}
}此限制仅针对于dump，写入是没有任何限制的。uboot有源码修复相对简单，但闭源的usbplug需要修复此问题的话，就只能去hack了，实测不是每个usbplug都做了限制，当遇到此问题时，需要注意下此限制。
#17 Re: 全志 SOC » 全志有fel模式，瑞芯微有maskrom模式，为了给裸机开发舔砖加瓦，fel模式有xfel工具，那么maskrom模式就需要xrock工具了 » 2024-09-06 12:15:35
转眼开发xrock已经三年了，最近有闲情，通过逆向并实现了部分指令，包括序列号读写，vendor storage访问，多存储器切换，otp dump等。
usage:
xrock maskrom <ddr> <usbplug> [--rc4-off] - Initial chip using ddr and usbplug in maskrom mode
xrock download <loader> - Initial chip using loader in maskrom mode
xrock ready - Show chip ready or not
xrock version - Show chip version
xrock capability - Show capability information
xrock reset [maskrom] - Reset chip to normal or maskrom mode
xrock dump <address> <length> - Dump memory region in hex format
xrock read <address> <length> <file> - Read memory to file
xrock write <address> <file> - Write file to memory
xrock exec <address> [dtb] - Call function address
xrock otp <length> - Dump otp memory in hex format
xrock sn - Read serial number
xrock sn <string> - Write serial number
xrock vs dump <index> <length> [type] - Dump vendor storage in hex format
xrock vs read <index> <length> <file> [type] - Read vendor storage
xrock vs write <index> <file> [type] - Write vendor storage
xrock storage - Read storage media list
xrock storage <index> - Switch storage media and show list
xrock flash - Detect flash and show information
xrock flash erase <sector> <count> - Erase flash sector
xrock flash read <sector> <count> <file> - Read flash sector to file
xrock flash write <sector> <file> - Write file to flash sector
extra:
xrock extra maskrom --rc4 <on|off> [--sram <file> --delay <ms>] [--dram <file> --delay <ms>] [...]当前版本为v1.0.9
https://gitee.com/xboot/xrock/releases
#19 Re: 计算机图形/GUI/RTOS/FileSystem/OpenGL/DirectX/SDL2 » 基于LVGL的嵌入式声明式UI框架zdec略有小成！ » 2024-01-30 09:25:45
#21 Re: 全志 SOC » xfel执行初始化T113 DDR后USB无响应 » 2023-07-25 17:21:49
#23 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-13 15:04:28
我来当小白鼠了，CHIP ID是可以改写的。在T113芯片上测试
先读取出厂的CHIP ID，前4个字节为93406000
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
93406000 0c004814 01426250 48671b4b 将前4个字节修改为0xffffffff
$ xfel extra efuse write32 0x00 0xffffffff再次查看芯片的CHIP ID，已经被修改为0xffffffff了。
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
ffffffff 0c004814 01426250 48671b4b 结论，关于CHIP ID，你真的可以用xfel工具，自己重写一个。如果全志出厂时，CHIP ID全0的话，你是真的可以完美复制出两个一模一样的芯片。
我印象中，当时还在研究D1，手上拿到了一颗F133样片，里面的SID就是全0，当时还很奇怪，为何没有SID呢，原来仅仅是没烧写。
一转眼，距离离研究D1芯片，已经过去2年了， 这该死的时间，也不慢一点。
#32 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 21:21:58
有厂家提前烧好的区域，比如chipid，thermal-sensor，但这些都还是可见的，全志在启用加密引导功能后，有部分EFUSE就不可见了，读取会直接返回0。
全志SOC，写EFUSE，必须通过SID控制器，通过寄存器操作来写入，但读取EFUSE，有两种方案，一种是比较简单的SRAM映射，直接用MMIO来访问就可以了，这里有个细节需要注意，仅支持word字访问，不支持byte字节访问，还有一种方案，就是用SID控制器来读取。
SRAM映射方案，只有在SOC重启时更新一次，所以，如果新写入了efuse，想不重启来查看的话，就需要用SID控制器来读取。
启用加密模式后，SID控制器访问也会受限，需要用SMC相关指令来访问，具体还没有研究加密后的SID控制器。
#33 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 16:32:31
上面的验签过程，有两种应用场景，需求不同，思路也会不同。
第一种，自己的产品防盗版，没有升级需求，或者loader没有升级需求，也就是某部分固件，完全不变化，且需防盗版抄袭。
这种需求，你需要将CPU ID + 固件或者loader，两者所有信息进行sha256摘要运算，并用ECDSA256对SHA256的摘要进行签名，存储在EFUSE里。当别人复制产品时，复制了SPI NOR FLASH，复制了EFUSE 签名，因CPU ID不同，也无法正常验签。
第二种，自己是方案商仅出主控芯片，客户自行烧录生产，有固件及各种烧写工具。这种情况要求客户必须从你这里走芯片，而不能从市面上随便购买。
对于这种需求，仅需要对CPU ID 进行SHA256摘要运算，并用ECDSA256对SHA256的摘要进行签名，存储在EFUSE里，烧录好，出给客户就可以了。客户可以随便刷机，升级，但不能随便购买芯片。
当然，固件完整性，固件防逆向，这些需求，可结合坑网之前的讨论的帖子，来实现。
最后一句话，攻防手段千千万，但几千年来，唯一不变的，还是人心，人性。
#34 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 15:57:03
在F133芯片上，烧写ECDSA256 64字节签名文件到EFUSE，偏移为0x00c0区域，也就是2048bit的最后面的512bit，efuse前面的bit有各种隐藏用途，需小心使用，但后面的bit就随便整了。无需担心变砖。
经验证，是可以通过efuse来存储签名文件，并能够验签通过。
1，通过write指令烧写64字节签名文件，烧写到0xc0这个偏移位置
xfel extra efuse write 0x00c0 sign.bin2，查看烧写好的efuse，发现0xc0偏移，已经储存了签名文件，与sign.bin的内容保持一致
xfel extra efuse dump
chipid:(0x0000 128-bits)
93005c00 ac004814 01425a4c 1c5318cb
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
7906c10a 019db011
ft-zone:(0x001c 128-bits)
83883119 0ef00f02 2b06111c 87180a0b
tvout:(0x002c 32-bits)
00000285
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
11223344 55667788
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
e133aa93 7aaf3227 14b10f12 06b71c6c
nv1:(0x00d0 32-bits)
ef80e46e
nv2:(0x00d4 32-bits)
e0ba33d4
reserved3:(0x00d8 96-bits)
a6fe6c3c f65c2d60 915ae6c7
oem-program-secure:(0x00e4 224-bits)
90ce9b07 94906489 3e39dce8 d06473aa 1dda2501 1f940484 36a770d8 3， 验签，将efuse里的签名读出来，用ECDSA256公钥进行验签，这里是对CPU唯一序列号的SHA256摘要进行验签。经过这样的操作，只要你没有ECDSA256私钥，你是无法生成正确的签名文件的，那么验签就无法通过。当别人想抄板或更换CPU，因序列号变了，且没有正确的签名，就无法启动运行，实现放盗版保护。
#35 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 12:50:28
扩展XFEL，支持V851/V853芯片的EFUSE读写操作
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
62c07800 cc004820 0145c519 204e1a8c
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
2291c0f9 007c9279
ft-zone:(0x001c 128-bits)
100f1109 13210de2 00278600 00691510
reserved1:(0x002c 96-bits)
00000000 00000000 00000000
write-protect:(0x0038 32-bits)
00000000
read-protect:(0x003c 32-bits)
00000000
lcjs:(0x0040 32-bits)
00000000
reserved2:(0x0044 800-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
rotpk:(0x00a8 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
reserved3:(0x00c8 448-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000 #36 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 11:32:46
山羊胡子 说：
写完会熔断吗？会不会因为写efuse不当导致芯片成砖
这个是可能的，比如你烧写了加密引导位，并且随便填了个rotpk的sha256值，那么你的芯片就永远无法启动了，没有合法的加密引导签名，谁都没辙，就变砖了。
但只要不碰到关键熔丝，还是没啥风险的，在操作之前，仔细确认EFUSE分配信息，就无伤大雅了。
efuse分配信息，其实也不是一成不变的，除了核心分配信息，基本都是随着SDK的而重新分配的，这些细节就只能去翻代码了。
有些efuse存储了全志出厂时的芯片校正信息，比如温度传感器校正参数，TVOUT校正，各种AD，DA，内部RC补偿等等，这些没有文档，只能自己去寻找蛛丝马迹了。
#37 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-12 10:38:33
现在XFEL支持了D1 / D1s / F133芯片的EFUSE读写操作
1，dump efuse
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
93005c00 ac004814 01425a4c 1c5318cb
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
7906c10a 019db011
ft-zone:(0x001c 128-bits)
83883119 0ef00f02 2b06111c 87180a0b
tvout:(0x002c 32-bits)
00000285
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
00000000 00000000
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
00000000 00000000 00000000 00000000
nv1:(0x00d0 32-bits)
00000000
nv2:(0x00d4 32-bits)
00000000
reserved3:(0x00d8 96-bits)
00000000 00000000 00000000
oem-program-secure:(0x00e4 224-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 2, write oem-program 1
$ xfel extra efuse write32 0x0038 0x11223344
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
93005c00 ac004814 01425a4c 1c5318cb
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
7906c10a 019db011
ft-zone:(0x001c 128-bits)
83883119 0ef00f02 2b06111c 87180a0b
tvout:(0x002c 32-bits)
00000285
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
11223344 00000000
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
00000000 00000000 00000000 00000000
nv1:(0x00d0 32-bits)
00000000
nv2:(0x00d4 32-bits)
00000000
reserved3:(0x00d8 96-bits)
00000000 00000000 00000000
oem-program-secure:(0x00e4 224-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 3, write oem-program 2
$ xfel extra efuse write32 0x003c 0x55667788
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
93005c00 ac004814 01425a4c 1c5318cb
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
7906c10a 019db011
ft-zone:(0x001c 128-bits)
83883119 0ef00f02 2b06111c 87180a0b
tvout:(0x002c 32-bits)
00000285
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
11223344 55667788
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
00000000 00000000 00000000 00000000
nv1:(0x00d0 32-bits)
00000000
nv2:(0x00d4 32-bits)
00000000
reserved3:(0x00d8 96-bits)
00000000 00000000 00000000
oem-program-secure:(0x00e4 224-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 4, reboot and dump efuse again
$ xfel extra efuse dump
chipid:(0x0000 128-bits)
93005c00 ac004814 01425a4c 1c5318cb
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
7906c10a 019db011
ft-zone:(0x001c 128-bits)
83883119 0ef00f02 2b06111c 87180a0b
tvout:(0x002c 32-bits)
00000285
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
11223344 55667788
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
00000000 00000000 00000000 00000000
nv1:(0x00d0 32-bits)
00000000
nv2:(0x00d4 32-bits)
00000000
reserved3:(0x00d8 96-bits)
00000000 00000000 00000000
oem-program-secure:(0x00e4 224-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 #39 Re: 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-11 22:28:40
efuse分配信息如下：
static const struct sid_section_t {
char * name;
uint32_t offset;
uint32_t size_bits;
} sids[] = {
{ "chipid", 0x0000, 128 },
{ "brom-conf-try", 0x0010, 32 },
{ "thermal-sensor", 0x0014, 64 },
{ "ft-zone", 0x001c, 128 },
{ "tvout", 0x002c, 32 },
{ "tvout-gamma", 0x0030, 64 },
{ "oem-program", 0x0038, 64 },
{ "write-protect", 0x0040, 32 },
{ "read-protect", 0x0044, 32 },
{ "reserved1", 0x0048, 64 },
{ "huk", 0x0050, 192 },
{ "reserved2", 0x0068, 64 },
{ "rotpk", 0x0070, 256 },
{ "ssk", 0x0090, 256 },
{ "rssk", 0x00b0, 128 },
{ "hdcp-hash", 0x00c0, 128 },
{ "nv1", 0x00d0, 32 },
{ "nv2", 0x00d4, 32 },
{ "reserved3", 0x00d8, 96 },
{ "oem-program-secure", 0x00e4, 224 },
};这是根据全志SDK总结而来。
#40 全志 SOC » 深入研究T113 EFUSE，现已扩展XFEL工具，并支持烧写T113熔丝位 » 2023-07-11 22:26:53
- xboot
- 回复： 30
全志的SOC，只要不是太老旧的芯片，里面都集成了2048bit的EFUSE，但此熔丝位的很多细节，并没有相关描述文档，这导致大家很难在实际项目中应用此功能，而且也缺乏灵活的烧写工具，基于此问题，我花了点时间扩展了下XFEL工具。
扩展的命令如下：
usage:
xfel extra efuse dump - Dump all of the efuse information
xfel extra efuse read32 <offset> - Read 32-bits value from efuse
xfel extra efuse write32 <offset> <value> - Write 32-bits value to efuse
xfel extra efuse write <offset> <file> - Write file to efuse执行dump指令，显示如下信息:
xfel extra efuse dump
chipid:(0x0000 128-bits)
93406000 0c004814 01426250 48671b4b
brom-conf-try:(0x0010 32-bits)
00000000
thermal-sensor:(0x0014 64-bits)
88fbc11a 01e9080f
ft-zone:(0x001c 128-bits)
898f1919 0f760f6c 3108126c 811a0a0e
tvout:(0x002c 32-bits)
0000028f
tvout-gamma:(0x0030 64-bits)
00000000 00000000
oem-program:(0x0038 64-bits)
00000000 00000000
write-protect:(0x0040 32-bits)
00000000
read-protect:(0x0044 32-bits)
00000000
reserved1:(0x0048 64-bits)
00000000 00000000
huk:(0x0050 192-bits)
00000000 00000000 00000000 00000000 00000000 00000000
reserved2:(0x0068 64-bits)
00000000 00000000
rotpk:(0x0070 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ssk:(0x0090 256-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
rssk:(0x00b0 128-bits)
00000000 00000000 00000000 00000000
hdcp-hash:(0x00c0 128-bits)
00000000 00000000 00000000 00000000
nv1:(0x00d0 32-bits)
00000000
nv2:(0x00d4 32-bits)
00000000
reserved3:(0x00d8 96-bits)
00000000 00000000 00000000
oem-program-secure:(0x00e4 224-bits)
00000000 00000000 00000000 00000000 00000000 00000000 00000000可以通过write32 或者write指令来烧写熔丝。
全志加密引导功能可以通过烧写熔丝来启用，当然你也可以烧写自己的序列号，或者mac地址之类的，当然这个efuse还可以用来做防盗版，来实现一机一固件，简要说明下，就是在efuse里烧录本机固件的签名文件，而这个签名文件又是跟cpu序列号关联，可以采用ECDSA256签名算法，签名大小为512bit，64字节，比RSA的签名要小很多，而且强度够。
#41 Re: 全志 SOC » V3LP问题请教 » 2023-07-04 19:49:45
#42 Re: 全志 SOC » f1c200s自制 win10 USB显示屏 » 2023-06-26 12:25:24
#43 Re: 全志 SOC » 抛砖引玉，全志T113 TVD模块裸机驱动 » 2023-06-11 09:40:46
#44 Re: 全志 SOC » 抛砖引玉，全志T113 TVD模块裸机驱动 » 2023-06-10 20:18:02
#45 Re: 全志 SOC » 抛砖引玉，全志T113 TVD模块裸机驱动 » 2023-06-10 20:17:15
#46 Re: 全志 SOC » 抛砖引玉，全志T113 TVD模块裸机驱动 » 2023-06-09 20:58:56
#47 全志 SOC » 抛砖引玉，全志T113 TVD模块裸机驱动 » 2023-06-08 13:04:27
- xboot
- 回复： 8
全志T113的TVD模块，测试下来，发现是这德行。估计又是哪里配置错误了。
驱动文件在这里
https://github.com/xboot/xboot/blob/master/src/arch/arm32/mach-t113s3/driver/cam-t113-tvd.c
站在微凉大侠的肩膀上，编写F1C100S平台的CVBS IN驱动, 也就是驱动完全找不到北的TVD模块。
https://whycan.com/t_6902.html
#50 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-31 19:44:09
#51 Re: 全志 SOC » mqr_t113使用xboot在SPINAND无法启动 » 2023-05-27 17:31:17
#52 Re: 全志 SOC » mqr_t113使用xboot在SPINAND无法启动 » 2023-05-27 17:29:08
#53 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-27 17:25:22
#54 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-27 12:21:38
#55 Re: 全志 SOC » mqr_t113使用xboot在SPINAND无法启动 » 2023-05-27 09:03:06
F133平台做了自动探测处理，T113平台没有实现。
enum {
BOOT_DEVICE_SPINOR,
BOOT_DEVICE_SPINAND,
BOOT_DEVICE_SDCARD,
};
static int get_boot_device(void)
{
uint8_t s = *((volatile uint8_t *)(0x00020000 + 0x28));
if(s == 0x3)
return BOOT_DEVICE_SPINOR;
else if(s == 0x4)
return BOOT_DEVICE_SPINAND;
else if(s == 0x0)
return BOOT_DEVICE_SDCARD;
return BOOT_DEVICE_SPINOR;
}#56 Re: 全志 SOC » mqr_t113使用xboot在SPINAND无法启动 » 2023-05-27 09:01:40
#57 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2023-05-26 11:37:43
想研究的，看这个代码，不贴代码的都是耍流氓。
{
// The Hotplug Flag Register is 0x070005DC.
// The Soft Entry Address Register is 0x070005E0.
// la a0, 0x02500000
// la a1, 0x23
// sb a1, 0 (a0)
// xxx: j xxx
// Test: write byte to 0x02500000 = UART0 data tegister
static const uint32_t code [] = {
0x02500537, // 37 05 50 02
0x0230059B, // 9B 05 30 02 │
0x00B50023, // 23 00 B5 00
0x0000006F, // 6F 00 00 00,
};
* (volatile uint32_t *) 0x070005DC = 0*0xFA50392Fu; // Hotplug Flag Register
* (volatile uint32_t *) 0x070005E0 = (uintptr_t) code; // Soft Entry Address Register
dcache_clean_all();
printhex(0x06000000, (void *) 0x06000000, 0x10000);
//CCU->RISC_GATING_REG
CCU->RISC_CFG_BGR_REG |= (1u << 16) | (1u << 0);
(void) CCU->RISC_CFG_BGR_REG;
PRINTF("CCU->RISC_CFG_BGR_REG=%08" PRIX32 "\n", CCU->RISC_CFG_BGR_REG);
RISC_CFG->RISC_STA_ADD0_REG = (uintptr_t) code;
RISC_CFG->RISC_STA_ADD1_REG = 0;//(uint32_t) (uintptr_t) code >> 32;
//memset(RISC_CFG, ~ 0u, sizeof * RISC_CFG);
PRINTF("CCU->RISC_GATING_REG=%08" PRIX32 ", CCU->RISC_CFG_BGR_REG=%08" PRIX32 "\n", CCU->RISC_GATING_REG, CCU->RISC_CFG_BGR_REG);
PRINTF("RISC_CFG->RISC_STA_ADD0_REG=%08" PRIX32 ", RISC_CFG->RISC_STA_ADD1_REG=%08" PRIX32 "\n", RISC_CFG->RISC_STA_ADD0_REG, RISC_CFG->RISC_STA_ADD1_REG);
//printhex32(RISC_CFG_BASE, RISC_CFG, sizeof * RISC_CFG);
local_delay_ms(3000);
//PRINTF("CCU->RISC_RST_REG=%08" PRIX32 "\n", CCU->RISC_RST_REG);
CCU->RISC_RST_REG = 0x16AA0001u;
(void) CCU->RISC_RST_REG;
//PRINTF("CCU->RISC_RST_REG=%08" PRIX32 "\n", CCU->RISC_RST_REG);
//ASSERT(CCU->RISC_RST_REG & 0x01u);
for (;;)
;
}#58 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-24 15:36:30
#59 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-24 14:33:22
#60 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-24 09:43:51
xfel-windows-v1.3.1.7z
上传一个已编译好的V1.3.1版本，windows平台。
#61 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-24 09:38:42
贴一个采用xfel直接引导xboot的完整log，可以是空片直接启动。
xfel ddr r128-s2;
xfel write 0x08200000 xboot.bin;
xfel extra exec riscv 0x08200000;[2]set pll end
[3]board init ok
[5]fake dram ok
[7]heap: 0x40a0000 size:0xe000
[9]lpsram init
[11]lspsram init aps64
[13]lspsram dqs:0x011a01a0
[18]psram chip APS64 init ok!, freq 1920000000
[22]Init psram controller ok
[24]hpsram init
[26]DRAM DQS gate is PD mode.
[29]DRAM BOOT DRIVE INFO: V2.00
[32]DRAM CLK = 800 MHZ
[34]dram_tpr11 = 0x0 , dram_tpr12 =0x0
[37]dram_tpr9 = 0x2020
[86]DRAM simple test OK.
[88]DRAM SIZE =8 MB
[100]fes1 done
█████████████████████████████████
██ ▄▄▄▄▄ █ ▀███▀ ▄█▀█ ▄█ ▄▄▄▄▄ ██
██ █ █ █ ▀▄█▄▄▀▄▀█▄▀ █ █ █ ██
██ █▄▄▄█ █▄ ▄▄▀█▄▀█ ▄█ █▄▄▄█ ██
██▄▄▄▄▄▄▄█ █ █▄▀▄█▄▀▄▀▄█▄▄▄▄▄▄▄██
███▄▄█▄█▄▄▀█ ▀ ▀ ▀ ███ ▀▄ ▄▄ ██
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██▄▀▄█▄█▄ ▄▄█▀▄▀ ▀ ███ ██ ██ ██
███ ▄▄▄▄▄▄ ▄▄▀▀▄▄█▀▀▄▀▄▀▄▀▄▀▄▀▄██
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██▄██▄█▄▄█▀▀▀▄█ ███ █ ▄▄▄ ██ ██
██ ▄▄▄▄▄ █▄ ██▀ ▀▀▄▀▄ █▄█ ▀▄▀▄██
██ █ █ █▄▀██▀█▄██ ▀▄ ▄▄ █▀ ██
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█████████████████████████████████
_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2023
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (May 24 2023 - 09:30:05) - [yuzuki][Yuzuki Based On Allwinner R128 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'fix-losc' with clk-fixed
[ 0.000810]Probe device 'rc-16m' with clk-fixed
[ 0.000820]Probe device 'rcosc-clk' with clk-fixed
[ 0.000830]Probe device 'ext-32k' with clk-fixed
[ 0.000840]Probe device 'rc-hf' with clk-fixed
[ 0.000850]Probe device 'rccal-fake-parent' with clk-fixed
[ 0.000860]Probe device 'osc26m' with clk-fixed
[ 0.000870]Probe device 'osc40m' with clk-fixed
[ 0.000880]Probe device 'osc24m' with clk-fixed
[ 0.000890]Probe device 'osc32m' with clk-fixed
[ 0.000900]Probe device 'osc24.576m' with clk-fixed
[ 0.000910]Probe device 'hosc' with clk-mux
[ 0.000920]Probe device 'hosc-div32k' with clk-fixed-factor
[ 0.000930]Probe device 'rcosc-div32k' with clk-fixed-factor
[ 0.000940]Probe device 'hosc-div2' with clk-fixed-factor
[ 0.000950]Probe device 'dpll1' with clk-r128-pll
[ 0.000960]Probe device 'dpll2' with clk-r128-pll
[ 0.000970]Probe device 'dpll3' with clk-r128-pll
[ 0.000980]Probe device 'pll-audio' with clk-r128-pll
[ 0.000990]Probe device 'rfip0-dpll' with clk-fixed-factor
[ 0.001000]Probe device 'rfip1-dpll' with clk-fixed-factor
[ 0.001010]Probe device 'pll-audio2x' with clk-fixed-factor
[ 0.001020]Probe device 'pll-audio1x' with clk-fixed-factor
[ 0.001030]Probe device 'dpll1-div4' with clk-fixed-factor
[ 0.001040]Probe device 'dpll1-div5' with clk-fixed-factor
[ 0.001050]Probe device 'dpll1-div6' with clk-fixed-factor
[ 0.001060]Probe device 'dpll1-div7' with clk-fixed-factor
[ 0.001070]Probe device 'dpll1-div8' with clk-fixed-factor
[ 0.001080]Probe device 'dpll1-div39' with clk-fixed-factor
[ 0.001090]Probe device 'dpll1-div85' with clk-fixed-factor
[ 0.001100]Probe device 'dpll3-div4' with clk-fixed-factor
[ 0.001110]Probe device 'dpll3-div5' with clk-fixed-factor
[ 0.001120]Probe device 'dpll3-div6' with clk-fixed-factor
[ 0.001130]Probe device 'dpll3-div7' with clk-fixed-factor
[ 0.001140]Probe device 'dpll3-div8' with clk-fixed-factor
[ 0.001150]Probe device 'ck1-usb' with clk-gate
[ 0.001160]Probe device 'mux-ck1-aud' with clk-mux
[ 0.001170]Probe device 'ck1-aud' with clk-gate
[ 0.001180]Probe device 'mux-ck1-dev' with clk-mux
[ 0.001190]Probe device 'ck1-dev' with clk-gate
[ 0.001200]Probe device 'mux-ck1-m33' with clk-mux
[ 0.001210]Probe device 'ck1-m33' with clk-gate
[ 0.001220]Probe device 'mux-ck3-dev' with clk-mux
[ 0.001230]Probe device 'ck3-dev' with clk-gate
[ 0.001240]Probe device 'mux-ck3-m33' with clk-mux
[ 0.001250]Probe device 'ck3-m33' with clk-gate
[ 0.001260]Probe device 'ck-dev' with clk-mux
[ 0.001270]Probe device 'device-clk' with clk-divider
[ 0.001280]Probe device 'ck-m33' with clk-mux
[ 0.001290]Probe device 'sys' with clk-divider
[ 0.001300]Probe device 'aud-rco-div' with clk-divider
[ 0.001310]Probe device 'ar200a-f' with clk-mux
[ 0.001320]Probe device 'hfclk-div' with clk-ratio
[ 0.001330]Probe device 'lfclk-div' with clk-ratio
[ 0.001340]Probe device 'ahb-div' with clk-ratio
[ 0.001350]Probe device 'apb' with clk-mux
[ 0.001360]Probe device 'ble-32m' with clk-gate
[ 0.001370]Probe device 'ble-48m' with clk-gate
[ 0.001380]Probe device 'gpio-gate' with clk-gate
[ 0.001390]Probe device 'bus-codec-dac' with clk-gate
[ 0.001400]Probe device 'rccal' with clk-gate
[ 0.001410]Probe device 'bus-codec-adc' with clk-gate
[ 0.001420]Probe device 'dmic-bus' with clk-gate
[ 0.001430]Probe device 'gpadc' with clk-gate
[ 0.001440]Probe device 'lpuart1-wkup' with clk-gate
[ 0.001450]Probe device 'lpuart0-wkup' with clk-gate
[ 0.001460]Probe device 'osc32k-en' with clk-gate
[ 0.001470]Probe device 'rc32k-en' with clk-gate
[ 0.001480]Probe device 'rc-hf-en' with clk-gate
[ 0.001490]Probe device 'rccal-32k' with clk-gate
[ 0.001500]Probe device 'rco-wup-en' with clk-gate
[ 0.001510]Probe device 'lf-sel' with clk-mux
[ 0.001520]Probe device 'sys-32k-sel' with clk-mux
[ 0.001530]Probe device 'ble-sel' with clk-mux
[ 0.001540]Probe device 'sysrtc32k' with clk-mux
[ 0.001550]Probe device 'pad' with clk-mux
[ 0.001560]Probe device 'div-pad' with clk-divider
[ 0.001570]Probe device 'pad-out' with clk-gate
[ 0.001580]Probe device 'div' with clk-mux
[ 0.001590]Probe device '32k-auto-en-switch' with clk-gate
[ 0.001600]Probe device 'bus-ehci0' with clk-gate
[ 0.001610]Probe device 'bus-ohci0' with clk-gate
[ 0.001620]Probe device 'bus-csi-jpe' with clk-gate
[ 0.001630]Probe device 'bus-ledc' with clk-gate
[ 0.001640]Probe device 'bus-otg' with clk-gate
[ 0.001650]Probe device 'bus-smcard' with clk-gate
[ 0.001660]Probe device 'bus-hspsram-ctrl' with clk-gate
[ 0.001670]Probe device 'bus-irrx' with clk-gate
[ 0.001680]Probe device 'bus-irtx' with clk-gate
[ 0.001690]Probe device 'bus-pwm' with clk-gate
[ 0.001700]Probe device 'bus-twi1' with clk-gate
[ 0.001710]Probe device 'bus-twi0' with clk-gate
[ 0.001720]Probe device 'bus-uart2' with clk-gate
[ 0.001730]Probe device 'bus-uart1' with clk-gate
[ 0.001740]Probe device 'bus-uart0' with clk-gate
[ 0.001750]Probe device 'bus-sdc0' with clk-gate
[ 0.001760]Probe device 'bus-spi1' with clk-gate
[ 0.001770]Probe device 'bus-spi0' with clk-gate
[ 0.001780]Probe device 'bus-monitor' with clk-gate
[ 0.001790]Probe device 'bus-g2d' with clk-gate
[ 0.001800]Probe device 'bus-de' with clk-gate
[ 0.001810]Probe device 'bus-display' with clk-gate
[ 0.001820]Probe device 'bus-lcd' with clk-gate
[ 0.001830]Probe device 'bus-bt-core' with clk-gate
[ 0.001840]Probe device 'bus-wlan-ctrl' with clk-gate
[ 0.001850]Probe device 'bus-trng' with clk-gate
[ 0.001860]Probe device 'bus-spc' with clk-gate
[ 0.001870]Probe device 'bus-ss' with clk-gate
[ 0.001880]Probe device 'bus-timer' with clk-gate
[ 0.001890]Probe device 'bus-spinlock' with clk-gate
[ 0.001900]Probe device 'bus-dma1' with clk-gate
[ 0.001910]Probe device 'bus-dma0' with clk-gate
[ 0.001920]Probe device 'bus-spdif' with clk-gate
[ 0.001930]Probe device 'bus-i2s' with clk-gate
[ 0.001940]Probe device 'riscv-cfg' with clk-gate
[ 0.001950]Probe device 'riscv-msgbox' with clk-gate
[ 0.001960]Probe device 'dsp-cfg' with clk-gate
[ 0.001970]Probe device 'dsp-msgbox' with clk-gate
[ 0.001980]Probe device 'cpu-msgbox' with clk-gate
[ 0.001990]Probe device 'mbus-de' with clk-gate
[ 0.002000]Probe device 'mbus-g2d' with clk-gate
[ 0.002010]Probe device 'mbus-csi' with clk-gate
[ 0.002020]Probe device 'mbus-dma1' with clk-gate
[ 0.002030]Probe device 'mbus-dma0' with clk-gate
[ 0.002040]Probe device 'mbus-usb' with clk-gate
[ 0.002050]Probe device 'mbus-ce' with clk-gate
[ 0.002060]Probe device 'mbus-dsp' with clk-gate
[ 0.002070]Probe device 'mbus-riscv' with clk-gate
[ 0.002080]Probe device 'mbus-cpu' with clk-gate
[ 0.002090]Probe device 'mux-pclk-spc' with clk-mux
[ 0.002100]Probe device 'div-pclk-spc' with clk-divider
[ 0.002110]Probe device 'pclk-spc' with clk-ratio
[ 0.002120]Probe device 'mux-spi0' with clk-mux
[ 0.002130]Probe device 'div-spi0' with clk-divider
[ 0.002140]Probe device 'ratio-spi0' with clk-ratio
[ 0.002150]Probe device 'spi0' with clk-gate
[ 0.002160]Probe device 'mux-spi1' with clk-mux
[ 0.002170]Probe device 'div-spi1' with clk-divider
[ 0.002180]Probe device 'ratio-spi1' with clk-ratio
[ 0.002190]Probe device 'spi1' with clk-gate
[ 0.002200]Probe device 'mux-sdc0' with clk-mux
[ 0.002210]Probe device 'div-sdc0' with clk-divider
[ 0.002220]Probe device 'ratio-sdc0' with clk-ratio
[ 0.002230]Probe device 'sdc0' with clk-gate
[ 0.002240]Probe device 'mux-ss' with clk-mux
[ 0.002250]Probe device 'div-ss' with clk-divider
[ 0.002260]Probe device 'ratio-ss' with clk-ratio
[ 0.002270]Probe device 'ss' with clk-gate
[ 0.002280]Probe device 'mux-csi-jpe' with clk-mux
[ 0.002290]Probe device 'div-csi-jpe' with clk-divider
[ 0.002300]Probe device 'ratio-csi-jpe' with clk-ratio
[ 0.002310]Probe device 'csi-jpe' with clk-gate
[ 0.002320]Probe device 'mux-ledc' with clk-mux
[ 0.002330]Probe device 'div-ledc' with clk-divider
[ 0.002340]Probe device 'ratio-ledc' with clk-ratio
[ 0.002350]Probe device 'ledc' with clk-gate
[ 0.002360]Probe device 'mux-irrx' with clk-mux
[ 0.002370]Probe device 'div-irrx' with clk-divider
[ 0.002380]Probe device 'ratio-irrx' with clk-ratio
[ 0.002390]Probe device 'irrx' with clk-gate
[ 0.002400]Probe device 'mux-irtx' with clk-mux
[ 0.002410]Probe device 'div-irtx' with clk-divider
[ 0.002420]Probe device 'ratio-irtx' with clk-ratio
[ 0.002430]Probe device 'irtx' with clk-gate
[ 0.002440]Probe device 'mux-systick-ref' with clk-mux
[ 0.002450]Probe device 'div-systick-ref' with clk-divider
[ 0.002460]Probe device 'ratio-systick-ref' with clk-ratio
[ 0.002470]Probe device 'systick-ref' with clk-gate
[ 0.002480]Probe device 'systick-noref' with clk-gate
[ 0.002490]Probe device 'systick-skew' with clk-gate
[ 0.002500]Probe device 'mux-csi-mclk' with clk-mux
[ 0.002510]Probe device 'div-csi-mclk' with clk-divider
[ 0.002520]Probe device 'ratio-csi-mclk' with clk-ratio
[ 0.002530]Probe device 'csi-mclk' with clk-gate
[ 0.002540]Probe device 'mux-flash-spi' with clk-mux
[ 0.002550]Probe device 'div-flash-spi' with clk-divider
[ 0.002560]Probe device 'ratio-flash-spi' with clk-ratio
[ 0.002570]Probe device 'flash-spi' with clk-gate
[ 0.002580]Probe device 'mux-g2d' with clk-mux
[ 0.002590]Probe device 'div-g2d' with clk-divider
[ 0.002600]Probe device 'ratio-g2d' with clk-ratio
[ 0.002610]Probe device 'g2d' with clk-gate
[ 0.002620]Probe device 'mux-de' with clk-mux
[ 0.002630]Probe device 'div-de' with clk-divider
[ 0.002640]Probe device 'ratio-de' with clk-ratio
[ 0.002650]Probe device 'de' with clk-gate
[ 0.002660]Probe device 'mux-lcd' with clk-mux
[ 0.002670]Probe device 'div-lcd' with clk-divider
[ 0.002680]Probe device 'ratio-lcd' with clk-ratio
[ 0.002690]Probe device 'lcd' with clk-gate
[ 0.002700]Probe device 'timer0' with clk-link
[ 0.002710]Probe device 'timer1' with clk-link
[ 0.002720]Probe device 'uart0' with clk-link
[ 0.002730]Probe device 'uart1' with clk-link
[ 0.002740]Probe device 'uart2' with clk-link
[ 0.002750]Probe device 'wdg' with clk-fixed
[ 0.002760]Probe device 'reset-r128.0' with reset-r128
[ 0.002770]Probe device 'reset-r128.1' with reset-r128
[ 0.002780]Probe device 'reset-r128.2' with reset-r128
[ 0.002790]Probe device 'reset-r128.3' with reset-r128
[ 0.002800]Probe device 'reset-r128.4' with reset-r128
[ 0.002810]Probe device 'reset-r128.5' with reset-r128
[ 0.002820]Probe device 'reset-r128.6' with reset-r128
[ 0.002830]Probe device 'irq-r128.0' with irq-r128
[ 0.002840]Probe device 'irq-r128-gpio.0' with irq-r128-gpio
[ 0.002850]Probe device 'irq-r128-gpio.1' with irq-r128-gpio
[ 0.002860]Probe device 'gpio-r128.0' with gpio-r128
[ 0.002870]Probe device 'gpio-r128.1' with gpio-r128
[ 0.002880]Probe device 'ce-r128-timer.0' with ce-r128-timer
[ 0.000089]Probe device 'cs-r128-timer.0' with cs-r128-timer
[ 0.005967]Probe device 'uart-16550.0' with uart-16550
[ 0.011228]Probe device 'uart-16550.1' with uart-16550
[ 0.016569]Probe device 'i2c-r128.0' with i2c-r128
[ 0.021506]Probe device 'i2c-r128.1' with i2c-r128
[ 0.026445]Probe device 'spi-r128.0' with spi-r128
[ 0.040882]Found spi nor flash 'SFDP' with 16.000MB
[ 0.045752]Found partition:
[ 0.048569] 0x0000000000000000 ~ 0x0000000000ffffff 16.000MB - blk-spinor.0
[ 0.055880] 0x0000000000000000 ~ 0x00000000005fffff 6.000MB - blk-spinor.0.xboot
[ 0.063687] 0x0000000000600000 ~ 0x00000000007fffff 2.000MB - blk-spinor.0.reserve
[ 0.071651] 0x0000000000800000 ~ 0x0000000000ffffff 8.000MB - blk-spinor.0.private
[ 0.079508]Probe device 'blk-spinor.0' with blk-spinor
[ 0.084811]Probe device 'wdg-r128.0' with wdg-r128
[ 0.089669]Probe device 'console-uart.0' with console-uart
[ 0.098777]mount /private with 'ram' filesystem
Press any key to stop auto boot: 0.260
xboot: /#
xboot: /#
xboot: /# #62 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 23:32:24
#63 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 23:30:37
xfel升级到V1.3.1版本，此版本已完整支持R128，楼上计划的所有功能均以实现，包括烧写SPI NOR FLASH，通过fel启动RISCV核心，启动DSP核心。
这里扩展了一个extra命令，可以启动RISCV和DSP核，后面的地址，就是核心的入口地址。
usage:
xfel extra exec riscv <address> - Boot riscv and jump to address
xfel extra exec dsp <address> - Boot dsp and jump to address现在运行xboot有两种方案：
1,直接用xfel来运行RISCV程序
xfel ddr r128-s2;
xfel write 0x08200000 xboot.bin;
xfel extra exec riscv 0x08200000;2,利用全志SDK里的m33.bin程序来引导riscv
xfel ddr r128-s2;
xfel write 0x08004000 lichee/rtos/build/r128s2_pro_m33/img/rt_system.bin;
xfel write 0x08200000 xboot.bin;
xfel exec 0x08004001;#64 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 15:08:08
#65 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 14:35:52
#66 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 12:49:58
严谨点说，就是多做3个操作，R128芯片内部spi nor flash必挂
1, 全局解锁SPI NOR FLASH
2, 将状态寄存器2，清零
3，将状态寄存器3，清零
具体是哪一个操作导致的，还是3个操作共同导致的，就不得而知了，每实验一次，一个芯片就报废了，我手上的三颗芯片，全处于搞残的状态，已经没有新芯片了，这些实验代价有点高。
除了这三个操作，xfel在操作spi nor时，还会执行两个动作
1，复位SPI NOR FLASH
2, 将状态寄存器1，清零
这两个动作是不会产生任何副作用的，在R128上已测试通过，就是最上面的三个步骤，会导致问题，而且百分百必现。
再去锁定下SPI NOR FLASH，可以救活被搞残的芯片？
#67 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 12:04:09
#68 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 09:12:28
#69 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-23 09:10:15
#70 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-22 19:27:10
已实现xfel烧写R128内部SPI NOR FLASH，但出现了一个超级超级大的坑。
只要用xfel访问过的R128芯片，哪怕仅仅是探测下spi nor flash，就会导致全志的固件无法正常运行，而且这个时候想用Phoenixsuit工具去刷机也不给刷了，提示找不到spi nor flash，但用xfel是可以正常读写spi nor flash的，这坑坑。。。。
换句话说，xfel能将R128搞残，而且是永久性的，这。。。。
全志固件启动的提示：
[2]BOOT0 commit : 7de04b7c
[5]set pll end
[6]board init ok
[8]boot reason: SUNXI_BOOT_REASON_COLD_BOOT
[26]heap: 0x40a0000 size:0xe000
[29]lspsram init aps64
[31]lspsram dqs:0x01190190
[36]psram chip APS64 init ok!, freq 1920000000
[40]Init psram controller ok
[43]hpsram init
[44]DRAM DQS gate is PD mode.
[47]DRAM BOOT DRIVE INFO: V2.00
[50]DRAM CLK = 800 MHZ
[52]dram_tpr11 = 0x0 , dram_tpr12 =0x0
[56]dram_tpr9 = 0x2121
[86]DRAM simple test OK.
[88]DRAM SIZE =8 MB
[90]boot package base:0xc600000
[93]prcm: 0x1
[94]init pins for sip nor
[96]nor read id ret:0x0, id[0]:0x0
[100]spinor init fail
[102]load gpt fail
[103]init gpt fail
[115]go to usb efex!手上仅有的2片R128都被搞残了。再贴个xfel烧写spi nor 的log吧，读写spi nor完全正常，校验也可以通过。
xfel spinor
Found spi nor flash 'SFDP' with 16777216 bytes
xfel spinor read 0 16777216 dump4.bin
100% [================================================] 16.000 MB, 383.050 KB/s
xfel spinor write 0 dump.bin
100% [================================================] 16.000 MB, 193.715 KB/s#71 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-22 17:23:30
针对R128，现已实现了中断驱动，GPIO驱动，TIMER驱动，SPI驱动，I2C驱动，时钟等驱动，打印log如下：
[0]fes begin commit:7de04b7c
[2]set pll end
[3]board init ok
[5]fake dram ok
[7]heap: 0x40a0000 size:0xe000
[9]lpsram init
[11]lspsram init aps64
[13]lspsram dqs:0x011c01c0
[18]psram chip APS64 init ok!, freq 1920000000
[22]Init psram controller ok
[24]hpsram init
[26]DRAM DQS gate is PD mode.
[29]DRAM BOOT DRIVE INFO: V2.00
[32]DRAM CLK = 800 MHZ
[34]dram_tpr11 = 0x0 , dram_tpr12 =0x0
[37]dram_tpr9 = 0x2424
[86]DRAM simple test OK.
[88]DRAM SIZE =8 MB
[100]fes1 done
Warning: clk ck1-m33 enable_count is 2, parent is dpll1, parent rate is 1920000000, should not be changed from 480000000 to 384000000, please recheck whether the operation is correct
Warning: clk ck1-dev enable_count is 2, parent is dpll1, parent rate is 1920000000, should not be changed from 1920000000 to 384000000, please recheck whether the operation is correct
M33 CPU Clock Freq: 192 MHz
*******************************************
** Welcome to R128 FreeRTOS V1.5.0 **
** Copyright (C) 2019-2022 AllwinnerTech **
** **
** starting armv8m FreeRTOS V0.7 **
*******************************************
Date:May 10 2023, Time:14:01:58
flash not ready, skip mount
---boot dsp(start_addr: 0x0c000660)---
---boot
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_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2023
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (May 22 2023 - 17:17:57) - [yuzuki][Yuzuki Based On Allwinner R128 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'fix-losc' with clk-fixed
[ 0.000810]Probe device 'rc-16m' with clk-fixed
[ 0.000820]Probe device 'rcosc-clk' with clk-fixed
[ 0.000830]Probe device 'ext-32k' with clk-fixed
[ 0.000840]Probe device 'rc-hf' with clk-fixed
[ 0.000850]Probe device 'rccal-fake-parent' with clk-fixed
[ 0.000860]Probe device 'osc26m' with clk-fixed
[ 0.000870]Probe device 'osc40m' with clk-fixed
[ 0.000880]Probe device 'osc24m' with clk-fixed
[ 0.000890]Probe device 'osc32m' with clk-fixed
[ 0.000900]Probe device 'osc24.576m' with clk-fixed
[ 0.000910]Probe device 'hosc' with clk-mux
[ 0.000920]Probe device 'hosc-div32k' with clk-fixed-factor
[ 0.000930]Probe device 'rcosc-div32k' with clk-fixed-factor
[ 0.000940]Probe device 'hosc-div2' with clk-fixed-factor
[ 0.000950]Probe device 'dpll1' with clk-r128-pll
[ 0.000960]Probe device 'dpll2' with clk-r128-pll
[ 0.000970]Probe device 'dpll3' with clk-r128-pll
[ 0.000980]Probe device 'pll-audio' with clk-r128-pll
[ 0.000990]Probe device 'rfip0-dpll' with clk-fixed-factor
[ 0.001000]Probe device 'rfip1-dpll' with clk-fixed-factor
[ 0.001010]Probe device 'pll-audio2x' with clk-fixed-factor
[ 0.001020]Probe device 'pll-audio1x' with clk-fixed-factor
[ 0.001030]Probe device 'dpll1-div4' with clk-fixed-factor
[ 0.001040]Probe device 'dpll1-div5' with clk-fixed-factor
[ 0.001050]Probe device 'dpll1-div6' with clk-fixed-factor
[ 0.001060]Probe device 'dpll1-div7' with clk-fixed-factor
[ 0.001070]Probe device 'dpll1-div8' with clk-fixed-factor
[ 0.001080]Probe device 'dpll1-div39' with clk-fixed-factor
[ 0.001090]Probe device 'dpll1-div85' with clk-fixed-factor
[ 0.001100]Probe device 'dpll3-div4' with clk-fixed-factor
[ 0.001110]Probe device 'dpll3-div5' with clk-fixed-factor
[ 0.001120]Probe device 'dpll3-div6' with clk-fixed-factor
[ 0.001130]Probe device 'dpll3-div7' with clk-fixed-factor
[ 0.001140]Probe device 'dpll3-div8' with clk-fixed-factor
[ 0.001150]Probe device 'ck1-usb' with clk-gate
[ 0.001160]Probe device 'mux-ck1-aud' with clk-mux
[ 0.001170]Probe device 'ck1-aud' with clk-gate
[ 0.001180]Probe device 'mux-ck1-dev' with clk-mux
[ 0.001190]Probe device 'ck1-dev' with clk-gate
[ 0.001200]Probe device 'mux-ck1-m33' with clk-mux
[ 0.001210]Probe device 'ck1-m33' with clk-gate
[ 0.001220]Probe device 'mux-ck3-dev' with clk-mux
[ 0.001230]Probe device 'ck3-dev' with clk-gate
[ 0.001240]Probe device 'mux-ck3-m33' with clk-mux
[ 0.001250]Probe device 'ck3-m33' with clk-gate
[ 0.001260]Probe device 'ck-dev' with clk-mux
[ 0.001270]Probe device 'device-clk' with clk-divider
[ 0.001280]Probe device 'ck-m33' with clk-mux
[ 0.001290]Probe device 'sys' with clk-divider
[ 0.001300]Probe device 'aud-rco-div' with clk-divider
[ 0.001310]Probe device 'ar200a-f' with clk-mux
[ 0.001320]Probe device 'hfclk-div' with clk-ratio
[ 0.001330]Probe device 'lfclk-div' with clk-ratio
[ 0.001340]Probe device 'ahb-div' with clk-ratio
[ 0.001350]Probe device 'apb' with clk-mux
[ 0.001360]Probe device 'ble-32m' with clk-gate
[ 0.001370]Probe device 'ble-48m' with clk-gate
[ 0.001380]Probe device 'gpio-gate' with clk-gate
[ 0.001390]Probe device 'bus-codec-dac' with clk-gate
[ 0.001400]Probe device 'rccal' with clk-gate
[ 0.001410]Probe device 'bus-codec-adc' with clk-gate
[ 0.001420]Probe device 'dmic-bus' with clk-gate
[ 0.001430]Probe device 'gpadc' with clk-gate
[ 0.001440]Probe device 'lpuart1-wkup' with clk-gate
[ 0.001450]Probe device 'lpuart0-wkup' with clk-gate
[ 0.001460]Probe device 'osc32k-en' with clk-gate
[ 0.001470]Probe device 'rc32k-en' with clk-gate
[ 0.001480]Probe device 'rc-hf-en' with clk-gate
[ 0.001490]Probe device 'rccal-32k' with clk-gate
[ 0.001500]Probe device 'rco-wup-en' with clk-gate
[ 0.001510]Probe device 'lf-sel' with clk-mux
[ 0.001520]Probe device 'sys-32k-sel' with clk-mux
[ 0.001530]Probe device 'ble-sel' with clk-mux
[ 0.001540]Probe device 'sysrtc32k' with clk-mux
[ 0.001550]Probe device 'pad' with clk-mux
[ 0.001560]Probe device 'div-pad' with clk-divider
[ 0.001570]Probe device 'pad-out' with clk-gate
[ 0.001580]Probe device 'div' with clk-mux
[ 0.001590]Probe device '32k-auto-en-switch' with clk-gate
[ 0.001600]Probe device 'bus-ehci0' with clk-gate
[ 0.001610]Probe device 'bus-ohci0' with clk-gate
[ 0.001620]Probe device 'bus-csi-jpe' with clk-gate
[ 0.001630]Probe device 'bus-ledc' with clk-gate
[ 0.001640]Probe device 'bus-otg' with clk-gate
[ 0.001650]Probe device 'bus-smcard' with clk-gate
[ 0.001660]Probe device 'bus-hspsram-ctrl' with clk-gate
[ 0.001670]Probe device 'bus-irrx' with clk-gate
[ 0.001680]Probe device 'bus-irtx' with clk-gate
[ 0.001690]Probe device 'bus-pwm' with clk-gate
[ 0.001700]Probe device 'bus-twi1' with clk-gate
[ 0.001710]Probe device 'bus-twi0' with clk-gate
[ 0.001720]Probe device 'bus-uart2' with clk-gate
[ 0.001730]Probe device 'bus-uart1' with clk-gate
[ 0.001740]Probe device 'bus-uart0' with clk-gate
[ 0.001750]Probe device 'bus-sdc0' with clk-gate
[ 0.001760]Probe device 'bus-spi1' with clk-gate
[ 0.001770]Probe device 'bus-spi0' with clk-gate
[ 0.001780]Probe device 'bus-monitor' with clk-gate
[ 0.001790]Probe device 'bus-g2d' with clk-gate
[ 0.001800]Probe device 'bus-de' with clk-gate
[ 0.001810]Probe device 'bus-display' with clk-gate
[ 0.001820]Probe device 'bus-lcd' with clk-gate
[ 0.001830]Probe device 'bus-bt-core' with clk-gate
[ 0.001840]Probe device 'bus-wlan-ctrl' with clk-gate
[ 0.001850]Probe device 'bus-trng' with clk-gate
[ 0.001860]Probe device 'bus-spc' with clk-gate
[ 0.001870]Probe device 'bus-ss' with clk-gate
[ 0.001880]Probe device 'bus-timer' with clk-gate
[ 0.001890]Probe device 'bus-spinlock' with clk-gate
[ 0.001900]Probe device 'bus-dma1' with clk-gate
[ 0.001910]Probe device 'bus-dma0' with clk-gate
[ 0.001920]Probe device 'bus-spdif' with clk-gate
[ 0.001930]Probe device 'bus-i2s' with clk-gate
[ 0.001940]Probe device 'riscv-cfg' with clk-gate
[ 0.001950]Probe device 'riscv-msgbox' with clk-gate
[ 0.001960]Probe device 'dsp-cfg' with clk-gate
[ 0.001970]Probe device 'dsp-msgbox' with clk-gate
[ 0.001980]Probe device 'cpu-msgbox' with clk-gate
[ 0.001990]Probe device 'mbus-de' with clk-gate
[ 0.002000]Probe device 'mbus-g2d' with clk-gate
[ 0.002010]Probe device 'mbus-csi' with clk-gate
[ 0.002020]Probe device 'mbus-dma1' with clk-gate
[ 0.002030]Probe device 'mbus-dma0' with clk-gate
[ 0.002040]Probe device 'mbus-usb' with clk-gate
[ 0.002050]Probe device 'mbus-ce' with clk-gate
[ 0.002060]Probe device 'mbus-dsp' with clk-gate
[ 0.002070]Probe device 'mbus-riscv' with clk-gate
[ 0.002080]Probe device 'mbus-cpu' with clk-gate
[ 0.002090]Probe device 'mux-pclk-spc' with clk-mux
[ 0.002100]Probe device 'div-pclk-spc' with clk-divider
[ 0.002110]Probe device 'pclk-spc' with clk-ratio
[ 0.002120]Probe device 'mux-spi0' with clk-mux
[ 0.002130]Probe device 'div-spi0' with clk-divider
[ 0.002140]Probe device 'ratio-spi0' with clk-ratio
[ 0.002150]Probe device 'spi0' with clk-gate
[ 0.002160]Probe device 'mux-spi1' with clk-mux
[ 0.002170]Probe device 'div-spi1' with clk-divider
[ 0.002180]Probe device 'ratio-spi1' with clk-ratio
[ 0.002190]Probe device 'spi1' with clk-gate
[ 0.002200]Probe device 'mux-sdc0' with clk-mux
[ 0.002210]Probe device 'div-sdc0' with clk-divider
[ 0.002220]Probe device 'ratio-sdc0' with clk-ratio
[ 0.002230]Probe device 'sdc0' with clk-gate
[ 0.002240]Probe device 'mux-ss' with clk-mux
[ 0.002250]Probe device 'div-ss' with clk-divider
[ 0.002260]Probe device 'ratio-ss' with clk-ratio
[ 0.002270]Probe device 'ss' with clk-gate
[ 0.002280]Probe device 'mux-csi-jpe' with clk-mux
[ 0.002290]Probe device 'div-csi-jpe' with clk-divider
[ 0.002300]Probe device 'ratio-csi-jpe' with clk-ratio
[ 0.002310]Probe device 'csi-jpe' with clk-gate
[ 0.002320]Probe device 'mux-ledc' with clk-mux
[ 0.002330]Probe device 'div-ledc' with clk-divider
[ 0.002340]Probe device 'ratio-ledc' with clk-ratio
[ 0.002350]Probe device 'ledc' with clk-gate
[ 0.002360]Probe device 'mux-irrx' with clk-mux
[ 0.002370]Probe device 'div-irrx' with clk-divider
[ 0.002380]Probe device 'ratio-irrx' with clk-ratio
[ 0.002390]Probe device 'irrx' with clk-gate
[ 0.002400]Probe device 'mux-irtx' with clk-mux
[ 0.002410]Probe device 'div-irtx' with clk-divider
[ 0.002420]Probe device 'ratio-irtx' with clk-ratio
[ 0.002430]Probe device 'irtx' with clk-gate
[ 0.002440]Probe device 'mux-systick-ref' with clk-mux
[ 0.002450]Probe device 'div-systick-ref' with clk-divider
[ 0.002460]Probe device 'ratio-systick-ref' with clk-ratio
[ 0.002470]Probe device 'systick-ref' with clk-gate
[ 0.002480]Probe device 'systick-noref' with clk-gate
[ 0.002490]Probe device 'systick-skew' with clk-gate
[ 0.002500]Probe device 'mux-csi-mclk' with clk-mux
[ 0.002510]Probe device 'div-csi-mclk' with clk-divider
[ 0.002520]Probe device 'ratio-csi-mclk' with clk-ratio
[ 0.002530]Probe device 'csi-mclk' with clk-gate
[ 0.002540]Probe device 'mux-flash-spi' with clk-mux
[ 0.002550]Probe device 'div-flash-spi' with clk-divider
[ 0.002560]Probe device 'ratio-flash-spi' with clk-ratio
[ 0.002570]Probe device 'flash-spi' with clk-gate
[ 0.002580]Probe device 'mux-g2d' with clk-mux
[ 0.002590]Probe device 'div-g2d' with clk-divider
[ 0.002600]Probe device 'ratio-g2d' with clk-ratio
[ 0.002610]Probe device 'g2d' with clk-gate
[ 0.002620]Probe device 'mux-de' with clk-mux
[ 0.002630]Probe device 'div-de' with clk-divider
[ 0.002640]Probe device 'ratio-de' with clk-ratio
[ 0.002650]Probe device 'de' with clk-gate
[ 0.002660]Probe device 'mux-lcd' with clk-mux
[ 0.002670]Probe device 'div-lcd' with clk-divider
[ 0.002680]Probe device 'ratio-lcd' with clk-ratio
[ 0.002690]Probe device 'lcd' with clk-gate
[ 0.002700]Probe device 'timer0' with clk-link
[ 0.002710]Probe device 'timer1' with clk-link
[ 0.002720]Probe device 'wdg' with clk-fixed
[ 0.002730]Probe device 'uart0' with clk-fixed
[ 0.002740]Probe device 'uart1' with clk-fixed
[ 0.002750]Probe device 'uart2' with clk-fixed
[ 0.002760]Probe device 'reset-r128.0' with reset-r128
[ 0.002770]Probe device 'reset-r128.1' with reset-r128
[ 0.002780]Probe device 'reset-r128.2' with reset-r128
[ 0.002790]Probe device 'reset-r128.3' with reset-r128
[ 0.002800]Probe device 'reset-r128.4' with reset-r128
[ 0.002810]Probe device 'reset-r128.5' with reset-r128
[ 0.002820]Probe device 'reset-r128.6' with reset-r128
[ 0.002830]Probe device 'irq-r128.0' with irq-r128
[ 0.002840]Probe device 'irq-r128-gpio.0' with irq-r128-gpio
[ 0.002850]Probe device 'irq-r128-gpio.1' with irq-r128-gpio
[ 0.002860]Probe device 'gpio-r128.0' with gpio-r128
[ 0.002870]Probe device 'gpio-r128.1' with gpio-r128
[ 0.002880]Probe device 'ce-r128-timer.0' with ce-r128-timer
[ 0.000046]Probe device 'cs-r128-timer.0' with cs-r128-timer
[ 0.005696]Probe device 'uart-16550.0' with uart-16550
[ 0.010808]Probe device 'uart-16550.1' with uart-16550
[ 0.015957]Probe device 'i2c-r128.0' with i2c-r128
[ 0.020727]Probe device 'i2c-r128.1' with i2c-r128
[ 0.025489]Probe device 'spi-r128.0' with spi-r128
[ 0.039591]Found spi nor flash 'SFDP' with 16.000MB
[ 0.044374]Found partition:
[ 0.047151] 0x0000000000000000 ~ 0x0000000000ffffff 16.000MB - blk-spinor.0
[ 0.054304] 0x0000000000000000 ~ 0x00000000005fffff 6.000MB - blk-spinor.0.xboot
[ 0.061925] 0x0000000000600000 ~ 0x00000000007fffff 2.000MB - blk-spinor.0.reserve
[ 0.069725] 0x0000000000800000 ~ 0x0000000000ffffff 8.000MB - blk-spinor.0.private
[ 0.077480]Probe device 'blk-spinor.0' with blk-spinor
[ 0.082645]Probe device 'wdg-r128.0' with wdg-r128
[ 0.087402]Probe device 'console-uart.0' with console-uart
[ 0.094821]mount /private with 'ram' filesystem
Press any key to stop auto boot: 0.120
xboot: /# #72 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-22 16:57:07
补充一个手册上没有的信息，R128内置SPI NOR FLASH，此Flash接在GPIOB8，GPIOB9，GPIOB10，GPIOB11，GPIOB12，GPIOB13 Pin脚上，功能3为SPI0 pinmux
"spi-r128:0@0x40009000": {
"clock-name": "spi0",
"reset": 0,
"sclk-gpio": 45,
"sclk-gpio-config": 3,
"mosi-gpio": 42,
"mosi-gpio-config": 3,
"miso-gpio": 43,
"miso-gpio-config": 3,
"cs-gpio": 44,
"cs-gpio-config": 3
},#73 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-17 23:39:22
通过xfel工具，R128现在已可以运行xboot，LOG记录如下，下面就可以愉快的编写R128驱动了。
█████████████████████████████████
██ ▄▄▄▄▄ █ ▀███▀ ▄█▀█ ▄█ ▄▄▄▄▄ ██
██ █ █ █ ▀▄█▄▄▀▄▀█▄▀ █ █ █ ██
██ █▄▄▄█ █▄ ▄▄▀█▄▀█ ▄█ █▄▄▄█ ██
██▄▄▄▄▄▄▄█ █ █▄▀▄█▄▀▄▀▄█▄▄▄▄▄▄▄██
███▄▄█▄█▄▄▀█ ▀ ▀ ▀ ███ ▀▄ ▄▄ ██
██▀ ▄▄ ▄▄█▄▄ ▀ ▄▄▀▄▀▄█ ▀▄▀▄▀▄██
██▄▀▄█▄█▄ ▄▄█▀▄▀ ▀ ███ ██ ██ ██
███ ▄▄▄▄▄▄ ▄▄▀▀▄▄█▀▀▄▀▄▀▄▀▄▀▄▀▄██
██▄▄█▀▄▄▄ ▄ ▀▀▄▄▄▀▄ ███ █ ██ ██
██▄▀▄▄█ ▄▀▀▄▀▄ ▄▀▀▄▀▄▀▄▀▄▀▄▀▄▀▄██
██▄██▄█▄▄█▀▀▀▄█ ███ █ ▄▄▄ ██ ██
██ ▄▄▄▄▄ █▄ ██▀ ▀▀▄▀▄ █▄█ ▀▄▀▄██
██ █ █ █▄▀██▀█▄██ ▀▄ ▄▄ █▀ ██
██ █▄▄▄█ █ ▀▀▄▄██▀▄▀▄█ █▀▄▀▄▀▄██
██▄▄▄▄▄▄▄███▄▄▄▄▄██▄▄█▄█▄█▄▄█▄▄██
█████████████████████████████████
_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2023
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (May 17 2023 - 23:25:28) - [yuzuki][Yuzuki Based On Allwinner R128 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'osc48m' with clk-fixed
[ 0.000810]Probe device 'osc32k' with clk-fixed
[ 0.000820]Probe device 'bus-uart0' with clk-fixed
[ 0.000830]Probe device 'wdg' with clk-fixed
[ 0.000840]Probe device 'uart-16550.0' with uart-16550
[ 0.000850]Probe device 'wdg-r128.0' with wdg-r128
[ 0.000860]Probe device 'console-uart.0' with console-uart
[ 0.000970]mount /private with 'ram' filesystem
Press any key to stop auto boot: 0.330
xboot: /# #74 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-16 19:34:26
#75 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-16 19:25:35
用xfel指令加载sdk默认镜像试验。
#初始化DDR
xfel ddr r128-s2;
#加载M33核程序到0x08004000
xfel write 0x08004000 lichee/rtos/build/r128s2_pro_m33/img/rt_system.bin;
#加载C906程序到0x08200000，注意此程序是SPI NOR XIP的，光加载到RAM中是无法完整运行的，这里仅做引导C906试验。
xfel write 0x08200000 lichee/rtos/build/r128s2_pro_c906/img/rt_system.bin;
#运行M33核心程序，M33核心运行时，会自动的运行C906以及DSP程序。所以，将C906和DSP程序准备好，可以随着M33核一起启动。
xfel exec 0x08004001现象如下：
[0]fes begin commit:7de04b7c
[2]set pll end
[3]board init ok
[5]fake dram ok
[7]heap: 0x40a0000 size:0xe000
[9]lpsram init
[11]lspsram init aps64
[13]lspsram dqs:0x011a01a0
[18]psram chip APS64 init ok!, freq 1920000000
[22]Init psram controller ok
[24]hpsram init
[26]DRAM DQS gate is PD mode.
[29]DRAM BOOT DRIVE INFO: V2.00
[32]DRAM CLK = 800 MHZ
[34]dram_tpr11 = 0x0 , dram_tpr12 =0x0
[37]dram_tpr9 = 0x2020
[86]DRAM simple test OK.
[88]DRAM SIZE =8 MB
[100]fes1 done
[0]fes begin commit:7de04b7c
[2]set pll end
[3]board init ok
[5]fake dram ok
[7]heap: 0x40a0000 size:0xe000
[9]lpsram init
[11]lspsram init aps64
[13]lspsram dqs:0x01060060
[18]psram chip APS64 init ok!, freq 1920000000
[22]Init psram controller ok
[24]hpsram init
[26]DRAM DQS gate is PD mode.
[29]DRAM BOOT DRIVE INFO: V2.00
[32]DRAM CLK = 800 MHZ
[34]dram_tpr11 = 0x0 , dram_tpr12 =0x0
[37]dram_tpr9 = 0x2020
[86]DRAM simple test OK.
[88]DRAM SIZE =8 MB
[100]fes1 done
Warning: clk ck1-m33 enable_count is 2, parent is dpll1, parent rate is 1920000000, should not be changed from 480000000 to 384000000, please recheck whether the operation is correct
Warning: clk ck1-dev enable_count is 2, parent is dpll1, parent rate is 1920000000, should not be changed from 1920000000 to 384000000, please recheck whether the operation is correct
] not support in sys_config
M33 CPU Clock Freq: 192 MHz
*******************************************
** Welcome to R128 FreeRTOS V1.5.0 **
** Copyright (C) 2019-2022 AllwinnerTech **
** **
** starting armv8m FreeRTOS V0.7 **
*******************************************
Date:May 10 2023, Time:14:01:58
[E(m33)] get dram_para dram_no_lpsram failed, skip LSPSRAM standby
[E(m33)] get dram_para dram_clk failed, skip HSPSRAM standby
flash not ready, skip mount
---boot dsp(start_addr: 0x0c000660)---
---boot c906---
C906 CPU Freq: 480 MHz
*******************************************
** Welcome to R128 FreeRTOS V1.5.0 **
** Copyright (C) 2019-2022 AllwinnerTech **
** **
** starting riscv FreeRTOS V0.7 **
*******************************************
Date:May 10 2023, Time:14:09:34
devfs: mount devfs to /dev ok
use default flash chip mJedec 0x0
[FD I]: Enter 32 Bit Address Mode
[FD I]: mode: 0x20, freq: 96000000Hz, drv: 0
[FD I]: jedec: 0x0, suspend_support: 1
no flash, skip init nor
=====================================================================================================
EXC_LOAD_ACCESS
=====================================================================================================
gprs:
x0:0x0000000000000000 ra:0x0000000008255c2e sp:0x000000000830dfe0 gp:0x00000000082c5420
tp:0x0000000000000000 t0:0x0000000000000030 t1:0x0000000000000000 t2:0x0000000000000009
s0:0x00000000082fca78 s1:0x00000000082b3df8 a0:0xffffffffffffffff a1:0x0000000000000000
a2:0x0000000000000000 a3:0x000000000830e070 a4:0x0000000000000000 a5:0x0000000000000000
a6:0x0000000000000002 a7:0x000000004004707c s2:0x00000000082b3df8 s3:0x0000000008336b70
s5:0xa5a5a5a5a5a5a5a5 s5:0xa5a5a5a5a5a5a5a5 s6:0xa5a5a5a5a5a5a5a5 s7:0xa5a5a5a5a5a5a5a5
s8:0xa5a5a5a5a5a5a5a5 s9:0xa5a5a5a5a5a5a5a5 s10:0xa5a5a5a5a5a5a5a5 s11:0xa5a5a5a5a5a5a5a5
t3:0x0000000000000000 t4:0x0000000000000000 t5:0x0000000000000020 t6:0x0000000000000000
other:
mepc :0x0000000008255c40
mcause :0x0000000000000005
mtval :0x0000000000000000
mstatus :0x0000000a00003980
mscratch:0x0000000000000000
-------backtrace-----------
backtrace : 0X08255C40
backtrace : 0X0825EFB6
backtrace : 0X0825EE76
---------------------------#76 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-16 19:13:52
#77 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-14 22:35:51
再接再厉，利用读写payload操作M33核的看门狗，实现reset功能。
static int chip_reset(struct xfel_ctx_t * ctx)
{
payload_write32(ctx, 0x40020400 + 0x14, (0x16aa << 16) | (0x1 << 0));
payload_write32(ctx, 0x40020400 + 0x18, (0x16aa << 16) | (1 << 0));
payload_write32(ctx, 0x40020400 + 0x10, (0xa57 << 1) | (1 << 0));
return 1;
}#78 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-14 21:40:20
有了上面的研究，我们就可以编写一个纯粹的针对cortex-m33核的read32以及write32的payload了，为何要自己编写这两个payload，而不采用fel协议自带的读写R32，W32实现，是因为fel协议本身在读写内存时，是基于字节访问的，而某些控制器的寄存器是不支持字节访问，只支持word字访问，因为有这种限制，那fel自带的读写函数，是不适合操作芯片寄存器的。
read32.S
.syntax unified
.global _start
_start:
dsb.w sy
isb.w sy
ldr.w r0, _iciallu
mov.w r1, #0x0
str.w r1, [r0]
dsb.w sy
isb.w sy
b.w reset
.align 2
_iciallu:
.word 0xe000ef50
reset:
ldr.w r0, _adr
adr.w r1, _val
ldr.w r2, [r0]
str.w r2, [r1]
bx lr
.align 2
_adr:
.word 0x11223344
_val:
.word 0x55667788write32.S
.syntax unified
.global _start
_start:
dsb.w sy
isb.w sy
ldr.w r0, _iciallu
mov.w r1, #0x0
str.w r1, [r0]
dsb.w sy
isb.w sy
b.w reset
.align 2
_iciallu:
.word 0xe000ef50
reset:
ldr.w r0, _adr
ldr.w r1, _val
str.w r1, [r0]
bx lr
.align 2
_adr:
.word 0x11223344
_val:
.word 0x55667788封装读写payload
static uint32_t payload_read32(struct xfel_ctx_t * ctx, uint32_t addr)
{
static const uint8_t payload[] = {
0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xdf, 0xf8, 0x14, 0x00,
0x4f, 0xf0, 0x00, 0x01, 0xc0, 0xf8, 0x00, 0x10, 0xbf, 0xf3, 0x4f, 0x8f,
0xbf, 0xf3, 0x6f, 0x8f, 0x00, 0xf0, 0x02, 0xb8, 0x50, 0xef, 0x00, 0xe0,
0xdf, 0xf8, 0x10, 0x00, 0x0f, 0xf2, 0x10, 0x01, 0xd0, 0xf8, 0x00, 0x20,
0xc1, 0xf8, 0x00, 0x20, 0x70, 0x47, 0x00, 0xbf
};
uint32_t adr = cpu_to_le32(addr);
uint32_t val;
fel_write(ctx, ctx->version.scratchpad, (void *)payload, sizeof(payload));
fel_write(ctx, ctx->version.scratchpad + sizeof(payload), (void *)&adr, sizeof(adr));
fel_exec(ctx, ctx->version.scratchpad);
fel_read(ctx, ctx->version.scratchpad + sizeof(payload) + sizeof(adr), (void *)&val, sizeof(val));
return le32_to_cpu(val);
}
static void payload_write32(struct xfel_ctx_t * ctx, uint32_t addr, uint32_t val)
{
static const uint8_t payload[] = {
0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xdf, 0xf8, 0x14, 0x00,
0x4f, 0xf0, 0x00, 0x01, 0xc0, 0xf8, 0x00, 0x10, 0xbf, 0xf3, 0x4f, 0x8f,
0xbf, 0xf3, 0x6f, 0x8f, 0x00, 0xf0, 0x02, 0xb8, 0x50, 0xef, 0x00, 0xe0,
0xdf, 0xf8, 0x0c, 0x00, 0xdf, 0xf8, 0x0c, 0x10, 0xc0, 0xf8, 0x00, 0x10,
0x70, 0x47, 0x00, 0xbf
};
uint32_t params[2] = {
cpu_to_le32(addr),
cpu_to_le32(val),
};
fel_write(ctx, ctx->version.scratchpad, (void *)payload, sizeof(payload));
fel_write(ctx, ctx->version.scratchpad + sizeof(payload), (void *)params, sizeof(params));
fel_exec(ctx, ctx->version.scratchpad);
}利用读写payload实现使能jtag的pinmux功能
static int chip_jtag(struct xfel_ctx_t * ctx)
{
uint32_t addr;
uint32_t val;
/* Config PA16 and PA17 to SWD-TMS and SWD-TCK */
addr = 0x4004a400 + 0x08;
val = payload_read32(ctx, addr);
val &= ~(0xf << ((0 & 0xf) << 2));
val |= ((0x8 & 0xf) << ((0 & 0xf) << 2));
payload_write32(ctx, addr, val);
val = payload_read32(ctx, addr);
val &= ~(0xf << ((1 & 0xf) << 2));
val |= ((0x8 & 0xf) << ((1 & 0xf) << 2));
payload_write32(ctx, addr, val);
return 1;
}#79 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-14 21:16:11
关于exec指令如何可靠稳定的执行自己写的测试程序的问题，经过深入研究，定位是M33核指令缓存相关问题。
我们编写的payload，如果上传到某个地址，然后在这个地址执行后，这部分代码就被缓存了，如果这个时候，我们在更新另外一个payload，通过write指令写入内存，SRAM或者LSPSRAM或者HSPSRAM中，然后新payload的执行地址如果跟原先的地址相同的话，这个时候就会出现不可预见的现象，执行的指令有可能是原先被缓存过payload。
既然分析到问题点了，解决手段，有两种方案：
一种是粗暴的关闭指令缓存，这种方案影响后续的执行效率，就不考虑了
另一种方案就是现在采用的方案，每一个payload保证开始的指令都是一致的，而且这些一致的指令里，首先做的动作就是清理指令，这样就能保证每个payload都能有效执行了，避免不可以预见的现象。
payload头指令
.syntax unified
.global _start
_start:
dsb.w sy
isb.w sy
ldr.w r0, _iciallu
mov.w r1, #0x0
str.w r1, [r0]
dsb.w sy
isb.w sy
b.w reset
.align 2
_iciallu:
.word 0xe000ef50
reset:
push.w { lr }
/* ... */
pop.w { lr }
bx lr经过以上处理后，就可以解决之前感觉怪意的问题，同时也验证了，payload放在LSPSRAM或在HSPRSRAM空间，都是可以正常执行的，不是必须是内部的SRAM。这就为后续的全RAM中执行程序，打下基础。什么M33程序，C906程序，DSP程序，理论上都是可以执行的。
#80 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-13 20:25:43
#81 Re: 全志 SOC » 全志T113-S3 G2D加速裸机驱动 » 2023-05-13 10:28:56
#82 Re: 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-13 10:19:11
虽然算是搞了exec指令，但如何可靠稳定的执行自己写的测试程序，现在测试下来，感觉还是有点怪意，初步分析，可能M33核心里面指令或者数据cache了，还没玩过M33，对这个核里面的细节不清楚，先不枉下结论了，但这个问题，是有必要去深究的。
R128里面有PSRAM，有nor flash。初步计划，针对R128芯片，后续xfel需要开发以下功能：
1，读写SRAM，（已完成）
2，执行运行在M33核的payload指令（已完成）
3，读取R128的SID（已完成）
4，初始化M33核心的jtag接口，此接口跟调试串口复用（已开发，未测试）
5，实现reset操作
6，初始化LSPRAM以及HSPSRAM
7, 支持启动C906核心，加载并执行通过write命令写入到RAM中的C906程序
8, 支持启动DSP核心，加载并执行通过write命令写入到RAM中的DSP程序 (优先级低，估计没手段验证)
9，支持烧写NOR FLASH
如果完美实现了这些功能，通过xfel来开发R128，估计要爽到飞起，开发验证都是足够便捷的。
#83 全志 SOC » 全志R128来袭，有想入坑的吗?我先来点初步研究成果 » 2023-05-13 10:01:58
- xboot
- 回复： 53
全志R128里面有三个核心，一个M33,一个C906，还有一个DSP。
M33核主要负责引导，启动，安全，休眠，唤醒，低功耗，WIFI/BT等相关功能。
C906主要负责运行各种APP，控制各种外设驱动
DSP主要负责音频算法处理
现在手上拿到了一个有异常的板子，无法正常烧录，刷机，但fel模式是可以运行的。所以先尝试开发xfel对R128芯片的支持。
适配xfel，前面比较顺利，可以顺利读写SRAM，但exec命令被卡壳了，无法运行ARM payload，经过不断尝试，终于可以执行exec指令了，原来M33核的payload每一条指令不一定都是32位，有可能存在16位的，M33核无法编译出全32位指令。
#84 Re: 全志 SOC » 全志T113-S3 G2D加速裸机驱动 » 2023-05-10 19:12:48
#85 全志 SOC » 全志T113-S3 G2D加速裸机驱动 » 2023-05-08 09:30:25
- xboot
- 回复： 9
花了点时间研究了下全志的2D加速模块，这个2D加速，其实就是DE2模块，现在测试了矩形填充，以及bitblit操作。
驱动代码在这里。
https://gitee.com/xboot/xboot/blob/master/src/arch/arm32/mach-t113s3/driver/g2d-t113.c
#86 Re: 全志 SOC » 全志D1芯片之终极探索 » 2023-04-27 20:09:52
#87 Re: 全志 SOC » 小麻雀 Nezha-MQ 迎来双核A7版本128M内存（基于T113-s3） » 2023-04-19 19:50:24
时隔一年，一个偶然的发现，搞定了T113的中断， _vector 需要32字节对齐，补丁如下：
diff --git a/src/arch/arm32/mach-t113s3/start.S b/src/arch/arm32/mach-t113s3/start.S
index 39d83e78a..4415adea1 100644
--- a/src/arch/arm32/mach-t113s3/start.S
+++ b/src/arch/arm32/mach-t113s3/start.S
@@ -86,7 +86,7 @@
.global _start
_start:
/* Boot head information for BROM */
- .long 0xea000016
+ .long 0xea00000e
.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
.long 0x12345678 /* checksum */
.long __spl_size /* spl size */
@@ -97,7 +97,9 @@ _start:
.long 0x0 /* eGON version */
.byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */
.byte 0x34, 0x2e, 0x30, 0x00
+ .long 0, 0, 0, 0 /* reserve */
+ .align 5
_vector:
b reset
ldr pc, _undefined_instruction#89 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-09-21 20:10:44
补充一个准确的说明文件，上面的偏移有些错误
# Rockchip RV1106
## Compile source code and generate the target files at the output directory
```shell
make clean
make CROSS_COMPILE=/path/to/arm-none-linux-gnueabihf- PLATFORM=arm32-rv1106
```
## Enter maskrom mode and using xrock for burning spi nor flash (offset = 0x00010000, sector = 128)
```shell
sudo xrock maskrom rv1106_ddr_924MHz_v1.09.bin rv1106_usbplug_v1.06.bin --rc4-off;
sleep 3;
sudo xrock flash write 128 xbootpak.bin;
sudo xrock reset;
```
## Enter maskrom mode and using xrock for burning spi nand flash (offset = 0x00040000, sector = 512)
```shell
sudo xrock maskrom rv1106_ddr_924MHz_v1.09.bin rv1106_usbplug_v1.06.bin --rc4-off;
sleep 3;
sudo xrock flash write 512 xbootpak.bin;
sudo xrock reset;
```
## Enter maskrom mode and using xrock for burning emmc (offset = 0x00008000, sector = 64)
```shell
sudo xrock maskrom rv1106_ddr_924MHz_v1.09.bin rv1106_usbplug_v1.06.bin --rc4-off;
sleep 3;
sudo xrock flash write 64 xbootpak.bin;
sudo xrock reset;
```
## Download xrock source code
```shell
git clone https://github.com/xboot/xrock.git
```
## Make and install xrock
```shell
make
sudo make install
```#92 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-19 10:54:48
现在已添加了不少裸机驱动，启动log如下：
DDR Version V1.09 20220630
f947
F
DDRConf2
DDR3, BW=16 Col=10 Bk=8 CS0 Row=13 CS=1 Die BW=16 Size=128MB
924MHz
DDR bin out
█████████████████████████
██ ▄▄▄▄▄ ██▄▀▀▀█ ▄▄▄▄▄ ██
██ █ █ █ ▀▄█ █ █ █ ██
██ █▄▄▄█ ██▄ ██ █▄▄▄█ ██
██▄▄▄▄▄▄▄█▄█ █ █▄▄▄▄▄▄▄██
████▀▄ ▀▄▄█ ▀█▄▀█▀▀ █▀██
███▀▄▀ ▀▄ ▄█▀▀▄▀█ ▀█ ▄███
███▄█▄█▄▄▄▀▀ ▄ ▀ ▄▄ ▀ ██
██ ▄▄▄▄▄ █▄ ▄█▄▀▄████▄▄██
██ █ █ █ ▀█▄█▄▄█ ▄▀█▄██
██ █▄▄▄█ ██▀ █ ▄▄▄▄█▄ ██
██▄▄▄▄▄▄▄███▄██▄▄▄▄▄▄▄███
█████████████████████████
_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2022
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (Aug 19 2022 - 10:43:57) - [x1106][X1106 Based On RV1106 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'xin24m' with clk-fixed
[ 0.000810]Probe device 'xin32k' with clk-fixed
[ 0.000820]Probe device 'clk_rtc_32k' with clk-link
[ 0.000830]Probe device 'apll' with clk-rv1106-pll
[ 0.000840]Probe device 'cpll' with clk-rv1106-pll
[ 0.000850]Probe device 'dpll' with clk-rv1106-pll
[ 0.000860]Probe device 'gpll' with clk-rv1106-pll
[ 0.000870]Probe device 'clk_pvtm_core' with clk-rv1106-gate
[ 0.000880]Probe device 'clk_core_mcu_rtc' with clk-rv1106-gate
[ 0.000890]Probe device 'clk_timer_root' with clk-rv1106-gate
[ 0.000900]Probe device 'hclk_cpu' with clk-rv1106-comp
[ 0.000910]Probe device 'clk_core_mcu' with clk-rv1106-comp
[ 0.000920]Probe device 'clk_50m_src' with clk-rv1106-comp
[ 0.000930]Probe device 'clk_100m_src' with clk-rv1106-comp
[ 0.000940]Probe device 'clk_150m_src' with clk-rv1106-comp
[ 0.000950]Probe device 'clk_200m_src' with clk-rv1106-comp
[ 0.000960]Probe device 'clk_250m_src' with clk-rv1106-comp
[ 0.000970]Probe device 'clk_300m_src' with clk-rv1106-comp
[ 0.000980]Probe device 'clk_339m_src' with clk-rv1106-comp
[ 0.000990]Probe device 'clk_400m_src' with clk-rv1106-comp
[ 0.001000]Probe device 'clk_450m_src' with clk-rv1106-comp
[ 0.001010]Probe device 'clk_500m_src' with clk-rv1106-comp
[ 0.001020]Probe device 'pclk_top_root' with clk-rv1106-comp
[ 0.001030]Probe device 'pclk_peri_root' with clk-rv1106-comp
[ 0.001040]Probe device 'clk_100m_pmu' with clk-rv1106-divider
[ 0.001050]Probe device 'pclk_pmu_root' with clk-rv1106-comp
[ 0.001060]Probe device 'pclk_vi_rtc_root' with clk-rv1106-comp
[ 0.001070]Probe device 'pclk_vi_rtc_phy' with clk-rv1106-gate
[ 0.001080]Probe device 'pclk_vi_rtc_test' with clk-rv1106-gate
[ 0.001090]Probe device 'pclk_i2c0' with clk-rv1106-gate
[ 0.001100]Probe device 'clk_i2c0' with clk-rv1106-comp
[ 0.001110]Probe device 'pclk_i2c1' with clk-rv1106-gate
[ 0.001120]Probe device 'clk_i2c1' with clk-rv1106-comp
[ 0.001130]Probe device 'pclk_i2c2' with clk-rv1106-gate
[ 0.001140]Probe device 'clk_i2c2' with clk-rv1106-comp
[ 0.001150]Probe device 'pclk_i2c3' with clk-rv1106-gate
[ 0.001160]Probe device 'clk_i2c3' with clk-rv1106-comp
[ 0.001170]Probe device 'pclk_i2c4' with clk-rv1106-gate
[ 0.001180]Probe device 'clk_i2c4' with clk-rv1106-comp
[ 0.001190]Probe device 'pclk_timer' with clk-rv1106-gate
[ 0.001200]Probe device 'clk_timer0' with clk-rv1106-gate
[ 0.001210]Probe device 'clk_timer1' with clk-rv1106-gate
[ 0.001220]Probe device 'clk_timer2' with clk-rv1106-gate
[ 0.001230]Probe device 'clk_timer3' with clk-rv1106-gate
[ 0.001240]Probe device 'clk_timer4' with clk-rv1106-gate
[ 0.001250]Probe device 'clk_timer5' with clk-rv1106-gate
[ 0.001260]Probe device 'pclk_stimer' with clk-rv1106-gate
[ 0.001270]Probe device 'clk_stimer0' with clk-rv1106-gate
[ 0.001280]Probe device 'clk_stimer1' with clk-rv1106-gate
[ 0.001290]Probe device 'pclk_saradc' with clk-rv1106-gate
[ 0.001300]Probe device 'clk_saradc' with clk-rv1106-comp
[ 0.001310]Probe device 'clk_uart0_src' with clk-rv1106-comp
[ 0.001320]Probe device 'gate-clk_uart0_src' with clk-rv1106-gate
[ 0.001330]Probe device 'clk_uart0_frac' with clk-rv1106-factor
[ 0.001340]Probe device 'clk_uart0' with clk-rv1106-mux
[ 0.001350]Probe device 'link-uart0' with clk-link
[ 0.001360]Probe device 'link-uart1' with clk-link
[ 0.001370]Probe device 'link-uart2' with clk-link
[ 0.001380]Probe device 'link-uart3' with clk-link
[ 0.001390]Probe device 'link-uart4' with clk-link
[ 0.001400]Probe device 'link-uart5' with clk-link
[ 0.001410]Probe device 'link-wdt' with clk-link
[ 0.001420]Probe device 'reset-rv1106.0' with reset-rv1106
[ 0.001430]Probe device 'reset-rv1106.1' with reset-rv1106
[ 0.001440]Probe device 'reset-rv1106.2' with reset-rv1106
[ 0.001450]Probe device 'reset-rv1106.3' with reset-rv1106
[ 0.001460]Probe device 'reset-rv1106.4' with reset-rv1106
[ 0.001470]Probe device 'reset-rv1106.5' with reset-rv1106
[ 0.001480]Probe device 'reset-rv1106.6' with reset-rv1106
[ 0.001490]Probe device 'reset-rv1106.7' with reset-rv1106
[ 0.001500]Probe device 'reset-rv1106.8' with reset-rv1106
[ 0.001510]Probe device 'reset-rv1106.9' with reset-rv1106
[ 0.001520]Probe device 'reset-rv1106.10' with reset-rv1106
[ 0.001530]Probe device 'reset-rv1106.11' with reset-rv1106
[ 0.001540]Probe device 'reset-rv1106.12' with reset-rv1106
[ 0.001550]Probe device 'reset-rv1106.13' with reset-rv1106
[ 0.001560]Probe device 'reset-rv1106.14' with reset-rv1106
[ 0.001570]Probe device 'reset-rv1106.15' with reset-rv1106
[ 0.001580]Probe device 'reset-rv1106.16' with reset-rv1106
[ 0.001590]Probe device 'reset-rv1106.17' with reset-rv1106
[ 0.001600]Probe device 'reset-rv1106.18' with reset-rv1106
[ 0.001610]Probe device 'reset-rv1106.19' with reset-rv1106
[ 0.001620]Probe device 'reset-rv1106.20' with reset-rv1106
[ 0.001630]Probe device 'reset-rv1106.21' with reset-rv1106
[ 0.001640]Probe device 'reset-rv1106.22' with reset-rv1106
[ 0.001650]Probe device 'reset-rv1106.23' with reset-rv1106
[ 0.001660]Probe device 'reset-rv1106.24' with reset-rv1106
[ 0.001670]Probe device 'reset-rv1106.25' with reset-rv1106
[ 0.001680]Probe device 'reset-rv1106.26' with reset-rv1106
[ 0.001690]Probe device 'irq-gic400.0' with irq-gic400
[ 0.001700]Probe device 'irq-rv1106-gpio.0' with irq-rv1106-gpio
[ 0.001710]Probe device 'irq-rv1106-gpio.1' with irq-rv1106-gpio
[ 0.001720]Probe device 'irq-rv1106-gpio.2' with irq-rv1106-gpio
[ 0.001730]Probe device 'irq-rv1106-gpio.3' with irq-rv1106-gpio
[ 0.001740]Probe device 'irq-rv1106-gpio.4' with irq-rv1106-gpio
[ 0.001750]Probe device 'gpio-rv1106.0' with gpio-rv1106
[ 0.001760]Probe device 'gpio-rv1106.1' with gpio-rv1106
[ 0.001770]Probe device 'gpio-rv1106.2' with gpio-rv1106
[ 0.001780]Probe device 'gpio-rv1106.3' with gpio-rv1106
[ 0.001790]Probe device 'gpio-rv1106.4' with gpio-rv1106
[ 0.001840]Probe device 'adc-rv1106.0' with adc-rv1106
[ 0.001850]Probe device 'ce-armv7-timer.0' with ce-armv7-timer
[ 0.000026]Probe device 'cs-armv7-timer.0' with cs-armv7-timer
[ 0.005833]Probe device 'uart-8250.0' with uarn & SS&S%"٥:ѵr:ѡѵj & SSS%"٥:ѵr:ѡѵj & SS0
[ 0.024936]Probe device 'uart-8250.5' with uart-8250
[ 0.029878]Probe device 'i2c-rv1106.0' with i2c-rv1106
[ 0.034987]Probe device 'i2c-rv1106.1' with i2c-rv1106
[ 0.040098]Probe device 'i2c-rv1106.2' with i2c-rv1106
[ 0.045215]Probe device 'i2c-rv1106.3' with i2c-rv1106
[ 0.050331]Probe device 'i2c-rv1106.4' with i2c-rv1106
[ 0.055455]Probe device 'rtc-rv1106.0' with rtc-rv1106
[ 0.060545]Probe device 'wdg-rv1106.0' with wdg-rv1106
[ 0.065660]Probe device 'key-adc.0' with key-adc
[ 0.070257]Probe device 'led-gpio.0' with led-gpio
[ 0.075014]Probe device 'led-gpio.1' with led-gpio
[ 0.079784]Probe device 'led-gpio.2' with led-gpio
[ 0.084554]Probe device 'ledtrigger-heartbeat.0' with ledtrigger-heartbeat
[ 0.091395]Probe device 'ledtrigger-heartbeat.1' with ledtrigger-heartbeat
[ 0.098242]Probe device 'ledtrigger-heartbeat.2' with ledtrigger-heartbeat
[ 0.105088]Probe device 'console-uart.0' with console-uart
[ 0.111138]mount /private with 'ram' filesystem
xboot: /#
xboot: /#
xboot: /#
xboot: /#
xboot: /# #93 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-19 10:48:17
实现RV1106的RTC驱动
/*
* driver/rtc-rv1106.c
*
* Copyright(c) 2007-2022 Jianjun Jiang <8192542@qq.com>
* Official site: http://xboot.org
* Mobile phone: +86-18665388956
* QQ: 8192542
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#include <xboot.h>
#include <clk/clk.h>
#include <rtc/rtc.h>
enum {
RTC_SET_SECONDS = 0x00,
RTC_SET_MINUTES = 0x04,
RTC_SET_HOURS = 0x08,
RTC_SET_DAYS = 0x0c,
RTC_SET_MONTHS = 0x10,
RTC_SET_YEARL = 0x14,
RTC_SET_YEARH = 0x18,
RTC_SET_WEEKS = 0x1c,
RTC_ALARM_SECONDS = 0x20,
RTC_ALARM_MINUTES = 0x24,
RTC_ALARM_HOURS = 0x28,
RTC_ALARM_DAYS = 0x2c,
RTC_ALARM_MONTHS = 0x30,
RTC_ALARM_YEARL = 0x34,
RTC_ALARM_YEARH = 0x38,
RTC_CTRL = 0x3C,
RTC_STATUS0 = 0x40,
RTC_STATUS1 = 0x44,
RTC_INT0_EN = 0x48,
RTC_INT1_EN = 0x4c,
RTC_MSEC_CTRL = 0x50,
RTC_MSEC_CNT = 0x54,
RTC_COMP_H = 0x58,
RTC_COMP_D = 0x5c,
RTC_COMP_M = 0x60,
RTC_ANALOG_CTRL = 0x64,
RTC_ANALOG_TEST = 0x68,
RTC_LDO_CTRL = 0x6c,
RTC_XO_TRIM0 = 0x70,
RTC_XO_TRIM1 = 0x74,
RTC_VPTAT_TRIM = 0x78,
RTC_ANALOG_EN = 0x7c,
RTC_CLK32K_TEST = 0x80,
RTC_TEST_ST = 0x84,
RTC_TEST_LEN = 0x88,
RTC_CNT_0 = 0x8c,
RTC_CNT_1 = 0x90,
RTC_CNT_2 = 0x94,
RTC_CNT_3 = 0x98,
};
struct rtc_rv1106_pdata_t {
virtual_addr_t virt;
char * clk;
};
static void rtc_update_bits(virtual_addr_t virt, u32_t offset, u32_t mask, u32_t set)
{
u32_t val;
val = read32(virt + offset);
write32(virt + offset, (val & ~mask) | set | 0xc4522900);
}
static bool_t rtc_rv1106_settime(struct rtc_t * rtc, struct rtc_time_t * time)
{
struct rtc_rv1106_pdata_t * pdat = (struct rtc_rv1106_pdata_t *)rtc->priv;
u32_t rtc_data[8];
u32_t status;
int yearh, yearl;
int i;
rtc_data[0] = bin2bcd(time->second) | 0xc4522900;
rtc_data[1] = bin2bcd(time->minute) | 0xc4522900;
rtc_data[2] = bin2bcd(time->hour) | 0xc4522900;
rtc_data[3] = bin2bcd(time->day) | 0xc4522900;
rtc_data[4] = bin2bcd(time->month) | 0xc4522900;
if(time->year > 199)
{
yearh = (time->year - 100) / 100;
yearl = time->year - 100 - yearh * 100;
}
else
{
yearh = 0;
yearl = time->year - 100 - yearh * 100;
}
rtc_data[5] = bin2bcd(yearl) | 0xc4522900;
rtc_data[6] = bin2bcd(yearh) | 0xc4522900;
rtc_data[7] = bin2bcd(time->week) | 0xc4522900;
rtc_update_bits(pdat->virt, RTC_CTRL, (1 << 0), 0);
do {
status = read32(pdat->virt + RTC_STATUS1);
udelay(1);
} while(status & (1 << 0));
for(i = 0; i < 8; i++)
write32(pdat->virt + RTC_SET_SECONDS + (i << 2), rtc_data[i]);
rtc_update_bits(pdat->virt, RTC_CTRL, (1 << 7) | (1 << 0), (1 << 7) | (1 << 0));
do {
status = read32(pdat->virt + RTC_STATUS1);
udelay(1);
} while(!(status & (1 << 0)));
return TRUE;
}
static bool_t rtc_rv1106_gettime(struct rtc_t * rtc, struct rtc_time_t * time)
{
struct rtc_rv1106_pdata_t * pdat = (struct rtc_rv1106_pdata_t *)rtc->priv;
u32_t rtc_data[8];
int i;
for(i = 0; i < 8; i++)
rtc_data[i] = read32(pdat->virt + RTC_SET_SECONDS + (i << 2));
for(i = 0; i < 8; i++)
rtc_data[i] = read32(pdat->virt + RTC_SET_SECONDS + (i << 2));
for(i = 0; i < 8; i++)
rtc_data[i] = read32(pdat->virt + RTC_SET_SECONDS + (i << 2));
time->second = bcd2bin(rtc_data[0] & 0x7f);
time->minute = bcd2bin(rtc_data[1] & 0x7f);
time->hour = bcd2bin(rtc_data[2] & 0x3f);
time->day = bcd2bin(rtc_data[3] & 0x3f);
time->month = bcd2bin(rtc_data[4] & 0x1f);
time->year = (bcd2bin(rtc_data[6] & 0xff)) * 100 + (bcd2bin(rtc_data[5] & 0xff)) + 100;
time->week = bcd2bin(rtc_data[7] & 0x07);
return TRUE;
}
static struct device_t * rtc_rv1106_probe(struct driver_t * drv, struct dtnode_t * n)
{
struct rtc_rv1106_pdata_t * pdat;
struct rtc_t * rtc;
struct device_t * dev;
virtual_addr_t virt = phys_to_virt(dt_read_address(n));
char * clk = dt_read_string(n, "clock-name", NULL);
if(!search_clk(clk))
return NULL;
pdat = malloc(sizeof(struct rtc_rv1106_pdata_t));
if(!pdat)
return NULL;
rtc = malloc(sizeof(struct rtc_t));
if(!rtc)
{
free(pdat);
return NULL;
}
pdat->virt = virt;
pdat->clk = strdup(clk);
rtc->name = alloc_device_name(dt_read_name(n), -1);
rtc->settime = rtc_rv1106_settime;
rtc->gettime = rtc_rv1106_gettime;
rtc->priv = pdat;
clk_enable(pdat->clk);
write32(phys_to_virt(0xff000000) + 0x50000, ((1 << 6) << 16) | (1 << 6));
rtc_update_bits(pdat->virt, RTC_VPTAT_TRIM, (1 << 4), (4 << 1));
rtc_update_bits(pdat->virt, RTC_ANALOG_EN, (1 << 1), 0x00);
rtc_update_bits(pdat->virt, RTC_LDO_CTRL, (1 << 0), (1 << 0));
rtc_update_bits(pdat->virt, RTC_ANALOG_EN, (1 << 5), (1 << 5));
rtc_update_bits(pdat->virt, RTC_CTRL, (1 << 0) | (1 << 7), (1 << 0) | (1 << 7));
if(!(dev = register_rtc(rtc, drv)))
{
clk_disable(pdat->clk);
free(pdat->clk);
free_device_name(rtc->name);
free(rtc->priv);
free(rtc);
return NULL;
}
return dev;
}
static void rtc_rv1106_remove(struct device_t * dev)
{
struct rtc_t * rtc = (struct rtc_t *)dev->priv;
struct rtc_rv1106_pdata_t * pdat = (struct rtc_rv1106_pdata_t *)rtc->priv;
if(rtc)
{
unregister_rtc(rtc);
clk_disable(pdat->clk);
free(pdat->clk);
free_device_name(rtc->name);
free(rtc->priv);
free(rtc);
}
}
static void rtc_rv1106_suspend(struct device_t * dev)
{
}
static void rtc_rv1106_resume(struct device_t * dev)
{
}
static struct driver_t rtc_rv1106 = {
.name = "rtc-rv1106",
.probe = rtc_rv1106_probe,
.remove = rtc_rv1106_remove,
.suspend = rtc_rv1106_suspend,
.resume = rtc_rv1106_resume,
};
static __init void rtc_rv1106_driver_init(void)
{
register_driver(&rtc_rv1106);
}
static __exit void rtc_rv1106_driver_exit(void)
{
unregister_driver(&rtc_rv1106);
}
driver_initcall(rtc_rv1106_driver_init);
driver_exitcall(rtc_rv1106_driver_exit);#94 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 19:09:11
基于ADC驱动，添加ADC按键驱动，添加如下设备树即可。
"key-adc@0": {
"adc-name": "adc-rv1106.0",
"adc-channel": 0,
"poll-interval-ms": 100,
"keys": [
{ "min-voltage": 0, "max-voltage": 100000, "key-code": 11 }
]
},xboot: /# event
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]
[key-adc.0]: [KeyDown] [11]
[key-adc.0]: [KeyUp] [11]#95 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 19:01:21
编写SARADC驱动，测试通过，其寄存器跟RK3588一致。
https://github.com/xboot/xboot/blob/master/src/arch/arm32/mach-rv1106/driver/adc-rv1106.c
#97 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 11:59:29
RV1106内部自带的6个timer不可见，其还带了两个加密模式的stimer，严重怀疑当前CPU工作在加密模式，导致其不可见，当然加密模式的stimer，现在不知道其基地址，所以也无从确认起。
关于搜寻timer基地址，本来是想通过 TIMER_REVISION_6CH = 0x11970006 或 TIMER_REVISION_2CH = 0x11970002 这两个关键信息，写了个程序来遍历的，但访问某些地址空间，触发访问异常，无法继续搜寻，所以，这个思路就没有继续了。
理论上是可以对异常进行处理后，再继续搜寻的。这个问题先放弃了，采用CORTEX-A7内部自带的，也更通用点，实现功能就行，不纠结了。
#98 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 11:44:26
关于timer的运行模式，看linux内核，有些平台4个中断全部一起注册，额，这是增强适应性吧。
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};PPI 中断号从16开始，对应就是上面的26，27，29，30，四个中断号
#99 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 11:38:23
已实现timer的中断支持，还算利用cortex-a7的timer了，核心代码如下：
#define armv7_read_cntpctl() ({ u32_t val; __asm__ __volatile__("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); val; })
#define armv7_write_cntpctl(val) __asm__ __volatile__("mcr p15, 0, %0, c14, c2, 1\nisb sy\n" : : "r" (val));
static inline void armv7_timer_start(void)
{
u32_t ctrl = armv7_read_cntpctl();
if(!(ctrl & (1 << 0)))
{
ctrl |= (1 << 0);
armv7_write_cntpctl(ctrl);
}
}
static inline void armv7_timer_stop(void)
{
u32_t ctrl = armv7_read_cntpctl();
if((ctrl & (1 << 0)))
{
ctrl &= ~(1 << 0);
armv7_write_cntpctl(ctrl);
}
}
static inline void armv7_timer_interrupt_enable(void)
{
u32_t ctrl = armv7_read_cntpctl();
if(ctrl & (1 << 1))
{
ctrl &= ~(1 << 1);
armv7_write_cntpctl(ctrl);
}
}
static inline void armv7_timer_interrupt_disable(void)
{
u32_t ctrl = armv7_read_cntpctl();
if(!(ctrl & (1 << 1)))
{
ctrl |= (1 << 1);
armv7_write_cntpctl(ctrl);
}
}
static inline u64_t armv7_timer_frequecy(void)
{
u32_t v;
__asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (v));
return (v != 0) ? (u64_t)v : 1000000;
}
static inline u64_t armv7_timer_read(void)
{
u32_t l, h;
__asm__ __volatile__("mrrc p15, 0, %0, %1, c14" : "=r" (l), "=r" (h));
return ((u64_t)h << 32) | l;
}
static inline void armv7_timer_compare(uint64_t interval)
{
u64_t last = armv7_timer_read() + interval;
__asm__ __volatile__("mcrr p15, 2, %Q0, %R0, c14" : : "r" (last));
}PPI里面timer中断有4个
#define RV1106_IRQ_HYPERVISOR_TIMER (26)
#define RV1106_IRQ_VIRTUAL_TIMER (27)
#define RV1106_IRQ_SECURE_PHYSICAL_TIMER (29)
#define RV1106_IRQ_NONSECURE_PHYSICAL_TIMER (30)现在需要申请29号中断才可以触发，仅申请30号中断，无法触发，从这一点来看，现在代码运行在加密模式？
引导过程大概如下：
BOOTROM -> DDR.BIN -> XBOOT
BOOTROM 和 DDR.BIN，前在运行在加密模式的可能性比较低，后者很有可能。现在还没有对当前CPU运行模式摸个底。
#100 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 09:23:27
#101 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 09:18:08
#102 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-18 09:14:48
继续RV1106的裸奔，在编写看门狗驱动，发现时间到了后，并不能复位芯片，有一个机关，必须在启动时执行如下代码
/*
* Release the watchdog
*/
write32(0xff000000 + 0x0004, 0x2000200);
write32(0xff3b0000 + 0x0c10, 0x400040);现在没TRM手册，也搞不清是啥意思，先能用就行，顺便来个sys_cpu_init函数吧，start.S里调用下，免得后面还有一堆未知的依赖。
void sys_cpu_init(void)
{
/*
* Set all devices to Non-secure
*/
write32(0xff070000 + 0x0020, 0xffff0000);
write32(0xff070000 + 0x0024, 0xffff0000);
write32(0xff070000 + 0x0028, 0xffff0000);
write32(0xff070000 + 0x002c, 0xffff0000);
write32(0xff070000 + 0x0030, 0xffff0000);
write32(0xff070000 + 0x00bc, 0x000f0000);
write32(0xff076000 + 0x0020, 0xffff0000);
write32(0xff076000 + 0x0024, 0xffff0000);
write32(0xff076000 + 0x0028, 0xffff0000);
write32(0xff076000 + 0x002c, 0xffff0000);
write32(0xff076000 + 0x0030, 0xffff0000);
write32(0xff076000 + 0x0040, 0x00030002);
write32(0xff080000, 0x20000000);
/*
* Set the emmc and fspi to access secure area
*/
write32(0xff900000 + 0x4c, 0x00000000);
write32(0xff910000 + 0x44, 0xff00ffff);
/*
* Set fspi clk 6mA
*/
write32(0xff568000 + 0x0030, 0x0f000700);
/*
* Set the USB2 PHY in suspend mode and turn off the
* USB2 PHY FS/LS differential receiver to save power
*/
write32(0xff000000 + 0x0050, 0x01ff01d1);
write32(0xff3e0000 + 0x0100, 0x00000000);
/*
* Release the watchdog
*/
write32(0xff000000 + 0x0004, 0x2000200);
write32(0xff3b0000 + 0x0c10, 0x400040);
/*
* When venc/npu use pvtpll, reboot will fail, because
* pvtpll is reset before venc/npu reset, so venc/npu
* is not completely reset, system will block when access
* NoC in SPL.
*/
write32(0xff3b0000 + 0x1008, 0xffff0018);
write32(0xff3b0000 + 0x1000, 0x00030003);
write32(0xff3b0000 + 0x1038, 0xffff0018);
write32(0xff3b0000 + 0x1030, 0x00030003);
sdelay(20);
/*
* Limits npu max transport packets to 4 for route to scheduler,
* give much more chance for other controllers to access memory.
*/
write32(0xff140080 + 0x0008, 0x4);
/*
* Improve VENC QOS PRIORITY
*/
write32(0xff150000 + 0x0008, 0x303);
}#103 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-12 16:37:33
#104 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-11 18:42:07
#105 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-11 18:33:24
#106 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-11 18:18:58
#107 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-11 18:10:12
RV1103 / RV1106 裸奔已支持SPI NOR FLASH以及SPI NAND FLASH引导
SPI NOR FLASH烧录指令 (offset = 0x00020000, sector = 256)
sudo xrock maskrom rv1106_ddr_924MHz_v1.09.bin rv1106_usbplug_v1.03.bin --rc4-off;
sleep 3;
sudo xrock flash write 256 xbootpak.bin;
sudo xrock reset;SPI NAND FLASH烧录指令 (offset = 0x00040000, sector = 512)
sudo xrock maskrom rv1106_ddr_924MHz_v1.09.bin rv1106_usbplug_v1.03.bin --rc4-off;
sleep 3;
sudo xrock flash write 512 xbootpak.bin;
sudo xrock reset;#108 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-10 15:56:21
#109 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-09 20:01:28
#110 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-09 17:28:00
先DUMP整个时种树，以便裸奔时参考。
# cat clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
xin24m 18 18 0 24000000 0 0 50000
pclk_vi_rtc_root 2 2 0 24000000 0 0 50000
pclk_vi_rtc_phy 1 1 0 24000000 0 0 50000
pclk_vi_rtc_test 1 1 0 24000000 0 0 50000
clk_tsadc_tsen 1 1 0 12000000 0 0 50000
clk_tsadc 1 1 0 1000000 0 0 50000
clk_user_otpc_s 0 0 0 12000000 0 0 50000
clk_sbpi_otpc_s 0 0 0 24000000 0 0 50000
clk_pmc_otp 0 0 0 24000000 0 0 50000
clk_user_otpc_ns 0 0 0 12000000 0 0 50000
clk_sbpi_otpc_ns 0 0 0 24000000 0 0 50000
clk_otpc_arb 0 0 0 24000000 0 0 50000
clk_macphy 1 1 0 24000000 0 0 50000
dbclk_gpio2 0 0 0 24000000 0 0 50000
clk_sdmmc_detn_flt 0 0 0 24000000 0 0 50000
cclk_src_sdmmc 1 1 0 800000 0 0 50000
sdmmc_sample 0 0 0 400000 0 0 50000
sdmmc_drv 0 0 0 400000 0 90 50000
dbclk_gpio3 0 0 0 24000000 0 0 50000
dbclk_gpio1 0 0 0 24000000 0 0 50000
clk_uart_detn_flt 0 0 0 24000000 0 0 50000
tclk_pmu_wdt 0 0 0 24000000 0 0 50000
clk_refout 0 0 0 24000000 0 0 50000
clk_pvtm_pmu 0 0 0 24000000 0 0 50000
clk_pmu_mcu_rtc 0 0 0 24000000 0 0 50000
dbclk_pmu_gpio0 0 0 0 24000000 0 0 50000
clk_pmu 1 1 0 24000000 0 0 50000
clk_ddr_fail_safe 0 0 0 24000000 0 0 50000
clk_rtc32k_frac 0 0 0 32768 0 0 50000
clk_rtc_32k 0 0 0 32768 0 0 50000
tclk_wdt_s 0 0 0 24000000 0 0 50000
tclk_wdt_ns 0 0 0 24000000 0 0 50000
clk_ref_usbphy 2 2 0 24000000 0 0 50000
clk_usbphy_480m 1 1 0 480000000 0 0 50000
clk_ref_usbotg 1 1 0 24000000 0 0 50000
clk_saradc 1 1 0 3000000 0 0 50000
clk_capture_pwm2_peri 0 0 0 24000000 0 0 50000
clk_capture_pwm1_peri 0 0 0 24000000 0 0 50000
clk_timer_root 2 2 0 24000000 0 0 50000
clk_timer5 1 1 0 24000000 0 0 50000
clk_timer4 0 0 0 24000000 0 0 50000
clk_timer3 0 0 0 24000000 0 0 50000
clk_timer2 0 0 0 24000000 0 0 50000
clk_timer1 0 0 0 24000000 0 0 50000
clk_timer0 0 0 0 24000000 0 0 50000
clk_stimer1 0 0 0 24000000 0 0 50000
clk_stimer0 0 0 0 24000000 0 0 50000
clk_capture_pwm0_peri 0 0 0 24000000 0 0 50000
dbclk_gpio4 0 0 0 24000000 0 0 50000
cclk_src_emmc 0 0 0 400000 0 0 50000
emmc_sample 0 0 0 200000 0 0 50000
emmc_drv 0 0 0 200000 0 180 50000
clk_timer_ddrmon 0 0 0 24000000 0 0 50000
clk_vicap_m1 1 1 0 24000000 0 0 50000
sclk_vicap_m1 1 1 0 24000000 0 0 50000
clk_vicap_m0 1 1 0 24000000 0 0 50000
sclk_vicap_m0 1 1 0 24000000 0 0 50000
clk_uart5 0 0 0 24000000 0 0 50000
sclk_uart5 0 0 0 24000000 0 0 50000
clk_uart4 0 0 0 24000000 0 0 50000
sclk_uart4 0 0 0 24000000 0 0 50000
clk_uart3 0 0 0 24000000 0 0 50000
sclk_uart3 0 0 0 24000000 0 0 50000
clk_uart2 1 1 0 24000000 0 0 50000
sclk_uart2 1 1 0 24000000 0 0 50000
clk_uart1 0 0 0 24000000 0 0 50000
sclk_uart1 0 0 0 24000000 0 0 50000
clk_uart0 0 0 0 24000000 0 0 50000
sclk_uart0 0 0 0 24000000 0 0 50000
clk_ref_mipi1 0 0 0 24000000 0 0 50000
mclk_ref_mipi1 0 0 0 24000000 0 0 50000
clk_core_mcu_rtc 1 1 0 24000000 0 0 50000
clk_pvtm_core 0 0 0 24000000 0 0 50000
xin_osc0_half 0 0 0 12000000 0 0 50000
i2s0_8ch_mclkout 0 0 0 12000000 0 0 50000
pll_gpll 1 1 0 1188000000 0 0 50000
gpll 12 12 0 1188000000 0 0 50000
clk_vicap_m1_src 0 0 0 594000000 0 0 50000
clk_vicap_m1_frac 0 0 0 12000000 0 0 50000
clk_vicap_m0_src 0 0 0 594000000 0 0 50000
clk_vicap_m0_frac 0 0 0 12000000 0 0 50000
clk_uart5_src 0 0 0 594000000 0 0 50000
clk_uart5_frac 0 0 0 12000000 0 0 50000
clk_uart4_src 0 0 0 594000000 0 0 50000
clk_uart4_frac 0 0 0 12000000 0 0 50000
clk_uart3_src 0 0 0 594000000 0 0 50000
clk_uart3_frac 0 0 0 12000000 0 0 50000
clk_uart2_src 0 0 0 594000000 0 0 50000
clk_uart2_frac 0 0 0 12000000 0 0 50000
clk_uart1_src 0 0 0 594000000 0 0 50000
clk_uart1_frac 0 0 0 12000000 0 0 50000
clk_uart0_src 0 0 0 594000000 0 0 50000
clk_uart0_frac 0 0 0 12000000 0 0 50000
clk_ref_mipi1_src 0 0 0 594000000 0 0 50000
clk_ref_mipi1_frac 0 0 0 12000000 0 0 50000
clk_ref_mipi0_src 1 1 0 594000000 0 0 50000
clk_ref_mipi0_frac 1 1 0 27000000 0 0 50000
clk_ref_mipi0 1 1 0 27000000 0 0 50000
mclk_ref_mipi0 1 1 0 27000000 0 0 50000
clk_i2s0_8ch_rx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_rx_frac 1 1 0 2048000 0 0 50000
clk_i2s0_8ch_rx 1 1 0 2048000 0 0 50000
mclk_i2s0_8ch_rx 1 1 0 2048000 0 0 50000
clk_i2s0_8ch_tx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_tx_frac 1 1 0 2048000 0 0 50000
clk_i2s0_8ch_tx 1 1 0 2048000 0 0 50000
mclk_i2s0_8ch_tx 2 2 0 2048000 0 0 50000
mclk_sai 0 0 0 2048000 0 0 50000
mclk_dsm 0 0 0 2048000 0 0 50000
mclk_acodec_tx 1 1 0 2048000 0 0 50000
clk_450m_src 1 1 0 475200000 0 0 50000
clk_400m_src 4 4 0 396000000 0 0 50000
cclk_src_sdio 0 0 0 396000000 0 0 50000
sdio_sample 0 0 0 198000000 0 0 50000
sdio_drv 0 0 0 198000000 0 180 50000
clk_core_rga2e 0 0 0 396000000 0 0 50000
aclk_vo_root 1 1 0 396000000 0 0 50000
aclk_rga2e 0 0 0 396000000 0 0 50000
aclk_vepu_com_root 1 1 0 396000000 0 0 50000
dclk_decom 0 0 0 396000000 0 0 50000
aclk_peri_root 1 1 0 396000000 0 0 50000
aclk_ive 0 0 0 396000000 0 0 50000
aclk_decom 0 0 0 396000000 0 0 50000
clk_339m_src 4 4 0 339428572 0 0 50000
clk_core_isp3p2 1 1 0 339428572 0 0 50000
dclk_vicap 1 1 0 339428572 0 0 50000
aclk_vi_root 3 3 0 339428572 0 0 50000
aclk_vicap 1 1 0 339428572 0 0 50000
aclk_isp3p2 1 1 0 339428572 0 0 50000
clk_300m_src 5 5 0 297000000 0 0 50000
sclk_sfc 0 0 0 74250000 0 0 50000
aclk_vop_root 1 1 0 297000000 0 0 50000
aclk_vop 1 1 0 297000000 0 0 50000
aclk_mac_root 1 1 0 297000000 0 0 50000
aclk_mac 1 1 0 297000000 0 0 50000
aclk_vepu_root 2 2 0 297000000 0 0 50000
aclk_vepu_pp 0 0 0 297000000 0 0 50000
aclk_vepu 1 1 0 297000000 0 0 50000
clk_pka_crypto 0 0 0 297000000 0 0 50000
clk_core_crypto 0 0 0 297000000 0 0 50000
aclk_bus_root 3 3 0 297000000 0 0 50000
aclk_usbotg 1 1 0 297000000 0 0 50000
aclk_dmac 1 1 0 297000000 0 0 50000
aclk_crypto 0 0 0 297000000 0 0 50000
clk_200m_src 6 8 0 198000000 0 0 50000
hclk_vo_root 2 2 0 198000000 0 0 50000
hclk_vop 1 1 0 198000000 0 0 50000
hclk_sdio 0 0 0 198000000 0 0 50000
hclk_rga2e 0 0 0 198000000 0 0 50000
clk_core_vepu_dvbm 0 0 0 198000000 0 0 50000
clk_spi0 0 0 0 198000000 0 0 50000
hclk_vepu_root 2 2 0 198000000 0 0 50000
hclk_vepu_pp 0 0 0 198000000 0 0 50000
hclk_vepu 1 1 0 198000000 0 0 50000
clk_i2c1 0 1 0 198000000 0 0 50000
hclk_pmu_root 1 1 0 198000000 0 0 50000
hclk_pmu_sram 0 0 0 198000000 0 0 50000
clk_pmu_mcu 0 0 0 198000000 0 0 50000
clk_100m_pmu 1 1 0 99000000 0 0 50000
pclk_pmu_root 3 4 0 99000000 0 0 50000
pclk_pmu_wdt 0 0 0 99000000 0 0 50000
pclk_pvtm_pmu 0 0 0 99000000 0 0 50000
pclk_pmu_mailbox 0 0 0 99000000 0 0 50000
pclk_i2c1 0 1 0 99000000 0 0 50000
pclk_pmu_gpio0 1 1 0 99000000 0 0 50000
pclk_pmu 1 1 0 99000000 0 0 50000
clk_i2c4 0 1 0 198000000 0 0 50000
clk_i2c3 0 0 0 198000000 0 0 50000
clk_i2c2 0 0 0 198000000 0 0 50000
clk_i2c0 0 0 0 198000000 0 0 50000
hclk_peri_root 2 2 0 198000000 0 0 50000
hclk_trng_s 0 0 0 198000000 0 0 50000
hclk_trng_ns 0 0 0 198000000 0 0 50000
hclk_sai 0 0 0 198000000 0 0 50000
hclk_bootrom 0 0 0 198000000 0 0 50000
hclk_sfc 0 0 0 198000000 0 0 50000
hclk_ive 0 0 0 198000000 0 0 50000
hclk_i2s0 1 1 0 198000000 0 0 50000
hclk_emmc 0 0 0 198000000 0 0 50000
hclk_crypto 0 0 0 198000000 0 0 50000
clk_150m_src 5 5 0 148500000 0 0 50000
pclk_vo_root 4 4 0 148500000 0 0 50000
pclk_tsadc 1 1 0 148500000 0 0 50000
pclk_otp_mask 0 0 0 148500000 0 0 50000
pclk_otpc_s 0 0 0 148500000 0 0 50000
pclk_otpc_ns 0 0 0 148500000 0 0 50000
pclk_mac 2 2 0 148500000 0 0 50000
pclk_gpio2 1 1 0 148500000 0 0 50000
pclk_vi_root 4 4 0 148500000 0 0 50000
pclk_mipicsiphy 1 1 0 148500000 0 0 50000
pclk_gpio3 1 1 0 148500000 0 0 50000
pclk_csihost1 0 0 0 148500000 0 0 50000
pclk_csihost0 1 1 0 148500000 0 0 50000
hclk_vi_root 4 4 0 148500000 0 0 50000
hclk_vicap 1 1 0 148500000 0 0 50000
hclk_sdmmc 1 1 0 148500000 0 0 50000
hclk_isp3p2 1 1 0 148500000 0 0 50000
hclk_npu_root 2 2 0 148500000 0 0 50000
hclk_rknn 1 1 0 148500000 0 0 50000
clk_core_mcu 1 1 0 297000000 0 0 50000
hclk_cpu 1 1 0 198000000 0 0 50000
pll_cpll 1 1 0 1000000000 0 0 50000
cpll 5 5 0 1000000000 0 0 50000
dclk_vop_src 1 1 0 50000000 0 0 50000
dclk_vop 1 1 0 50000000 0 0 50000
clk_500m_src 2 2 0 500000000 0 0 50000
aclk_ddr_root 2 2 0 500000000 0 0 50000
aclk_sys_shrm 1 1 0 500000000 0 0 50000
clk_250m_src 1 1 0 250000000 0 0 50000
clk_100m_src 7 7 0 100000000 0 0 50000
pclk_vepu_root 2 2 0 100000000 0 0 50000
pclk_gpio1 1 1 0 100000000 0 0 50000
pclk_spi0 0 0 0 100000000 0 0 50000
clk_pwm2_peri 0 0 0 100000000 0 0 50000
clk_pwm1_peri 0 0 0 100000000 0 0 50000
clk_pwm0_peri 2 2 0 100000000 0 0 50000
pclk_peri_root 7 9 0 100000000 0 0 50000
pclk_wdt_s 0 0 0 100000000 0 0 50000
pclk_wdt_ns 0 0 0 100000000 0 0 50000
pclk_usbphy 1 1 0 100000000 0 0 50000
pclk_uart5 0 0 0 100000000 0 0 50000
pclk_uart4 0 0 0 100000000 0 0 50000
pclk_uart3 0 0 0 100000000 0 0 50000
pclk_uart2 1 1 0 100000000 0 0 50000
pclk_timer 1 1 0 100000000 0 0 50000
pclk_stimer 0 0 0 100000000 0 0 50000
pclk_spi1 0 0 0 100000000 0 0 50000
pclk_saradc 1 1 0 100000000 0 0 50000
pclk_pwm2_peri 0 0 0 100000000 0 0 50000
pclk_pwm1_peri 0 0 0 100000000 0 0 50000
pclk_uart1 0 0 0 100000000 0 0 50000
pclk_uart0 0 0 0 100000000 0 0 50000
pclk_pwm0_peri 0 2 0 100000000 0 0 50000
pclk_dft2apb 0 0 0 100000000 0 0 50000
pclk_i2c4 0 1 0 100000000 0 0 50000
pclk_i2c3 0 0 0 100000000 0 0 50000
pclk_i2c2 0 0 0 100000000 0 0 50000
pclk_i2c0 0 0 0 100000000 0 0 50000
pclk_gpio4 1 1 0 100000000 0 0 50000
pclk_dsm 0 0 0 100000000 0 0 50000
pclk_decom 0 0 0 100000000 0 0 50000
pclk_acodec 1 1 0 100000000 0 0 50000
pclk_npu_root 1 1 0 100000000 0 0 50000
pclk_ddr_root 2 2 0 100000000 0 0 50000
pclk_dfictrl 1 1 0 100000000 0 0 50000
pclk_ddrc 0 0 0 100000000 0 0 50000
pclk_ddrmon 0 0 0 100000000 0 0 50000
pclk_ddr_hwlp 0 0 0 100000000 0 0 50000
pclk_ddrphy 0 0 0 100000000 0 0 50000
pclk_top_root 1 1 0 100000000 0 0 50000
clk_50m_src 2 2 0 50000000 0 0 50000
clk_gmac0_50m_o 2 2 0 50000000 0 0 50000
clk_gmac0_tx_50m_o 1 1 0 50000000 0 0 50000
clk_gmac0_ref_50m 1 1 0 50000000 0 0 50000
clk_spi1 0 0 0 50000000 0 0 50000
pll_dpll 1 1 0 924000000 0 0 50000
dpll 1 1 0 924000000 0 0 50000
clk_core_ddrc_src 2 2 0 462000000 0 0 50000
clk_core_ddrc 1 1 0 462000000 0 0 50000
aclk_ddrc 1 1 0 462000000 0 0 50000
clk_ddr_phy 0 0 0 462000000 0 0 50000
clk_ddrmon 0 0 0 462000000 0 0 50000
clk_dfictrl 0 0 0 462000000 0 0 50000
pll_apll 1 1 0 1608000000 0 0 50000
apll 1 1 0 1608000000 0 0 50000
armclk 1 1 0 1608000000 0 0 50000
pclk_dbg 2 2 0 201000000 0 0 50000
pclk_cpu_root 2 2 0 201000000 0 0 50000
pclk_mailbox 1 1 0 201000000 0 0 50000
clk_pvtpll_1 1 1 0 420000000 0 0 50000
aclk_npu_root 2 2 0 420000000 0 0 50000
aclk_rknn 1 1 0 420000000 0 0 50000
clk_pvtpll_0 1 1 0 410000000 0 0 50000
clk_core_vepu 1 1 0 410000000 0 0 50000
clk_utmi_usbotg 1 1 0 0 0 0 50000
sclk_in_spi0 0 0 0 0 0 0 50000
pclk_vicap_vepu 1 1 0 0 0 0 50000
clk_rxbyteclkhs_1 0 0 0 0 0 0 50000
clk_rxbyteclkhs_0 1 1 0 0 0 0 50000
pclk_vicap 1 1 0 0 0 0 50000
i1clk_vicap 1 1 0 0 0 0 50000
i0clk_vicap 1 1 0 0 0 0 50000
isp0clk_vicap 2 2 0 0 0 0 50000
rx1pclk_vicap 1 1 0 0 0 0 50000
rx0pclk_vicap 1 1 0 0 0 0 50000#111 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-02 09:53:58
#112 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-08-01 15:11:42
#113 Re: RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-07-29 17:13:52
为了烧写裸奔镜像，这里对xrock工具进行了扩展，支持了RV1103/RV1106芯片
https://github.com/xboot/xrock
烧写指令：
sudo xrock maskrom rv1106_ddr_924MHz_v1.07.bin rv1106_usbplug_v1.03.bin --rc4-off;
sleep 3;
sudo xrock flash write 512 xbootpak.bin;
sudo xrock reset;#114 RK3288/RK3399/RK1108 » RV1103/RV1106 裸奔日记 » 2022-07-29 17:10:58
- xboot
- 回复： 65
RV1103 / RV1106开始裸奔了，要搞定裸奔必须研究透RK的引导机制，经过一整天的深入研究，在没有任何TRM手册的情况下，搞定了RV1106的SPI NAND FLASH引导启动。
下面是启动日记
DDR Version V1.07 20220523
f947
F
DDRConf2
DDR3, BW=16 Col=10 Bk=8 CS0 Row=13 CS=1 Die BW=16 Size=128MB
924MHz
DDR bin out
█████████████████████████
██ ▄▄▄▄▄ ██▄▀▀▀█ ▄▄▄▄▄ ██
██ █ █ █ ▀▄█ █ █ █ ██
██ █▄▄▄█ ██▄ ██ █▄▄▄█ ██
██▄▄▄▄▄▄▄█▄█ █ █▄▄▄▄▄▄▄██
████▀▄ ▀▄▄█ ▀█▄▀█▀▀ █▀██
███▀▄▀ ▀▄ ▄█▀▀▄▀█ ▀█ ▄███
███▄█▄█▄▄▄▀▀ ▄ ▀ ▄▄ ▀ ██
██ ▄▄▄▄▄ █▄ ▄█▄▀▄████▄▄██
██ █ █ █ ▀█▄█▄▄█ ▄▀█▄██
██ █▄▄▄█ ██▀ █ ▄▄▄▄█▄ ██
██▄▄▄▄▄▄▄███▄██▄▄▄▄▄▄▄███
█████████████████████████
_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2022
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (Jul 29 2022 - 16:59:22) - [x1106][X1106 Based On RV1106 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'usbphy480m' with clk-fixed
[ 0.000810]Probe device 'xin24m' with clk-fixed
[ 0.000820]Probe device 'xin32k' with clk-fixed
[ 0.000830]Probe device 'link-uart0' with clk-link
[ 0.000840]Probe device 'link-uart1' with clk-link
[ 0.000850]Probe device 'link-uart2' with clk-link
[ 0.000860]Probe device 'link-uart3' with clk-link
[ 0.000870]Probe device 'link-uart4' with clk-link
[ 0.000880]Probe device 'link-uart5' with clk-link
[ 0.000890]Probe device 'uart-8250.0' with uar & S&LWobe device 'uart-8250.2' with uart-8250
[ 0.000920]Probe device 'uart-8250.3' with uart-8250
[ 0.000930]Probe device 'uart-8250.4' with uart-8250
[ 0.000940]Probe device 'uart-8250.5' with uart-8250
[ 0.000950]Probe device 'console-uart.0' with console-uart
[ 0.001060]mount /private with 'ram' filesystem
xboot: /#
xboot: /# #115 Re: RK3288/RK3399/RK1108 » RV1106/RV1103芯片参数 » 2022-07-29 17:05:46
RV1106 裸奔
DDR Version V1.07 20220523
f947
F
DDRConf2
DDR3, BW=16 Col=10 Bk=8 CS0 Row=13 CS=1 Die BW=16 Size=128MB
924MHz
DDR bin out
█████████████████████████
██ ▄▄▄▄▄ ██▄▀▀▀█ ▄▄▄▄▄ ██
██ █ █ █ ▀▄█ █ █ █ ██
██ █▄▄▄█ ██▄ ██ █▄▄▄█ ██
██▄▄▄▄▄▄▄█▄█ █ █▄▄▄▄▄▄▄██
████▀▄ ▀▄▄█ ▀█▄▀█▀▀ █▀██
███▀▄▀ ▀▄ ▄█▀▀▄▀█ ▀█ ▄███
███▄█▄█▄▄▄▀▀ ▄ ▀ ▄▄ ▀ ██
██ ▄▄▄▄▄ █▄ ▄█▄▀▄████▄▄██
██ █ █ █ ▀█▄█▄▄█ ▄▀█▄██
██ █▄▄▄█ ██▀ █ ▄▄▄▄█▄ ██
██▄▄▄▄▄▄▄███▄██▄▄▄▄▄▄▄███
█████████████████████████
_ _
_ _ | |___ _____ _____ _| |_
\ \/ /| _ | _ | _ |_ _| (C) 2007-2022
) ( | |_| | |_| | |_| | | |____JIANJUN.JIANG__
/_/\_\|_____|_____|_____| |_____________________|
V3.0.0 (Jul 29 2022 - 16:59:22) - [x1106][X1106 Based On RV1106 SOC]
[ 0.000020]Probe device 'blk-romdisk.0' with blk-romdisk
[ 0.000800]Probe device 'usbphy480m' with clk-fixed
[ 0.000810]Probe device 'xin24m' with clk-fixed
[ 0.000820]Probe device 'xin32k' with clk-fixed
[ 0.000830]Probe device 'link-uart0' with clk-link
[ 0.000840]Probe device 'link-uart1' with clk-link
[ 0.000850]Probe device 'link-uart2' with clk-link
[ 0.000860]Probe device 'link-uart3' with clk-link
[ 0.000870]Probe device 'link-uart4' with clk-link
[ 0.000880]Probe device 'link-uart5' with clk-link
[ 0.000890]Probe device 'uart-8250.0' with uar & S&LWobe device 'uart-8250.2' with uart-8250
[ 0.000920]Probe device 'uart-8250.3' with uart-8250
[ 0.000930]Probe device 'uart-8250.4' with uart-8250
[ 0.000940]Probe device 'uart-8250.5' with uart-8250
[ 0.000950]Probe device 'console-uart.0' with console-uart
[ 0.001060]mount /private with 'ram' filesystem
xboot: /# #116 Re: 全志 SOC » XFEL已支持spi nand flash烧写 » 2022-06-28 11:23:11
#117 Re: 全志 SOC » XFEL已支持spi nand flash烧写 » 2022-06-27 19:10:20
#118 Re: 全志 SOC » XFEL已支持spi nand flash烧写 » 2022-06-27 09:58:57
#120 Re: 全志 SOC » T113同时启用RISC-V和A7双核的尝试 » 2022-06-07 09:00:18
#121 Re: RK3288/RK3399/RK1108 » RV1106/RV1103芯片参数 » 2022-06-02 15:38:05
#122 全志 SOC » 自制CKLink-lite调试器，调试D1裸机编程 » 2022-05-26 18:54:48
- xboot
- 回复： 1
#134 全志 SOC » 一个如何让你的客户必须从你这里购买主芯片新思路，抛砖引玉，探讨探讨。（不采用加密芯片的方案） » 2022-05-21 18:14:50
- xboot
- 回复： 16
一年前，写了个帖子https://whycan.com/t_6507.html在全志芯片F1C100S/V3S/V831上实现裸机加密方案，防盗版进行时(不采用专用加密芯片)。
用于解决防盗版问题，这种方案是保护整个产品。
但如果我们的诉求变化了，不是保护完整的产品，仅要保证客户必须从我这里采购芯片，即使客户不从我们这里采购芯片，也能运行，只不过有个恶心的“未授权”提示，体验功能不受任何影响，那么该如何实现呢。同样，不采用任何加密芯片（一个主芯片配一个加密芯片，这种算常规方案，不考虑）
归纳下：
1，要求客户必须从你这里买主芯片，如果是从其他渠道购买的，所有功能都是正常的，但有屏幕有恶心提示，或显示我司联系方式。
2，不采用加密芯片，
3，镜像或者源码可以提供给客户（部分闭源）。
#135 Re: 全志 SOC » T113裸奔之 通过IAR/Jlink 初始化 SDARM...... » 2022-05-16 14:09:41
#136 Re: 全志 SOC » T113裸奔之 通过IAR/Jlink 初始化 SDARM...... » 2022-05-16 10:00:39
#137 Re: RISC-V » 性能最强的 RISC-V 内核单片机：HPM6750 » 2022-05-11 15:08:39
#138 Re: 全志 SOC » T113-s3 spi-nand 启动 » 2022-05-07 20:21:38
#139 Re: 全志 SOC » XFEL已支持spi nand flash烧写 » 2022-04-15 15:19:34
#140 Re: 全志 SOC » 全志V831芯片裸机开发日记--移植V831到xboot » 2022-03-28 09:28:11
#141 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-23 20:08:44
#142 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-23 20:07:34
看了下eggos，里面实现如下syscall，不是全部linux syscall， 这些syscall，绝大部分还是用go写的。
kernelCalls = [...]uintptr{
syscall.SYS_ARCH_PRCTL,
syscall.SYS_MMAP,
syscall.SYS_MUNMAP,
syscall.SYS_CLOCK_GETTIME,
syscall.SYS_RT_SIGPROCMASK,
syscall.SYS_SIGALTSTACK,
syscall.SYS_RT_SIGACTION,
syscall.SYS_GETTID,
syscall.SYS_CLONE,
syscall.SYS_FUTEX,
syscall.SYS_NANOSLEEP,
syscall.SYS_SCHED_YIELD,
syscall.SYS_MADVISE,
syscall.SYS_EXIT_GROUP,
// TODO: real random
unix.SYS_GETRANDOM,
// may removed in the future
syscall.SYS_EPOLL_CREATE1,
syscall.SYS_EPOLL_CTL,
syscall.SYS_EPOLL_WAIT,
syscall.SYS_EPOLL_PWAIT,
syscall.SYS_PIPE2,
SYS_WAIT_IRQ,
SYS_WAIT_SYSCALL,
SYS_FIXED_MMAP,
SYS_EPOLL_NOTIFY,
}#143 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-22 11:02:39
#144 Re: 全志 SOC » 哪位兄弟用过f133移植rtthread 能否提供一下, » 2022-03-22 10:13:07
#145 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-22 10:08:09
#146 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-22 10:02:17
#147 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-22 10:01:07
#148 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-21 20:30:48
#149 Re: 全志 SOC » 发现一个蛮有创意的二维码生成及展示方式，超级终端模式，我用来在系统上电时通过串口来展示芯片唯一ID了。 » 2022-03-21 18:13:46
生成串口二维码的代码，不复杂，就4种字符，其中一个是空格，其他是UTF8字符。支持反显，大部分linux终端，都是黑底白字，所有需要反色显示，当然对于微信，无所谓，正反都可以，但阿里的app，就不支持反显扫码了，这一点，还是微信做的好点。
/* ▀▄█ */
#define UTF8_EMPTY(inv) do{ if(inv) { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x88; } else { *p++ = 0x20; } } while(0)
#define UTF8_TOPHALF(inv) do{ if(inv) { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x84; } else { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x80; } } while(0)
#define UTF8_BOTTOMHALF(inv) do{ if(inv) { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x80; } else { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x84; } } while(0)
#define UTF8_FULL(inv) do{ if(inv) { *p++ = 0x20; } else { *p++ = 0xe2; *p++ = 0x96; *p++ = 0x88; } } while(0)
#define UTF8_NEWLINE() do{ *p++ = '\r'; *p++ = '\n'; } while(0)
#define UTF8_END() do{ *p++ = '\0'; } while(0)
char * qrcgen_tostring(const char * txt, int invert)
{
uint8_t qrc[QRCGEN_BUFFER_LEN_MAX];
uint8_t tmp[QRCGEN_BUFFER_LEN_MAX];
int qrs, x, y, i;
int t, b;
char *s, *p;
if(qrcgen_encode_text(txt, tmp, qrc, QRCGEN_ECC_MEDIUM, QRCGEN_VERSION_MIN, QRCGEN_VERSION_MAX, QRCGEN_MASK_AUTO, 1))
{
qrs = qrcgen_get_size(qrc);
if(qrs > 0)
{
p = s = malloc(((qrs + 4) * 3 + 2) * (qrs / 2 + 1 + 2) + 1);
if(s)
{
for(i = 0; i < qrs + 4; ++i)
UTF8_EMPTY(invert);
UTF8_NEWLINE();
for(y = 0; y < qrs; y += 2)
{
UTF8_EMPTY(invert);
UTF8_EMPTY(invert);
for(x = 0; x < qrs; x++)
{
t = qrcgen_get_pixel(qrc, x, y);
b = 0;
if(y + 1 < qrs)
b = qrcgen_get_pixel(qrc, x, y + 1);
if(t)
{
if(b)
UTF8_FULL(invert);
else
UTF8_TOPHALF(invert);
}
else
{
if(b)
UTF8_BOTTOMHALF(invert);
else
UTF8_EMPTY(invert);
}
}
UTF8_EMPTY(invert);
UTF8_EMPTY(invert);
UTF8_NEWLINE();
}
for(i = 0; i < qrs + 4; i++)
UTF8_EMPTY(invert);
UTF8_NEWLINE();
UTF8_END();
return s;
}
}
}
return NULL;
}
#152 Re: 全志 SOC » XFEL已支持spi nand flash烧写 » 2022-03-21 17:24:35
#153 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-21 17:12:17
#154 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-21 14:05:04
#155 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-21 12:59:02
#156 Re: 全志 SOC » go语言裸机编程探索 » 2022-03-21 09:35:04
#161 Re: 全志 SOC » 全志D1，D1s，F133，T113，R528的SPI控制器跟之前的SOC，有点不太一致，沿用之前的驱动在某些SPI频率上，会出现卡死现象。 » 2022-03-11 18:11:44
#162 全志 SOC » 全志D1，D1s，F133，T113，R528的SPI控制器跟之前的SOC，有点不太一致，沿用之前的驱动在某些SPI频率上，会出现卡死现象。 » 2022-03-11 09:52:05
- xboot
- 回复： 2
坑网LinjieGuo发布了一个帖子，用SPI来驱动WS2811这种灯带，基于此研究成果，我编写了一个WS2812的通用驱动，原贴路径https://whycan.com/t_7742.html
因为此驱动需要4M的SPI时钟，在测试后发现，程序直接卡死，实验了3M同样如此，但2M，及5M，或者50M这些都没有任何问题，SPI驱动一直沿用之前的，什么F1C100S，V3S，V831，都是这一个，因为从来没有在F133上实验过如此低的频率，所以，也一直没有发现问题。现在突然发现这个问题，就有必要去深入研究一下了，初步比较芯片手册，之前的SPI_CCR寄存器没有了。发现多了SPI_BA_CCR之类的寄存器，但虽然SPI_CCR寄存器没有了，但还是可以通过这个寄存器来控制分频。那问题来了这个消失的寄存器，是如何控制分频的，难道是SPI_BA_CCR的马甲寄存器？
有谁研究过F133的SPI控制器驱动吗？可以去linux内核里翻翻，看能否找到蛛丝马迹。
#163 Re: 全志 SOC » 全志V831芯片裸机开发日记--移植V831到xboot » 2022-03-11 09:36:48
#164 Re: DIY/综合/Arduino/写字机/3D打印机/智能小车/平衡车/四轴飞行/MQTT/物联网 » [记录]使用SPI驱动WS2811 » 2022-03-10 20:22:11
更新了下WS2812的驱动，添加缓存支持，提升刷新效率。
26a11c1820cdb4e202a99876c37971684c4634e5
src/driver/led/ledstrip-ws2812.c | 37 ++++++++++++++++++++-----------------
1 file changed, 20 insertions(+), 17 deletions(-)
diff --git a/src/driver/led/ledstrip-ws2812.c b/src/driver/led/ledstrip-ws2812.c
index 6f598bb3e..bc0736ef4 100644
--- a/src/driver/led/ledstrip-ws2812.c
+++ b/src/driver/led/ledstrip-ws2812.c
@@ -47,9 +47,11 @@ struct ledstrip_ws2812_pdata_t {
struct spi_device_t * spidev;
int count;
struct color_t * color;
+ int buflen;
+ unsigned char * buffer;
};
-static const unsigned char ws2812_table[256][5]={
+static const unsigned char ws2812_map[256][5]={
{ 0x84, 0x21, 0x08, 0x42, 0x10, },
{ 0x84, 0x21, 0x08, 0x42, 0x1e, },
{ 0x84, 0x21, 0x08, 0x43, 0xd0, },
@@ -308,12 +310,6 @@ static const unsigned char ws2812_table[256][5]={
{ 0xf7, 0xbd, 0xef, 0x7b, 0xde, },
};
-static void ledstrip_ws2812_send(struct ledstrip_t * strip, unsigned char byte)
-{
- struct ledstrip_ws2812_pdata_t * pdat = (struct ledstrip_ws2812_pdata_t *)strip->priv;
- spi_device_write_then_read(pdat->spidev, (void *)&ws2812_table[byte][0], 5, NULL, 0);
-}
-
static void ledstrip_ws2812_set_count(struct ledstrip_t * strip, int n)
{
struct ledstrip_ws2812_pdata_t * pdat = (struct ledstrip_ws2812_pdata_t *)strip->priv;
@@ -322,9 +318,20 @@ static void ledstrip_ws2812_set_count(struct ledstrip_t * strip, int n)
{
if(pdat->color)
free(pdat->color);
+ if(pdat->buffer)
+ free(pdat->buffer);
pdat->count = n;
pdat->color = malloc(pdat->count * sizeof(struct color_t));
memset(pdat->color, 0, pdat->count * sizeof(struct color_t));
+ pdat->buflen = n * 3 * 5 + 150;
+ pdat->buffer = malloc(pdat->buflen);
+ for(int i = 0; i < n; i++)
+ {
+ memcpy(&pdat->buffer[(i * 3 + 0) * 5], (void *)&ws2812_map[0][0], 5);
+ memcpy(&pdat->buffer[(i * 3 + 1) * 5], (void *)&ws2812_map[0][0], 5);
+ memcpy(&pdat->buffer[(i * 3 + 2) * 5], (void *)&ws2812_map[0][0], 5);
+ }
+ memset(&pdat->buffer[n * 3 * 5], 0, 150);
}
}
@@ -338,6 +345,9 @@ static void ledstrip_ws2812_set_color(struct ledstrip_t * strip, int i, struct c
{
struct ledstrip_ws2812_pdata_t * pdat = (struct ledstrip_ws2812_pdata_t *)strip->priv;
memcpy(&pdat->color[i], c, sizeof(struct color_t));
+ memcpy(&pdat->buffer[(i * 3 + 0) * 5], (void *)&ws2812_map[pdat->color[i].g][0], 5);
+ memcpy(&pdat->buffer[(i * 3 + 1) * 5], (void *)&ws2812_map[pdat->color[i].r][0], 5);
+ memcpy(&pdat->buffer[(i * 3 + 2) * 5], (void *)&ws2812_map[pdat->color[i].b][0], 5);
}
static void ledstrip_ws2812_get_color(struct ledstrip_t * strip, int i, struct color_t * c)
@@ -349,16 +359,7 @@ static void ledstrip_ws2812_get_color(struct ledstrip_t * strip, int i, struct c
static void ledstrip_ws2812_refresh(struct ledstrip_t * strip)
{
struct ledstrip_ws2812_pdata_t * pdat = (struct ledstrip_ws2812_pdata_t *)strip->priv;
- int i;
-
- for(i = 0; i < 150; i++)
- ledstrip_ws2812_send(strip, 0x00);
- for(i = 0; i < pdat->count; i++)
- {
- ledstrip_ws2812_send(strip, pdat->color[i].g);
- ledstrip_ws2812_send(strip, pdat->color[i].r);
- ledstrip_ws2812_send(strip, pdat->color[i].b);
- }
+ spi_device_write_then_read(pdat->spidev, pdat->buffer, pdat->buflen, NULL, 0);
}
static struct device_t * ledstrip_ws2812_probe(struct driver_t * drv, struct dtnode_t * n)
@@ -386,6 +387,8 @@ static struct device_t * ledstrip_ws2812_probe(struct driver_t * drv, struct dtn
pdat->spidev = spidev;
pdat->count = 0;
pdat->color = NULL;
+ pdat->buflen = 0;
+ pdat->buffer = NULL;
strip->name = alloc_device_name(dt_read_name(n), dt_read_id(n));
strip->set_count = ledstrip_ws2812_set_count;
#171 Re: 全志 SOC » 开源一个6000行的2D矢量图形库libcg，零依赖,API接口类似cairo，在某些场景可以代替cairo，特别适合裸奔场景。 » 2022-03-05 13:31:29
void cg_set_operator(struct cg_ctx_t * ctx, enum cg_operator_t op);enum cg_operator_t {
CG_OPERATOR_SRC = 0, /* r = s * ca + d * cia */
CG_OPERATOR_SRC_OVER = 1, /* r = (s + d * sia) * ca + d * cia */
CG_OPERATOR_DST_IN = 2, /* r = d * sa * ca + d * cia */
CG_OPERATOR_DST_OUT = 3, /* r = d * sia * ca + d * cia */
};调用cg_set_operator可以设定合成模式，测试用例没有覆盖所有模式。
#172 Re: 全志 SOC » f133用xfel烧录到ddr2运行正常,烧录到spi没反应 » 2022-03-03 20:10:38
#183 Re: 全志 SOC » 小麻雀 Nezha-MQ 迎来双核A7版本128M内存（基于T113-s3） » 2022-02-16 17:48:46
用xfel工具，很容易读取BROM
https://whycan.com/t_6546.html#p72836
#185 Re: 全志 SOC » 小麻雀 Nezha-MQ 迎来双核A7版本128M内存（基于T113-s3） » 2022-02-16 14:39:58
全志T113-S3编译烧写步骤
https://xboot.org/xboot/#/guide-allwinner-t113s3
编译源码，生成的目标文件在output目录下
make clean
make CROSS_COMPILE=/path/to/arm-none-linux-gnueabihf- PLATFORM=arm32-t113s3烧写到RAM中并运行
sudo xfel ddr t113-s3; sudo xfel write 0x40000000 xboot.bin; sudo xfel exec 0x40000000;烧写普通镜像到SPI Nor Flash
sudo xfel spinor write 0 xboot.bin烧写压缩镜像到SPI Nor Flash
sudo xfel spinor write 0 xboot.bin.z烧写普通镜像到SPI Nand Flash
sudo xfel spinand splwrite 2048 1048576 xboot.bin烧写压缩镜像到SPI Nand Flash
sudo xfel spinand splwrite 2048 1048576 xboot.bin.z现在T113还没有实现get_boot_device函数，默认引导介质为SPI NOR FLASH，F133, D1这些已实现get_boot_device函数。
#187 Re: 全志 SOC » F133的SPL代码DRAM初始化参数是怎样的？ » 2022-02-16 09:29:15
#192 Re: 全志 SOC » 小麻雀 Nezha-MQ 迎来双核A7版本128M内存（基于T113-s3） » 2022-02-14 09:51:42
这是坑网网友mengxp逆向R328-S3 fes1 工程里的相关代码，有一个bond_id_check函数，这个看名字是芯片邦定相关检测函数，感觉没啥大用，理论上全志应该会有一套自己的马甲管理方案的，也便于自己做产品控制，相关信息也一定会在封装时写入了efuse之类的地方，包括开哪个核，等等，这些细节有可能研究出来吗？
uint32_t crc_16(uint16_t reg, uint8_t data_crc)
{
uint32_t ret;
uint16_t v3;
uint16_t v4;
ret = reg ^ (data_crc << 8);
v3 = 8;
do {
v4 = 2 * ret;
v3--;
if ((ret << 16) >= 0)
ret = v4;
else
ret = v4 ^ 0x8005;
} while (v3);
return ret;
}
uint32_t disturb_coding(uint16_t disturb_code, uint8_t id_num)
{
return (disturb_code + id_num) | (crc_16(disturb_code, id_num) << 16);
}
uint32_t id_judge_fun(uint16_t disturb_code)
{
uint32_t chipId;
uint8_t v5;
uint32_t ret;
chipId = MEMORY(0x3006200) & 0xF;
printf("the chip id is 0x%x\n", chipId);
if (chipId == 3)
{
v5 = 7;
ret = disturb_coding(disturb_code, v5);
}
else
{
v5 = 1;
ret = 0;
}
return ret;
}
int bond_id_check(void)
{
uint8_t v0;
uint32_t v1;
uint16_t v3;
uint32_t v4;
v0 = 1;
v1 = id_judge_fun(0);
while (v1 != disturb_coding(0, v0))
{
v0++;
if (v0 == 17)
return 0;
}
v3 = 1;
while (1)
{
v4 = id_judge_fun(v3);
if (v4 != disturb_coding(v3, v0))
break;
v3++;
if (v3 == 5)
return 1;
}
return 0;
}
int chip_id_check(void)
{
uint32_t chipId = MEMORY(0x3006200) & 0xF;
if(chipId != 3)
return 0;
return 1;
}#193 Re: 全志 SOC » 小麻雀 Nezha-MQ 迎来双核A7版本128M内存（基于T113-s3） » 2022-02-14 09:39:19
现在有个棘手的问题，fel模式下如果通过代码的方式区分这些马甲，已知有两类，RISCV单核一类，ARM双核一类。
RISCV 单核，D1/F133，检测代码
static int chip_detect(struct xfel_ctx_t * ctx, uint32_t id)
{
if(id == 0x00185900)
{
/*
* XuanTie C906 RISC-V
*/
if(R32(0x00000000) == 0x43014281)
return 1;
}
return 0;
}ARM双核，R528/T113，检测代码
static int chip_detect(struct xfel_ctx_t * ctx, uint32_t id)
{
if(id == 0x00185900)
{
/*
* Dual-Core ARM Cortex-A7
*/
if(R32(0x00000000) == 0xea000019)
return 1;
}
return 0;
}这里通过读取0地址的机器码来判断是开启的是RISCV还是ARM核，但如何进一步区分，这马甲是R528还是T113呢？或者更近一步，能区分出马甲的尾缀，比如R528-S2，R528-S3，T113-S2，T113-S3这些马甲呢？
有没有相关解决这个问题的思路呢，大家来点脑洞吧，也许真能找到完美解决方案。
#195 Re: 全志 SOC » f1c100s上跑xboot,移植gt911求助 » 2022-02-09 19:46:14
#196 Re: 全志 SOC » f1c100s上跑xboot,移植gt911求助 » 2022-02-09 18:41:04
#197 Re: 全志 SOC » f1c100s上跑xboot,移植gt911求助 » 2022-02-09 18:39:34
只要关心这个配置，填如GPIO编号即可，中断号无需关心，系统会通过gpio_to_irq来获取具体的中断号
"interrupt-gpio": 137,
"interrupt-gpio-config": 6,
"reset-gpio": 138,
"reset-gpio-config": 1GPIO 编号如下：
#define F1C100S_GPIOA0 (0)
#define F1C100S_GPIOA1 (1)
#define F1C100S_GPIOA2 (2)
#define F1C100S_GPIOA3 (3)
#define F1C100S_GPIOC0 (64)
#define F1C100S_GPIOC1 (65)
#define F1C100S_GPIOC2 (66)
#define F1C100S_GPIOC3 (67)
#define F1C100S_GPIOD0 (96)
#define F1C100S_GPIOD1 (97)
#define F1C100S_GPIOD2 (98)
#define F1C100S_GPIOD3 (99)
#define F1C100S_GPIOD4 (100)
#define F1C100S_GPIOD5 (101)
#define F1C100S_GPIOD6 (102)
#define F1C100S_GPIOD7 (103)
#define F1C100S_GPIOD8 (104)
#define F1C100S_GPIOD9 (105)
#define F1C100S_GPIOD10 (106)
#define F1C100S_GPIOD11 (107)
#define F1C100S_GPIOD12 (108)
#define F1C100S_GPIOD13 (109)
#define F1C100S_GPIOD14 (110)
#define F1C100S_GPIOD15 (111)
#define F1C100S_GPIOD16 (112)
#define F1C100S_GPIOD17 (113)
#define F1C100S_GPIOD18 (114)
#define F1C100S_GPIOD19 (115)
#define F1C100S_GPIOD20 (116)
#define F1C100S_GPIOD21 (117)
#define F1C100S_GPIOE0 (128)
#define F1C100S_GPIOE1 (129)
#define F1C100S_GPIOE2 (130)
#define F1C100S_GPIOE3 (131)
#define F1C100S_GPIOE4 (132)
#define F1C100S_GPIOE5 (133)
#define F1C100S_GPIOE6 (134)
#define F1C100S_GPIOE7 (135)
#define F1C100S_GPIOE8 (136)
#define F1C100S_GPIOE9 (137)
#define F1C100S_GPIOE10 (138)
#define F1C100S_GPIOE11 (139)
#define F1C100S_GPIOE12 (140)
#define F1C100S_GPIOF0 (160)
#define F1C100S_GPIOF1 (161)
#define F1C100S_GPIOF2 (162)
#define F1C100S_GPIOF3 (163)
#define F1C100S_GPIOF4 (164)
#define F1C100S_GPIOF5 (165)#198 Re: 全志 SOC » 开源一个6000行的2D矢量图形库libcg，零依赖,API接口类似cairo，在某些场景可以代替cairo，特别适合裸奔场景。 » 2022-02-09 14:39:15
#199 Re: 全志 SOC » 用F1C100S开发了一个项目，原始技术实现，裸奔XUI GUI框架 » 2022-02-08 09:37:46
#200 Re: 全志 SOC » RK3568 boot下载失败处理方法 » 2022-02-08 09:33:25
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