WhyCan Forum(哇酷开发者社区)

* disable irq type */
     1 static void spi_disable_irq(u32 bitmap, void __iomem *base_addr)
     2 {
     5     u32 reg_val = readl(base_addr + SPI_INT_CTL_REG);
     6 
     7     bitmap &= SPI_INTEN_MASK;
     8     reg_val &= ~bitmap;
     9     writel(reg_val, base_addr + SPI_INT_CTL_REG);
    10 }

nt spi_xfer(struct spi_slave *slave, unsigned int bitlen,
     1         const void *dout, void *din, unsigned long flags)
     2 {
     3     struct sunxi_spi_slave *sspi = to_sunxi_slave(slave);
     4     unsigned int len = bitlen / 8;
     5     int timeout = 0xfffff;
     6     printf("bus:%X, cs:%X, bus:%X, base addr:%X\n", sspi->slave.bus, sspi->slave.cs, sspi->bus, sspi-
     7     void __iomem *base_addr = (void __iomem *)(unsigned long)sspi->base_addr;
     8 

partno erro : can't find partition bootloader                                                               
[00.521]bmp_name=bootlogo.bmp size 84870                                                                    
bus:EA000019, cs:EAFFFFFE, bus:E8FD9FFF, base addr:EB00007D                                                 
data abort                                                                                                  
pc : [<47f0bb36>]          lr : [<47f0baf9>]                                                                
reloc pc : [<43042b36>]    lr : [<43042af9>]                                                                
sp : 43e66cd8  ip : 00000000     fp : 47fb494c                                                              
r10: 00000000  r9 : 43ea8e70     r8 : 43e66d0c                                                              
r7 : 00000000  r6 : 43e66d08     r5 : 00000000  r4 : eb00007d                                               
r3 : 0000002a  r2 : 80000000     r1 : 43e66d09  r0 : 47fb493c                                               
Flags: nZcv  IRQs on  FIQs off  Mode SVC_32                                                                 
Code: bf142e00 f04f46aa f1b80a00 bf080f00 (69232500)                                                        
bus:1, cs:0, bus:1, base addr:4026000                                                                       
bus:1, cs:0, bus:1, base addr:4026000                                                                       
bus:1, cs:0, bus:1, base addr:4026000                                                                       
bus:1, cs:0, bus:1, base addr:4026000      

 	spi0_pins_a: spi0@0 {
		pins = "PC2", "PC4", "PC5"; /* clk, mosi, miso */
		function = "spi0";
		muxsel = <2>;
		drive-strength = <20>;
	};

	spi0_pins_b: spi0@1 {
/*		pins = "PC3", "PC7", "PC6"; */
		pins = "PC3"; 
		function = "spi0";
		muxsel = <2>;
		drive-strength = <20>;
		bias-pull-up;   /* cs, hold, wp should be pulled up */
	};

 &spi0 {
	clock-frequency = <100000000>;
	pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
	pinctrl-1 = <&spi0_pins_c>;
	pinctrl-names = "default", "sleep";
	/*spi-supply = <&reg_dcdc1>;*/
	spi_slave_mode = <0>;
	spi0_cs_number = <1>;
    spi0_cs_bitmap = <1>;
	status = "okay";

	eth1: dm9051@0 {
		compatible = "davicom,dm9051";
		spi-max-frequency=<80000000>;
		reg = <0x0>;
		spi-rx-bus-width = <0x01>;
		spi-tx-bus-width = <0x01>;

    	interrupt-parent = <&pio>;
		interrupts = <PC 7 IRQ_TYPE_EDGE_FALLING>;

        reset-gpios = <&pio PC 6 GPIO_ACTIVE_LOW>;

        local-mac-address = [ 00 60 6e 99 5a a5 ];

/*
		spi-cpol;
		spi-cpha;
*/
		status = "okay";

	};
};

/*
 * drivers/spi/spi-sunxi.c
 *
 * Copyright (C) 2012 - 2016 Reuuimlla Limited
 * Pan Nan <pannan@reuuimllatech.com>
 *
 * SUNXI SPI Controller Driver
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * 2013.5.7 Mintow <duanmintao@allwinnertech.com>
 *    Adapt to support sun8i/sun9i of Allwinner.
 *
 * 2021-3-2 liuyu <liuyu@allwinnertech.com>
 *	1 : use the new kernel framework to transfer
 *	2 : support soft cs gpio
 *	3 : delet unused dts node : cs_bitmap
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/pinctrl/consumer.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/spi/spi_bitbang.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/sched.h>
#include <linux/kthread.h>
#include <linux/signal.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/clk/sunxi.h>
#include <linux/regulator/consumer.h>
#include "spi-sunxi.h"
#include "spi-slave-protocol.h"

/* For debug */
#define SPI_ERR(fmt, arg...)	pr_warn("%s()%d - "fmt, __func__, __LINE__, ##arg)

static u32 debug_mask = 1;
#define dprintk(level_mask, fmt, arg...)				\
do {									\
	if (unlikely(debug_mask & level_mask))				\
		pr_warn("%s()%d - "fmt, __func__, __LINE__, ##arg);	\
} while (0)

#define SUNXI_SPI_OK   0
#define SUNXI_SPI_FAIL -1

#define XFER_TIMEOUT	5000

enum spi_mode_type {
	SINGLE_HALF_DUPLEX_RX,		/* single mode, half duplex read */
	SINGLE_HALF_DUPLEX_TX,		/* single mode, half duplex write */
	SINGLE_FULL_DUPLEX_RX_TX,	/* single mode, full duplex read and write */
	DUAL_HALF_DUPLEX_RX,		/* dual mode, half duplex read */
	DUAL_HALF_DUPLEX_TX,		/* dual mode, half duplex write */
	QUAD_HALF_DUPLEX_RX,		/* quad mode, half duplex read */
	QUAD_HALF_DUPLEX_TX,		/* quad mode, half duplex write */
	MODE_TYPE_NULL,
};

#if IS_ENABLED(CONFIG_DMA_ENGINE)

#define SPI_MAX_PAGES	100
enum spi_dma_dir {
	SPI_DMA_RWNULL,
	SPI_DMA_WDEV = DMA_TO_DEVICE,
	SPI_DMA_RDEV = DMA_FROM_DEVICE,
};

typedef struct {
	enum spi_dma_dir dir;
	struct dma_chan *chan;
	int nents;
	struct scatterlist sg[SPI_MAX_PAGES];
	struct page *pages[SPI_MAX_PAGES];
} spi_dma_info_t;

u64 sunxi_spi_dma_mask = DMA_BIT_MASK(32);

#endif

struct sunxi_spi {
	#define SPI_FREE   (1<<0)
	#define SPI_SUSPND (1<<1)
	#define SPI_BUSY   (1<<2)

#if IS_ENABLED(CONFIG_DMA_ENGINE)
	spi_dma_info_t dma_rx;
	spi_dma_info_t dma_tx;
#endif

	struct platform_device *pdev;
	struct spi_master *master;/* kzalloc */
	struct spi_device *spi;
	struct spi_dbi_config *dbi_config;
	struct sunxi_slave *slave;
	struct pinctrl		 *pctrl;

	struct clk *pclk;  /* PLL clock */
	struct clk *mclk;  /* spi module clock */
	struct clk *bus_clk; /*spi bus clock*/
	struct reset_control *reset; /*reset clock*/

	struct task_struct *task;

	struct completion done;  /* wakup another spi transfer */
	spinlock_t lock;

	char dev_name[48];
	enum spi_mode_type mode_type;
	void __iomem *base_addr; /* register */

	u32 base_addr_phy;
	u32 mode; /* 0: master mode, 1: slave mode */
	u32 irq; /* irq NO. */
	int busy;
	int result; /* 0: succeed -1:fail */
	int task_flag;
	int dbi_enabled;
	u32 sample_mode;
	u32 sample_delay;
};

int spi_get_dbi_config(const struct spi_device *spi, struct spi_dbi_config *dbi_config)
{
	struct sunxi_spi *sspi = spi->master->dev.driver_data;

	if (!sspi->dbi_enabled)
		return -EINVAL;

	memcpy(dbi_config, sspi->dbi_config, sizeof(struct spi_dbi_config));
	return 0;
}
EXPORT_SYMBOL_GPL(spi_get_dbi_config);

int spi_set_dbi_config(struct spi_device *spi, const struct spi_dbi_config *dbi_config)
{
	struct sunxi_spi *sspi = spi->master->dev.driver_data;

	if (!sspi->dbi_enabled)
		return -EINVAL;

	memcpy(sspi->dbi_config, dbi_config, sizeof(struct spi_dbi_config));
	return 0;
}
EXPORT_SYMBOL_GPL(spi_set_dbi_config);

void spi_dump_reg(struct sunxi_spi *sspi, u32 offset, u32 len)
{
	u32 i;
	u8 buf[64], cnt = 0;

	for (i = 0; i < len; i = i + REG_INTERVAL) {
		if (i%HEXADECIMAL == 0)
			cnt += sprintf(buf + cnt, "0x%08x: ",
					(u32)(sspi->base_addr_phy  + offset + i));

		cnt += sprintf(buf + cnt, "%08x ",
				readl(sspi->base_addr + offset + i));

		if (i%HEXADECIMAL == REG_CL) {
			pr_warn("%s\n", buf);
			cnt = 0;
		}
	}
}

void spi_dump_data(u8 *buf, u32 len)
{
	u32 i, cnt = 0;
	u8 *tmp;

	tmp = kzalloc(len, GFP_KERNEL);
	if (!tmp)
		return;

	for (i = 0; i < len; i++) {
		if (i%HEXADECIMAL == 0)
			cnt += sprintf(tmp + cnt, "0x%08x: ", i);

		cnt += sprintf(tmp + cnt, "%02x ", buf[i]);

		if ((i%HEXADECIMAL == REG_END) || (i == (len - 1))) {
			pr_warn("%s\n", tmp);
			cnt = 0;
		}
	}

	kfree(tmp);
}

static void dbi_disable_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_DBI_INT_REG);

	bitmap &= DBI_INT_STA_MASK;
	reg_val &= ~bitmap;
	writel(reg_val, base_addr + SPI_DBI_INT_REG);
}

static void dbi_enable_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_DBI_INT_REG);


	bitmap &= DBI_INT_STA_MASK;
	reg_val |= bitmap;
	writel(reg_val, base_addr + SPI_DBI_INT_REG);
}

static s32 set_dbi_timer_param(struct sunxi_spi *sspi, struct spi_device *spi)
{
	u32 timer_val = 0, pixel_cycle = 0;
	s32 ret = -1;
	void __iomem *base_addr = sspi->base_addr;

	if (!sspi || !base_addr)
		goto OUT;

	goto OUT; /*not use */

	if (sspi->dbi_config->dbi_te_en || !sspi->dbi_config->dbi_fps) {
		writel(0x0, base_addr + SPI_DBI_TIMER_REG);
		goto OUT;
	}

	if (sspi->dbi_config->dbi_interface == D2LI) {
		switch (sspi->dbi_config->dbi_format) {
		case DBI_RGB111:
			pixel_cycle = 8;
			break;
		case DBI_RGB444:
		case DBI_RGB565:
			pixel_cycle = 9;
			break;
		case DBI_RGB666:
			pixel_cycle = 10;
			break;
		case DBI_RGB888:
			pixel_cycle = 13;
			break;
		default:
			break;
		}
	} else {
		switch (sspi->dbi_config->dbi_format) {
		case DBI_RGB111:
			pixel_cycle = 8;
			break;
		case DBI_RGB444:
			pixel_cycle = 12;
			break;
		case DBI_RGB565:
			pixel_cycle = 16;
			break;
		case DBI_RGB666:
		case DBI_RGB888:
			pixel_cycle = 24;
			break;
		default:
			break;
		}
	}
	timer_val = spi->max_speed_hz / sspi->dbi_config->dbi_fps -
		    pixel_cycle * sspi->dbi_config->dbi_video_h * sspi->dbi_config->dbi_video_v;

	timer_val |= 0x80000000;
	writel(timer_val, base_addr + SPI_DBI_TIMER_REG);
	ret = 0;

OUT:
	return ret;
}

/* config dbi */
static void spi_config_dbi(struct sunxi_spi *sspi, struct spi_device *spi)
{
	u32 reg_val = 0;
	u32 reg_tmp = 0;
	u32 config = sspi->dbi_config->dbi_mode;
	void __iomem *base_addr = sspi->base_addr;

	/*1. command type */
	if (config & SPI_DBI_COMMAND_READ_) {
		reg_val |= DBI_CR_READ;
		reg_tmp = readl(base_addr + SPI_DBI_CR_REG1);
		writel(reg_tmp | sspi->dbi_config->dbi_read_bytes,
			base_addr + SPI_DBI_CR_REG1);
	} else
		reg_val &= ~DBI_CR_READ;

	/*3. output data sequence */
	if (config & SPI_DBI_LSB_FIRST_)
		reg_val |= DBI_CR_LSB_FIRST;
	else
		reg_val &= ~DBI_CR_LSB_FIRST;

	/*4. transmit data type */
	if (config & SPI_DBI_TRANSMIT_VIDEO_) {
		reg_val |= DBI_CR_TRANSMIT_MODE;
		writel((sspi->dbi_config->dbi_video_v << 16)|(sspi->dbi_config->dbi_video_h),
			base_addr + SPI_DBI_VIDEO_SIZE);
		if (sspi->dbi_config->dbi_te_en)
			dbi_enable_irq(DBI_TE_INT_EN, base_addr);
		else
			dbi_enable_irq(DBI_FRAM_DONE_INT_EN, base_addr);
	} else {
		reg_val &= ~DBI_CR_TRANSMIT_MODE;

		writel(0x0, base_addr + SPI_DBI_VIDEO_SIZE);
		dbi_disable_irq(DBI_FRAM_DONE_INT_EN | DBI_TE_INT_EN, base_addr);
		dbi_enable_irq(DBI_FIFO_EMPTY_INT_EN, base_addr);
	}


	/*5. output data format */
	reg_val &= ~(DBI_CR_FORMAT_MASK);
	if (sspi->dbi_config->dbi_format == DBI_RGB111)
		reg_val &= ~(0x7 << DBI_CR_FORMAT);
	else
		reg_val |= ((sspi->dbi_config->dbi_format) << DBI_CR_FORMAT);

	/*6. dbi interface select */
	reg_val &= ~(DBI_CR_INTERFACE_MASK);

	if (sspi->dbi_config->dbi_interface == L3I1)
		reg_val &= ~((0x7) << DBI_CR_INTERFACE);
	else
		reg_val |= ((sspi->dbi_config->dbi_interface) << DBI_CR_INTERFACE);

	if (sspi->dbi_config->dbi_format <= DBI_RGB565)
		reg_val |= 0x1;
	else
		reg_val &= ~0x1;

	if (sspi->dbi_config->dbi_out_sequence == DBI_OUT_RGB)
		reg_val &= ~((0x7) << 16);
	else
		reg_val |= ((sspi->dbi_config->dbi_out_sequence) << 16);

	if (sspi->dbi_config->dbi_src_sequence == DBI_SRC_RGB)
		reg_val &= ~((0xf) << 4);
	else
		reg_val |= ((sspi->dbi_config->dbi_src_sequence) << 4);

	if (sspi->dbi_config->dbi_rgb_bit_order == 1)
		reg_val |= ((0x1) << 2);
	else
		reg_val &= ~((0x1) << 2);

	if (sspi->dbi_config->dbi_rgb32_alpha_pos == 1)
		reg_val |= ((0x1) << 1);
	else
		reg_val &= ~((0x1) << 1);

	writel(reg_val, base_addr + SPI_DBI_CR_REG);

	reg_val = 0;

	if (sspi->dbi_config->dbi_interface == D2LI) {
		reg_val |= DBI_CR2_DCX_PIN;
		reg_val &= ~DBI_CR2_SDI_PIN;
	} else {
		reg_val |= DBI_CR2_SDI_PIN;
		reg_val &= ~DBI_CR2_DCX_PIN;
	}

	if ((sspi->dbi_config->dbi_te_en == DBI_TE_DISABLE) ||
	    !(config & SPI_DBI_TRANSMIT_VIDEO_)) {
		reg_val &= ~(0x3 << 0); // te disable
	} else {
		/*te enable*/
		reg_val |= 0x1;
		if (sspi->dbi_config->dbi_te_en == DBI_TE_FALLING_EDGE)
			reg_val |= (0x1 << 1);
		else
			reg_val &= ~(0x1 << 1);
	}

	writel(reg_val, base_addr + SPI_DBI_CR_REG2);


	dprintk(DEBUG_INFO, "DBI mode configurate : %x\n", reg_val);

	reg_val = 0;
	if (config & SPI_DBI_DCX_DATA_)
		reg_val |= DBI_CR1_DCX_DATA;
	else
		reg_val &= ~DBI_CR1_DCX_DATA;

	if (sspi->dbi_config->dbi_rgb16_pixel_endian == 1)
		reg_val |= ((0x1) << 21);
	else
		reg_val &= ~((0x1) << 21);

	/* dbi en mode sel */
	if ((sspi->dbi_config->dbi_te_en == DBI_TE_DISABLE) ||
	    !(config & SPI_DBI_TRANSMIT_VIDEO_)) {
		if (!set_dbi_timer_param(sspi, spi))
			reg_val |= (0x2 << 29); // timer trigger mode
		else
			reg_val &= ~(0x3 << 29); // always on mode
	} else {
		/*te trigger mode */
		reg_val |= ((0x3) << 29);
	}

	/* config dbi clock mode: auto gating */
	if (sspi->dbi_config->dbi_clk_out_mode == SPI_DBI_CLK_ALWAYS_ON)
		reg_val &= ~(DBI_CR1_CLK_AUTO);
	else
		reg_val |= DBI_CR1_CLK_AUTO;

	writel(reg_val, base_addr + SPI_DBI_CR_REG1);

	if ((debug_mask & DEBUG_INIT) && (debug_mask & DEBUG_DATA)) {
		dprintk(DEBUG_DATA, "[spi%d] dbi register dump reg:\n", sspi->master->bus_num);
		spi_dump_reg(sspi, 0x100, 0x30);
	}
}

/* enable spi dbi */
static void spi_enable_dbi(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_DBI_EN;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* set dbi mode */
static void spi_set_dbi(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_DBI_MODE_SEL;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* spi controller config chip select
 * only spi controller cs mode can use this function
 * */
static s32 sunxi_spi_ss_select(u32 chipselect, void __iomem *base_addr)
{
	char ret;
	u32 reg_val = readl(base_addr + SPI_TC_REG);

	if (chipselect < 4) {
		reg_val &= ~SPI_TC_SS_MASK;/* SS-chip select, clear two bits */
		reg_val |= chipselect << SPI_TC_SS_BIT_POS;/* set chip select */
		writel(reg_val, base_addr + SPI_TC_REG);
		ret = SUNXI_SPI_OK;
	} else {
		SPI_ERR("Chip Select set fail! cs = %d\n", chipselect);
		ret = SUNXI_SPI_FAIL;
	}

	return ret;
}

/* config spi */
static void spi_config_tc(u32 master, u32 config, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_TC_REG);

	/*1. POL */
	if (config & SPI_POL_ACTIVE_)
		reg_val |= SPI_TC_POL;/*default POL = 1 */
	else
		reg_val &= ~SPI_TC_POL;

	/*2. PHA */
	if (config & SPI_PHA_ACTIVE_)
		reg_val |= SPI_TC_PHA;/*default PHA = 1 */
	else
		reg_val &= ~SPI_TC_PHA;

	/*3. SSPOL,chip select signal polarity */
	if (config & SPI_CS_HIGH_ACTIVE_)
		reg_val &= ~SPI_TC_SPOL;
	else
		reg_val |= SPI_TC_SPOL; /*default SSPOL = 1,Low level effect */

	/*4. LMTF--LSB/MSB transfer first select */
	if (config & SPI_LSB_FIRST_ACTIVE_)
		reg_val |= SPI_TC_FBS;
	else
		reg_val &= ~SPI_TC_FBS;/*default LMTF =0, MSB first */

	/*master mode: set DDB,DHB,SMC,SSCTL*/
	if (master == 1) {
		/*5. dummy burst type */
		if (config & SPI_DUMMY_ONE_ACTIVE_)
			reg_val |= SPI_TC_DDB;
		else
			reg_val &= ~SPI_TC_DDB;/*default DDB =0, ZERO */

		/*6.discard hash burst-DHB */
		if (config & SPI_RECEIVE_ALL_ACTIVE_)
			reg_val &= ~SPI_TC_DHB;
		else
			reg_val |= SPI_TC_DHB;/*default DHB =1, discard unused burst */

		/*7. set SMC = 1 , SSCTL = 0 ,TPE = 1 */
		reg_val &= ~SPI_TC_SSCTL;
	} else {
		/* tips for slave mode config */
		dprintk(DEBUG_INFO, "slave mode configurate control register\n");
	}

	writel(reg_val, base_addr + SPI_TC_REG);
}

/* set spi clock */
static void spi_set_clk(u32 spi_clk, u32 ahb_clk, struct sunxi_spi *sspi)
{
	dprintk(DEBUG_INFO, "set spi clock %d, mclk %d\n", spi_clk, ahb_clk);

	clk_set_rate(sspi->mclk, spi_clk);
	if (clk_get_rate(sspi->mclk) != spi_clk) {
#if 0
		clk_set_rate(sspi->mclk, ahb_clk);
		SPI_ERR("[spi%d] set spi clock failed, use clk:%d\n",
				sspi->master->bus_num, ahb_clk);
#else
        //add by fae
		u32 get_spi = clk_set_rate(sspi->mclk, spi_clk);
		clk_set_rate(sspi->mclk, get_spi);

		SPI_ERR("[spi%d] set spi clock failed, use clk:%d\n",
				sspi->master->bus_num, get_spi);
#endif
	}
}

/* delay internal read sample point*/
static void spi_sample_delay(u32 sdm, u32 sdc, u32 sdc1,
					void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_TC_REG);
	u32 org_val = reg_val;

	if (sdm)
		reg_val |= SPI_TC_SDM;
	else
		reg_val &= ~SPI_TC_SDM;

	if (sdc)
		reg_val |= SPI_TC_SDC;
	else
		reg_val &= ~SPI_TC_SDC;

	if (sdc1)
		reg_val |= SPI_TC_SDC1;
	else
		reg_val &= ~SPI_TC_SDC1;

	if (reg_val != org_val)
		writel(reg_val, base_addr + SPI_TC_REG);
}

static void spi_set_sample_mode(unsigned int mode, void __iomem *base_addr)
{
	unsigned int sample_mode[7] = {
		DELAY_NORMAL_SAMPLE, DELAY_0_5_CYCLE_SAMPLE,
		DELAY_1_CYCLE_SAMPLE, DELAY_1_5_CYCLE_SAMPLE,
		DELAY_2_CYCLE_SAMPLE, DELAY_2_5_CYCLE_SAMPLE,
		DELAY_3_CYCLE_SAMPLE
	};
	spi_sample_delay((sample_mode[mode] >> DELAY_SDM_POS) & 0xf,
			(sample_mode[mode] >> DELAY_SDC_POS) & 0xf,
			(sample_mode[mode] >>  DELAY_SDC1_POS)& 0xf,
			base_addr);
}

static void spi_samp_dl_sw_status(unsigned int status, void __iomem *base_addr)
{
	unsigned int rval = readl(base_addr + SPI_SAMPLE_DELAY_REG);

	if (status)
		rval |= SPI_SAMP_DL_SW_EN;
	else
		rval &= ~SPI_SAMP_DL_SW_EN;

	writel(rval, base_addr + SPI_SAMPLE_DELAY_REG);
}

static void spi_samp_mode_enable(unsigned int status, void __iomem *base_addr)
{
	unsigned int rval = readl(base_addr + SPI_GC_REG);

	if (status)
		rval |= SPI_SAMP_MODE_EN;
	else
		rval &= ~SPI_SAMP_MODE_EN;

	writel(rval, base_addr + SPI_GC_REG);
}

static void spi_set_sample_delay(unsigned int sample_delay,
		void __iomem *base_addr)
{
	unsigned int rval = readl(base_addr + SPI_SAMPLE_DELAY_REG)
					& (~(0x3f << 0));

	rval |= sample_delay;
	writel(rval, base_addr + SPI_SAMPLE_DELAY_REG);
}

/* start spi transfer */
static void spi_start_xfer(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_TC_REG);

	reg_val |= SPI_TC_XCH;
	writel(reg_val, base_addr + SPI_TC_REG);
}

/* enable spi bus */
static void spi_enable_bus(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_EN;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* disbale spi bus */
static void spi_disable_bus(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val &= ~SPI_GC_EN;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* set master mode */
static void spi_set_master(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_MODE;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* set slaev mode */
static void spi_set_slave(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);
	u32 val = SPI_GC_MODE;

	reg_val &= ~val;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* enable transmit pause */
static void spi_enable_tp(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_TP_EN;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* soft reset spi controller */
static void spi_soft_reset(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_GC_REG);

	reg_val |= SPI_GC_SRST;
	writel(reg_val, base_addr + SPI_GC_REG);
}

/* enable irq type */
static void spi_enable_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_INT_CTL_REG);

	bitmap &= SPI_INTEN_MASK;
	reg_val |= bitmap;
	writel(reg_val, base_addr + SPI_INT_CTL_REG);
}

/* disable irq type */
static void spi_disable_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_INT_CTL_REG);

	bitmap &= SPI_INTEN_MASK;
	reg_val &= ~bitmap;
	writel(reg_val, base_addr + SPI_INT_CTL_REG);
}

#if IS_ENABLED(CONFIG_DMA_ENGINE)
/* enable dma irq */
static void spi_enable_dma_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG);

	bitmap &= SPI_FIFO_CTL_DRQEN_MASK;
	reg_val |= bitmap;
	writel(reg_val, base_addr + SPI_FIFO_CTL_REG);

	spi_set_dma_mode(base_addr);
}

/* disable dma irq */
static void spi_disable_dma_irq(u32 bitmap, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG);

	bitmap &= SPI_FIFO_CTL_DRQEN_MASK;
	reg_val &= ~bitmap;
	writel(reg_val, base_addr + SPI_FIFO_CTL_REG);
}

static void spi_enable_dbi_dma(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_DBI_CR_REG2);

	reg_val |= DBI_CR2_DMA_ENABLE;
	writel(reg_val, base_addr + SPI_DBI_CR_REG2);
}

static void spi_disable_dbi_dma(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_DBI_CR_REG2);

	reg_val &= ~(DBI_CR2_DMA_ENABLE);
	writel(reg_val, base_addr + SPI_DBI_CR_REG2);
}
#endif

/* query irq enable */
static u32 spi_qry_irq_enable(void __iomem *base_addr)
{
	return (SPI_INTEN_MASK & readl(base_addr + SPI_INT_CTL_REG));
}

/* query dbi irq pending */
static u32 dbi_qry_irq_pending(void __iomem *base_addr)
{
	return (DBI_INT_STA_MASK & readl(base_addr + SPI_DBI_INT_REG));
}

/* clear irq pending */
static void dbi_clr_irq_pending(u32 pending_bit, void __iomem *base_addr)
{
	pending_bit &= DBI_INT_STA_MASK;
	writel(pending_bit, base_addr + SPI_DBI_INT_REG);
}

/* query irq pending */
static u32 spi_qry_irq_pending(void __iomem *base_addr)
{
	return (SPI_INT_STA_MASK & readl(base_addr + SPI_INT_STA_REG));
}

/* clear irq pending */
static void spi_clr_irq_pending(u32 pending_bit, void __iomem *base_addr)
{
	pending_bit &= SPI_INT_STA_MASK;
	writel(pending_bit, base_addr + SPI_INT_STA_REG);
}

/* query txfifo bytes */
static u32 spi_query_txfifo(void __iomem *base_addr)
{
	u32 reg_val = (SPI_FIFO_STA_TX_CNT & readl(base_addr + SPI_FIFO_STA_REG));

	reg_val >>= SPI_TXCNT_BIT_POS;
	return reg_val;
}

/* query rxfifo bytes */
static u32 spi_query_rxfifo(void __iomem *base_addr)
{
	u32 reg_val = (SPI_FIFO_STA_RX_CNT & readl(base_addr + SPI_FIFO_STA_REG));

	reg_val >>= SPI_RXCNT_BIT_POS;
	return reg_val;
}

/* reset fifo */
static void spi_reset_fifo(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG);

	reg_val |= (SPI_FIFO_CTL_RX_RST|SPI_FIFO_CTL_TX_RST);
	/* Set the trigger level of RxFIFO/TxFIFO. */
	reg_val &= ~(SPI_FIFO_CTL_RX_LEVEL|SPI_FIFO_CTL_TX_LEVEL);
	reg_val |= (0x20<<16) | 0x20;
	writel(reg_val, base_addr + SPI_FIFO_CTL_REG);
}

static void spi_set_rx_trig(u32 val, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_FIFO_CTL_REG);

	reg_val &= ~SPI_FIFO_CTL_RX_LEVEL;
	reg_val |= val & SPI_FIFO_CTL_RX_LEVEL;
	writel(reg_val, base_addr + SPI_FIFO_CTL_REG);

}

/* set transfer total length BC, transfer length TC and single transmit length STC */
static void spi_set_bc_tc_stc(u32 tx_len, u32 rx_len, u32 stc_len, u32 dummy_cnt, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_BURST_CNT_REG);

	/* set MBC(0x30) = tx_len + rx_len + dummy_cnt */
	reg_val &= ~SPI_BC_CNT_MASK;
	reg_val |= (SPI_BC_CNT_MASK & (tx_len + rx_len + dummy_cnt));
	writel(reg_val, base_addr + SPI_BURST_CNT_REG);

	/* set MTC(0x34) = tx_len */
	reg_val = readl(base_addr + SPI_TRANSMIT_CNT_REG);
	reg_val &= ~SPI_TC_CNT_MASK;
	reg_val |= (SPI_TC_CNT_MASK & tx_len);
	writel(reg_val, base_addr + SPI_TRANSMIT_CNT_REG);

	/* set BBC(0x38) = dummy cnt & single mode transmit counter */
	reg_val = readl(base_addr + SPI_BCC_REG);
	reg_val &= ~SPI_BCC_STC_MASK;
	reg_val |= (SPI_BCC_STC_MASK & stc_len);
	reg_val &= ~(0xf << 24);
	reg_val |= (dummy_cnt << 24);
	writel(reg_val, base_addr + SPI_BCC_REG);
}

/* set ss c
 * sunxi_spi_ss_ctrl : software control or spi controller control
 * owner = 1 : software contorl
 * owner = 0 : spi controller control
 * */
static void sunxi_spi_ss_ctrl(void __iomem *base_addr, bool owner)
{
	u32 reg_val = readl(base_addr + SPI_TC_REG);

	owner &= 0x1;
	if (owner)
		reg_val |= SPI_TC_SS_OWNER;
	else
		reg_val &= ~SPI_TC_SS_OWNER;
	writel(reg_val, base_addr + SPI_TC_REG);
}

/* set dhb, 1: discard unused spi burst; 0: receiving all spi burst */
static void spi_set_all_burst_received(void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr+SPI_TC_REG);

	reg_val &= ~SPI_TC_DHB;
	writel(reg_val, base_addr + SPI_TC_REG);
}

static void spi_disable_dual(void __iomem  *base_addr)
{
	u32 reg_val = readl(base_addr+SPI_BCC_REG);
	reg_val &= ~SPI_BCC_DUAL_MODE;
	writel(reg_val, base_addr + SPI_BCC_REG);
}

static void spi_enable_dual(void __iomem  *base_addr)
{
	u32 reg_val = readl(base_addr+SPI_BCC_REG);
	reg_val &= ~SPI_BCC_QUAD_MODE;
	reg_val |= SPI_BCC_DUAL_MODE;
	writel(reg_val, base_addr + SPI_BCC_REG);
}

static void spi_disable_quad(void __iomem  *base_addr)
{
	u32 reg_val = readl(base_addr+SPI_BCC_REG);

	reg_val &= ~SPI_BCC_QUAD_MODE;
	writel(reg_val, base_addr + SPI_BCC_REG);
}

static void spi_enable_quad(void __iomem  *base_addr)
{
	u32 reg_val = readl(base_addr+SPI_BCC_REG);

	reg_val |= SPI_BCC_QUAD_MODE;
	writel(reg_val, base_addr + SPI_BCC_REG);
}
static int spi_regulator_request(struct sunxi_spi_platform_data *pdata,
			struct device *dev)
{
	struct regulator *regu = NULL;

	if (pdata->regulator != NULL)
		return 0;

	regu = devm_regulator_get(dev, "spi");
	if (IS_ERR(regu)) {
		SPI_ERR("%s: spi get supply failed!\n", __func__);
		return -1;
	}

	pdata->regulator = regu;
	return 0;
}

static int spi_regulator_enable(struct sunxi_spi_platform_data *pdata)
{
	if (pdata->regulator == NULL)
		return 0;

	if (regulator_enable(pdata->regulator) != 0) {
		SPI_ERR("enable regulator %s failed!\n", pdata->regulator_id);
		return -1;
	}
	return 0;
}

static int spi_regulator_disable(struct sunxi_spi_platform_data *pdata)
{
	if (pdata->regulator == NULL)
		return 0;

	if (regulator_disable(pdata->regulator) != 0) {
		SPI_ERR("enable regulator %s failed!\n", pdata->regulator_id);
		return -1;
	}
	return 0;
}

#if IS_ENABLED(CONFIG_DMA_ENGINE)

/* ------------------------------- dma operation start----------------------- */
/* dma full done callback for spi rx */
static void sunxi_spi_dma_cb_rx(void *data)
{
	struct sunxi_spi *sspi = (struct sunxi_spi *)data;
	unsigned long flags = 0;
	void __iomem *base_addr = sspi->base_addr;

	spin_lock_irqsave(&sspi->lock, flags);
	dprintk(DEBUG_INFO, "[spi%d] dma read data end\n", sspi->master->bus_num);

	if (spi_query_rxfifo(base_addr) > 0) {
		SPI_ERR("[spi%d] DMA end, but RxFIFO isn't empty! FSR: %#x\n",
			sspi->master->bus_num, spi_query_rxfifo(base_addr));
		sspi->result = -1; /* failed */
	} else {
		sspi->result = 0;
	}

	complete(&sspi->done);
	spin_unlock_irqrestore(&sspi->lock, flags);
}

/* dma full done callback for spi tx */
static void sunxi_spi_dma_cb_tx(void *data)
{
	struct sunxi_spi *sspi = (struct sunxi_spi *)data;
	unsigned long flags = 0;

	spin_lock_irqsave(&sspi->lock, flags);
	dprintk(DEBUG_INFO, "[spi%d] dma write data end\n", sspi->master->bus_num);
	spin_unlock_irqrestore(&sspi->lock, flags);
}

static int sunxi_spi_dmg_sg_cnt(void *addr, int len)
{
	int npages = 0;
	char *bufp = (char *)addr;
	int mapbytes = 0;
	int bytesleft = len;

	while (bytesleft > 0) {
		if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
			mapbytes = bytesleft;
		else
			mapbytes = PAGE_SIZE - offset_in_page(bufp);

		npages++;
		bufp += mapbytes;
		bytesleft -= mapbytes;
	}
	return npages;
}

static int sunxi_spi_dma_init_sg(spi_dma_info_t *info, void *addr,
				 int len)
{
	int i;
	int npages = 0;
	void *bufp = addr;
	int mapbytes = 0;
	int bytesleft = len;

	npages = sunxi_spi_dmg_sg_cnt(addr, len);
	WARN_ON(npages == 0);
	dprintk(DEBUG_INFO, "npages = %d, len = %d\n", npages, len);
	if (npages > SPI_MAX_PAGES)
		npages = SPI_MAX_PAGES;

	sg_init_table(info->sg, npages);
	for (i = 0; i < npages; i++) {
		/* If there are less bytes left than what fits
		 * in the current page (plus page alignment offset)
		 * we just feed in this, else we stuff in as much
		 * as we can.
		 */
		if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
			mapbytes = bytesleft;
		else
			mapbytes = PAGE_SIZE - offset_in_page(bufp);

		dprintk(DEBUG_INFO, "%d: len %d, offset %ld, addr %p(%d)\n", i, mapbytes,
			offset_in_page(bufp), bufp, virt_addr_valid(bufp));
		if (virt_addr_valid(bufp))
			sg_set_page(&info->sg[i], virt_to_page(bufp),
				    mapbytes, offset_in_page(bufp));
		else
			sg_set_page(&info->sg[i], vmalloc_to_page(bufp),
				    mapbytes, offset_in_page(bufp));

		bufp += mapbytes;
		bytesleft -= mapbytes;
	}

	WARN_ON(bytesleft);
	info->nents = npages;
	return 0;
}

/* request dma channel and set callback function */
static int sunxi_spi_prepare_dma(struct device *dev, spi_dma_info_t *_info,
				enum spi_dma_dir _dir, const char *name)
{
	dprintk(DEBUG_INFO, "Init DMA, dir %d\n", _dir);

	if (_info->chan == NULL) {
		_info->chan = dma_request_chan(dev, name);
		if (IS_ERR(_info->chan)) {
			SPI_ERR("Request DMA(dir %d) failed!\n", _dir);
			return -EINVAL;
		}
	}

	_info->dir = _dir;
	return 0;
}

static int sunxi_spi_config_dma_rx(struct sunxi_spi *sspi, struct spi_transfer *t)
{
	int ret = 0;
	int nents = 0;
	struct dma_slave_config dma_conf = {0};
	struct dma_async_tx_descriptor *dma_desc = NULL;
	unsigned int i, j;
	u8 buf[64], cnt = 0;

	if (debug_mask & DEBUG_INFO3) {
		dprintk(DEBUG_INIT, "t->len = %d\n", t->len);
		if (debug_mask & DEBUG_DATA) {
			for (i = 0; i < t->len; i += 16) {
				cnt = 0;
				cnt += sprintf(buf + cnt, "%03x: ", i);
				for (j = 0; ((i + j) < t->len) && (j < 16); j++)
					cnt += sprintf(buf + cnt, "%02x ",
							((unsigned char *)(t->rx_buf))[i+j]);
				pr_warn("%s\n", buf);
			}
		}
	}

	ret = sunxi_spi_dma_init_sg(&sspi->dma_rx, t->rx_buf, t->len);
	if (ret != 0)
		return ret;

	dma_conf.direction = DMA_DEV_TO_MEM;
	dma_conf.src_addr = sspi->base_addr_phy + SPI_RXDATA_REG;
	if (t->len%DMA_SLAVE_BUSWIDTH_4_BYTES) {
		dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	} else {
		dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	}
	dma_conf.src_maxburst = 4;
	dma_conf.dst_maxburst = 4;
	dmaengine_slave_config(sspi->dma_rx.chan, &dma_conf);

	nents = dma_map_sg(&sspi->pdev->dev, sspi->dma_rx.sg,
			   sspi->dma_rx.nents, DMA_FROM_DEVICE);
	if (!nents) {
		SPI_ERR("[spi%d] dma_map_sg(%d) failed! return %d\n",
				sspi->master->bus_num, sspi->dma_rx.nents, nents);
		return -ENOMEM;
	}
	dprintk(DEBUG_INFO, "[spi%d] npages = %d, nents = %d\n",
			sspi->master->bus_num, sspi->dma_rx.nents, nents);

	dma_desc = dmaengine_prep_slave_sg(sspi->dma_rx.chan, sspi->dma_rx.sg,
					   nents, DMA_DEV_TO_MEM,
					   DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
	if (!dma_desc) {
		SPI_ERR("[spi%d] dmaengine_prep_slave_sg() failed!\n",
				sspi->master->bus_num);
		dma_unmap_sg(&sspi->pdev->dev, sspi->dma_rx.sg,
			     sspi->dma_rx.nents, DMA_FROM_DEVICE);
		return -1;
	}

	dma_desc->callback = sunxi_spi_dma_cb_rx;
	dma_desc->callback_param = (void *)sspi;
	dmaengine_submit(dma_desc);

	return 0;
}

static int sunxi_spi_config_dma_tx(struct sunxi_spi *sspi, struct spi_transfer *t)
{
	int ret = 0;
	int nents = 0;
	struct dma_slave_config dma_conf = {0};
	struct dma_async_tx_descriptor *dma_desc = NULL;
	unsigned int i, j;
	u8 buf[64], cnt = 0;

	if (debug_mask & DEBUG_INFO4) {
		dprintk(DEBUG_INIT, "t->len = %d\n", t->len);
		if (debug_mask & DEBUG_DATA) {
			for (i = 0; i < t->len; i += 16) {
				cnt = 0;
				cnt += sprintf(buf + cnt, "%03x: ", i);
				for (j = 0; ((i + j) < t->len) && (j < 16); j++)
					cnt += sprintf(buf + cnt, "%02x ",
							((unsigned char *)(t->tx_buf))[i+j]);
				pr_warn("%s\n", buf);
			}
		}
	}

	ret = sunxi_spi_dma_init_sg(&sspi->dma_tx, (void *)t->tx_buf,
				    t->len);
	if (ret != 0)
		return ret;

	dma_conf.direction = DMA_MEM_TO_DEV;
	dma_conf.dst_addr = sspi->base_addr_phy + SPI_TXDATA_REG;
	if (t->len%DMA_SLAVE_BUSWIDTH_4_BYTES) {
		dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	} else {
		dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	}
	dma_conf.src_maxburst = 4;
	dma_conf.dst_maxburst = 4;
	dmaengine_slave_config(sspi->dma_tx.chan, &dma_conf);

	nents = dma_map_sg(&sspi->pdev->dev, sspi->dma_tx.sg, sspi->dma_tx.nents, DMA_TO_DEVICE);
	if (!nents) {
		SPI_ERR("[spi%d] dma_map_sg(%d) failed! return %d\n",
				sspi->master->bus_num, sspi->dma_tx.nents, nents);
		return -ENOMEM;
	}
	dprintk(DEBUG_INFO, "[spi%d] npages = %d, nents = %d\n",
			sspi->master->bus_num, sspi->dma_tx.nents, nents);

	dma_desc = dmaengine_prep_slave_sg(sspi->dma_tx.chan, sspi->dma_tx.sg,
					   nents, DMA_MEM_TO_DEV,
					   DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
	if (!dma_desc) {
		SPI_ERR("[spi%d] dmaengine_prep_slave_sg() failed!\n",
				sspi->master->bus_num);
		dma_unmap_sg(&sspi->pdev->dev, sspi->dma_tx.sg,
			     sspi->dma_tx.nents, DMA_TO_DEVICE);
		return -1;
	}

	dma_desc->callback = sunxi_spi_dma_cb_tx;
	dma_desc->callback_param = (void *)sspi;
	dmaengine_submit(dma_desc);
	return 0;
}

/* config dma src and dst address,
 * io or linear address,
 * drq type,
 * then enqueue
 * but not trigger dma start
 */
static int sunxi_spi_config_dma(struct sunxi_spi *sspi, enum spi_dma_dir dma_dir, struct spi_transfer *t)
{
	if (dma_dir == SPI_DMA_RDEV)
		return sunxi_spi_config_dma_rx(sspi, t);
	else
		return sunxi_spi_config_dma_tx(sspi, t);
}

/* set dma start flag, if queue, it will auto restart to transfer next queue */
static int sunxi_spi_start_dma(spi_dma_info_t *_info)
{
	dma_async_issue_pending(_info->chan);
	return 0;
}

/* Unmap and free the SG tables */
static void sunxi_spi_dma_free_sg(struct sunxi_spi *sspi, spi_dma_info_t *info)
{
	if (info->dir == SPI_DMA_RWNULL)
		return;

	dma_unmap_sg(&sspi->pdev->dev, info->sg, info->nents, (enum dma_data_direction)info->dir);
	info->dir = SPI_DMA_RWNULL;

	/* Never release the DMA channel. Duanmintao
	 * dma_release_channel(info->chan);
	 * info->chan = NULL;
	 */
}

/* release dma channel, and set queue status to idle. */
static int sunxi_spi_release_dma(struct sunxi_spi *sspi, struct spi_transfer *t)
{
	unsigned long flags = 0;

	spin_lock_irqsave(&sspi->lock, flags);

	sunxi_spi_dma_free_sg(sspi, &sspi->dma_rx);
	sunxi_spi_dma_free_sg(sspi, &sspi->dma_tx);

	spin_unlock_irqrestore(&sspi->lock, flags);
	return 0;
}
#endif

/* sunxi_spi_set_cs : spi control set cs to connect device
 * enable : 1, working mode : set ss to connect device
 * enable : 0, default mode : set ss to do not connect device
 *
 * spi controller cs mode use this funtion to set cs
 * software cs mode use kernel code to set cs
 * */
static void sunxi_spi_set_cs(struct spi_device *spi, bool enable)
{
	u32 reg_val;
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);

	sunxi_spi_ss_select(spi->chip_select, sspi->base_addr);

	reg_val = readl(sspi->base_addr + SPI_TC_REG);
	enable &= 0x01;
	if (enable)	//set cs to connect device
		reg_val |= SPI_TC_SS_LEVEL;
	else		//set cs to default mode
		reg_val &= ~SPI_TC_SS_LEVEL;
	writel(reg_val, sspi->base_addr + SPI_TC_REG);
}

/* change the properties of spi device with spi transfer.
 * every spi transfer must call this interface to update
 * the master to the excute transfer set clock.
 * return:  >= 0 : succeed;    < 0: failed.
 */
static int sunxi_spi_xfer_setup(struct spi_device *spi, struct spi_transfer *t)
{
	/* get at the setup function, the properties of spi device */
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	u32 spi_speed_hz;
	void __iomem *base_addr = sspi->base_addr;

	spi_speed_hz  = (t && t->speed_hz) ? t->speed_hz : spi->max_speed_hz;

	if (sspi->sample_delay == SAMP_MODE_DL_DEFAULT) {
		if (spi_speed_hz >= SPI_HIGH_FREQUENCY)
			spi_sample_delay(0, 1, 0, base_addr);
		else if (spi_speed_hz <= SPI_LOW_FREQUENCY)
			spi_sample_delay(1, 0, 0, base_addr);
		else
			spi_sample_delay(0, 0, 0, base_addr);
	} else {
		spi_samp_mode_enable(1, base_addr);
		spi_samp_dl_sw_status(1, base_addr);
		spi_set_sample_mode(sspi->sample_mode, base_addr);
		spi_set_sample_delay(sspi->sample_delay, base_addr);
	}

#if IS_ENABLED(CONFIG_EVB_PLATFORM)
	spi_set_clk(spi_speed_hz, clk_get_rate(sspi->mclk), sspi);
#else
	spi_set_clk(spi_speed_hz, 24000000, sspi);
#endif

	spi_config_tc(1, spi->mode, sspi->base_addr);
	return 0;
}

static int sunxi_spi_mode_check(struct sunxi_spi *sspi, struct spi_device *spi, struct spi_transfer *t)
{
	unsigned long flags = 0;

	if (sspi->mode_type != MODE_TYPE_NULL)
		return -EINVAL;

	/* full duplex */
	spin_lock_irqsave(&sspi->lock, flags);
	if (t->tx_buf && t->rx_buf) {
		spi_set_all_burst_received(sspi->base_addr);
		spi_set_bc_tc_stc(t->len, 0, t->len, 0, sspi->base_addr);
		sspi->mode_type = SINGLE_FULL_DUPLEX_RX_TX;
		dprintk(DEBUG_INFO, "[spi%d] Single mode Full duplex tx & rx\n", sspi->master->bus_num);
	} /* half duplex transmit */
	else if (t->tx_buf) {
		if (t->tx_nbits == SPI_NBITS_QUAD) {
			spi_disable_dual(sspi->base_addr);
			spi_enable_quad(sspi->base_addr);
			spi_set_bc_tc_stc(t->len, 0, 0, 0, sspi->base_addr);
			sspi->mode_type = QUAD_HALF_DUPLEX_TX;
			dprintk(DEBUG_INFO, "[spi%d] Quad mode Half duplex tx\n", sspi->master->bus_num);
		} else if (t->tx_nbits == SPI_NBITS_DUAL) {
			spi_disable_quad(sspi->base_addr);
			spi_enable_dual(sspi->base_addr);
			spi_set_bc_tc_stc(t->len, 0, 0, 0, sspi->base_addr);
			sspi->mode_type = DUAL_HALF_DUPLEX_TX;
			dprintk(DEBUG_INFO, "[spi%d] Dual mode Half duplex tx\n", sspi->master->bus_num);
		} else {
			spi_disable_quad(sspi->base_addr);
			spi_disable_dual(sspi->base_addr);
			spi_set_bc_tc_stc(t->len, 0, t->len, 0, sspi->base_addr);
			sspi->mode_type = SINGLE_HALF_DUPLEX_TX;
			dprintk(DEBUG_INFO, "[spi%d] Single mode Half duplex tx\n", sspi->master->bus_num);
		}
	} /* half duplex receive */
	else if (t->rx_buf) {
		if (t->rx_nbits == SPI_NBITS_QUAD) {
			spi_disable_dual(sspi->base_addr);
			spi_enable_quad(sspi->base_addr);
			spi_set_bc_tc_stc(0, t->len, 0, 0, sspi->base_addr);
			sspi->mode_type = QUAD_HALF_DUPLEX_RX;
			dprintk(DEBUG_INFO, "[spi%d] Quad mode Half duplex rx\n", sspi->master->bus_num);
		} else if (t->rx_nbits == SPI_NBITS_DUAL) {
			spi_disable_quad(sspi->base_addr);
			spi_enable_dual(sspi->base_addr);
			spi_set_bc_tc_stc(0, t->len, 0, 0, sspi->base_addr);
			sspi->mode_type = DUAL_HALF_DUPLEX_RX;
			dprintk(DEBUG_INFO, "[spi%d] Dual mode Half duplex rx\n", sspi->master->bus_num);
		} else {
			spi_disable_quad(sspi->base_addr);
			spi_disable_dual(sspi->base_addr);
			spi_set_bc_tc_stc(0, t->len, 0, 0, sspi->base_addr);
			sspi->mode_type = SINGLE_HALF_DUPLEX_RX;
			dprintk(DEBUG_INFO, "[spi%d] Single mode Half duplex rx\n", sspi->master->bus_num);
		}
	}
	spin_unlock_irqrestore(&sspi->lock, flags);

	return 0;

}

static int sunxi_spi_cpu_readl(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned rx_len = t->len;	/* number of bytes sent */
	unsigned char *rx_buf = (unsigned char *)t->rx_buf;
	unsigned int poll_time = 0x7ffffff;
	unsigned int i, j;
	u8 buf[64], cnt = 0;

	while (rx_len) {
	/* rxFIFO counter */
		if (spi_query_rxfifo(base_addr) && (--poll_time > 0)) {
			*rx_buf++ =  readb(base_addr + SPI_RXDATA_REG);
			--rx_len;
		}
	}
	if (poll_time <= 0) {
		SPI_ERR("[spi%d] cpu receive data time out!\n", sspi->master->bus_num);
		return -1;
	}

	if (debug_mask & DEBUG_INFO1) {
		dprintk(DEBUG_INIT, "t->len = %d\n", t->len);
		if (debug_mask & DEBUG_DATA) {
			for (i = 0; i < t->len; i += 16) {
				cnt = 0;
				cnt += sprintf(buf + cnt, "%03x: ", i);
				for (j = 0; ((i + j) < t->len) && (j < 16); j++)
					cnt += sprintf(buf + cnt, "%02x ",
							((unsigned char *)(t->rx_buf))[i+j]);
				pr_warn("%s\n", buf);
			}
		}
	}

	return 0;
}

static int sunxi_spi_cpu_writel(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned long flags = 0;
#if IS_ENABLED(CONFIG_DMA_ENGINE)
	unsigned char time;
#endif
	unsigned tx_len = t->len;	/* number of bytes receieved */
	unsigned char *tx_buf = (unsigned char *)t->tx_buf;
	unsigned int poll_time = 0x7ffffff;
	unsigned int i, j;
	u8 buf[64], cnt = 0;

	if (debug_mask & DEBUG_INFO2) {
		dprintk(DEBUG_INIT, "t->len = %d\n", t->len);
		if (debug_mask & DEBUG_DATA) {
			for (i = 0; i < t->len; i += 16) {
				cnt = 0;
				cnt += sprintf(buf + cnt, "%03x: ", i);
				for (j = 0; ((i + j) < t->len) && (j < 16); j++)
					cnt += sprintf(buf + cnt, "%02x ",
							((unsigned char *)(t->tx_buf))[i+j]);
				pr_warn("%s\n", buf);
			}
		}
	}

	spin_lock_irqsave(&sspi->lock, flags);
	for (; tx_len > 0; --tx_len) {
		writeb(*tx_buf++, base_addr + SPI_TXDATA_REG);
#if IS_ENABLED(CONFIG_DMA_ENGINE)
		if (spi_query_txfifo(base_addr) >= MAX_FIFU)
			for (time = 2; 0 < time; --time)
				;
#endif
	}
	spin_unlock_irqrestore(&sspi->lock, flags);
	while (spi_query_txfifo(base_addr) && (--poll_time > 0))
		;
	if (poll_time <= 0) {
		SPI_ERR("[spi%d] cpu transfer data time out!\n", sspi->master->bus_num);
		return -1;
	}

	return 0;
}

#if IS_ENABLED(CONFIG_DMA_ENGINE)
static int sunxi_spi_dma_rx_config(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	int ret = 0;

	/* rxFIFO reday dma request enable */
	spi_enable_dma_irq(SPI_FIFO_CTL_RX_DRQEN, base_addr);
	ret = sunxi_spi_prepare_dma(&sspi->pdev->dev, &sspi->dma_rx,
				SPI_DMA_RDEV, "rx");
	if (ret < 0) {
		spi_disable_dma_irq(SPI_FIFO_CTL_RX_DRQEN, base_addr);
		spi_disable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, base_addr);
		return -EINVAL;
	}
	sunxi_spi_config_dma(sspi, SPI_DMA_RDEV, t);
	sunxi_spi_start_dma(&sspi->dma_rx);

	return ret;
}

static int sunxi_spi_dma_tx_config(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	int ret = 0;

	spi_enable_dma_irq(SPI_FIFO_CTL_TX_DRQEN, base_addr);
	ret = sunxi_spi_prepare_dma(&sspi->pdev->dev, &sspi->dma_tx,
				SPI_DMA_WDEV, "tx");
	if (ret < 0) {
		spi_disable_dma_irq(SPI_FIFO_CTL_TX_DRQEN, base_addr);
		spi_disable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, base_addr);
		return -EINVAL;
	}
	sunxi_spi_config_dma(sspi, SPI_DMA_WDEV, t);
	sunxi_spi_start_dma(&sspi->dma_tx);

	return ret;
}
static int sunxi_spi_dma_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned tx_len = t->len;	/* number of bytes receieved */
	unsigned rx_len = t->len;	/* number of bytes sent */

	switch (sspi->mode_type) {
	case SINGLE_HALF_DUPLEX_RX:
	case DUAL_HALF_DUPLEX_RX:
	case QUAD_HALF_DUPLEX_RX:
	{
		/* >64 use DMA transfer, or use cpu */
		if (t->len > BULK_DATA_BOUNDARY) {
			dprintk(DEBUG_INFO, "[spi%d] rx -> by dma\n", sspi->master->bus_num);
			/* For Rx mode, the DMA end(not TC flag) is real end. */
			spi_disable_irq(SPI_INTEN_TC, base_addr);
			sunxi_spi_dma_rx_config(spi, t);
			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
		} else {
			dprintk(DEBUG_INFO, "[spi%d] rx -> by ahb\n", sspi->master->bus_num);
			/* SMC=1,XCH trigger the transfer */
			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
			sunxi_spi_cpu_readl(spi, t);
		}
		break;
	}
	case SINGLE_HALF_DUPLEX_TX:
	case DUAL_HALF_DUPLEX_TX:
	case QUAD_HALF_DUPLEX_TX:
	{
		/* >64 use DMA transfer, or use cpu */
		if (t->len > BULK_DATA_BOUNDARY) {
			dprintk(DEBUG_INFO, "[spi%d] tx -> by dma\n", sspi->master->bus_num);
			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
			/* txFIFO empty dma request enable */
			sunxi_spi_dma_tx_config(spi, t);
		} else {
			dprintk(DEBUG_INFO, "[spi%d] tx -> by ahb\n", sspi->master->bus_num);
			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
			sunxi_spi_cpu_writel(spi, t);
		}
		break;
	}
	case SINGLE_FULL_DUPLEX_RX_TX:
	{
		/* >64 use DMA transfer, or use cpu */
		if (t->len > BULK_DATA_BOUNDARY) {
			dprintk(DEBUG_INFO, "[spi%d] rx and tx -> by dma\n", sspi->master->bus_num);
			/* For Rx mode, the DMA end(not TC flag) is real end. */
			spi_disable_irq(SPI_INTEN_TC, base_addr);
			sunxi_spi_dma_rx_config(spi, t);
			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
			sunxi_spi_dma_tx_config(spi, t);
		} else {
			dprintk(DEBUG_INFO, "[spi%d] rx and tx -> by ahb\n", sspi->master->bus_num);
			if ((rx_len == 0) || (tx_len == 0))
				return -EINVAL;

			if (!sspi->dbi_enabled)
				spi_start_xfer(base_addr);
			sunxi_spi_cpu_writel(spi, t);
			sunxi_spi_cpu_readl(spi, t);
		}
		break;
	}
	default:
		return -1;
	}

	return 0;
}
#else
static int sunxi_spi_cpu_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned tx_len = t->len;	/* number of bytes receieved */
	unsigned rx_len = t->len;	/* number of bytes sent */

	switch (sspi->mode_type) {
	case SINGLE_HALF_DUPLEX_RX:
	case DUAL_HALF_DUPLEX_RX:
	case QUAD_HALF_DUPLEX_RX:
	{
		dprintk(DEBUG_INFO, "[spi%d] rx -> by ahb\n", sspi->master->bus_num);
		/* SMC=1,XCH trigger the transfer */
		if (!sspi->dbi_enabled)
			spi_start_xfer(base_addr);
		sunxi_spi_cpu_readl(spi, t);
		break;
	}
	case SINGLE_HALF_DUPLEX_TX:
	case DUAL_HALF_DUPLEX_TX:
	case QUAD_HALF_DUPLEX_TX:
	{
		dprintk(DEBUG_INFO, "[spi%d] tx -> by ahb\n", sspi->master->bus_num);
		if (!sspi->dbi_enabled)
			spi_start_xfer(base_addr);
		sunxi_spi_cpu_writel(spi, t);
		break;
	}
	case SINGLE_FULL_DUPLEX_RX_TX:
	{
		dprintk(DEBUG_INFO, "[spi%d] rx and tx -> by ahb\n", sspi->master->bus_num);
		if ((rx_len == 0) || (tx_len == 0))
			return -EINVAL;

		if (!sspi->dbi_enabled)
			spi_start_xfer(base_addr);
		sunxi_spi_cpu_writel(spi, t);
		sunxi_spi_cpu_readl(spi, t);
		break;
	}
	default:
		return -1;
	}

	return 0;
}
#endif

/*
 * <= 64 : cpu mode transt
 * > 64  : dma mode transt
 * wait for done completion in this function, wakup in the irq hanlder
 * transt one message->transfer to slave devices
 */
static int sunxi_spi_transfer_one(struct spi_controller *master,
					struct spi_device *spi,
					struct spi_transfer *t)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned char *tx_buf = (unsigned char *)t->tx_buf;
	unsigned char *rx_buf = (unsigned char *)t->rx_buf;
	unsigned long timeout = 0;
	int ret = 0;
	static int xfer_setup;

	dprintk(DEBUG_INFO, "[spi%d] begin transfer, txbuf %p, rxbuf %p, len %d\n",
		spi->master->bus_num, tx_buf, rx_buf, t->len);
	if ((!t->tx_buf && !t->rx_buf) || !t->len)
		return -EINVAL;

	if (!xfer_setup || spi->master->bus_num) {
		if (sunxi_spi_xfer_setup(spi, t) < 0)
			return -EINVAL;
		xfer_setup = 1;
	}

	/* write 1 to clear 0 */
	spi_clr_irq_pending(SPI_INT_STA_MASK, base_addr);
#if IS_ENABLED(CONFIG_DMA_ENGINE)
	/* disable all DRQ */
	spi_disable_dma_irq(SPI_FIFO_CTL_DRQEN_MASK, base_addr);
#endif
	/* reset tx/rx fifo */
	//spi_reset_fifo(base_addr);

	if (sunxi_spi_mode_check(sspi, spi, t))
		return -EINVAL;

	if (sspi->dbi_enabled) {
		spi_config_dbi(sspi, spi);
#if IS_ENABLED(CONFIG_DMA_ENGINE)
		spi_enable_dbi_dma(base_addr);
#endif
	} else {
		/* reset tx/rx fifo */
		spi_reset_fifo(base_addr);
		/*	1. Tx/Rx error irq,process in IRQ;
			2. Transfer Complete Interrupt Enable
		*/
		spi_enable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, base_addr);
	}

	if ((debug_mask & DEBUG_INIT) && (debug_mask & DEBUG_DATA)) {
		dprintk(DEBUG_DATA, "[spi%d] dump reg:\n", sspi->master->bus_num);
		spi_dump_reg(sspi, 0, 0x40);
	}

#if IS_ENABLED(CONFIG_DMA_ENGINE)
	sunxi_spi_dma_transfer(spi, t);
#else
	sunxi_spi_cpu_transfer(spi, t);
#endif

	if ((debug_mask & DEBUG_INIT) && (debug_mask & DEBUG_DATA)) {
		dprintk(DEBUG_DATA, "[spi%d] dump reg:\n", sspi->master->bus_num);
		spi_dump_reg(sspi, 0, 0x40);
	}

	/* wait for xfer complete in the isr. */
	timeout = wait_for_completion_timeout(
				&sspi->done,
				msecs_to_jiffies(XFER_TIMEOUT));
	if (timeout == 0) {
		SPI_ERR("[spi%d] xfer timeout\n", spi->master->bus_num);
		ret = -1;
	} else if (sspi->result < 0) {
		SPI_ERR("[spi%d] xfer failed...\n", spi->master->bus_num);
		ret = -1;
	}

#if IS_ENABLED(CONFIG_DMA_ENGINE)
	/* release dma resource if necessary */
	sunxi_spi_release_dma(sspi, t);

	if (sspi->dbi_enabled)
		spi_disable_dbi_dma(base_addr);
#endif

	if (sspi->mode_type != MODE_TYPE_NULL)
		sspi->mode_type = MODE_TYPE_NULL;

	return ret;
}
#ifdef CONFIG_AW_MTD_SPINAND
/* tx_len : all data to transfer(single io tx data + quad io tx data)
 * stc_len: single io tx data*/
static void spi_set_bc_tc_stc2(u32 tx_len, u32 rx_len, u32 stc_len, u8 nbits, void __iomem *base_addr)
{
	u32 reg_val = readl(base_addr + SPI_BURST_CNT_REG);
	reg_val &= ~SPI_BC_CNT_MASK;
	reg_val |= (SPI_BC_CNT_MASK & (tx_len + rx_len));
	writel(reg_val, base_addr + SPI_BURST_CNT_REG);
	//SPI_DBG("\n-- BC = %d --\n", readl(base_addr + SPI_BURST_CNT_REG));

	reg_val = readl(base_addr + SPI_TRANSMIT_CNT_REG);
	reg_val &= ~SPI_TC_CNT_MASK;
	reg_val |= (SPI_TC_CNT_MASK & tx_len);
	writel(reg_val, base_addr + SPI_TRANSMIT_CNT_REG);
	//SPI_DBG("\n-- TC = %d --\n", readl(base_addr + SPI_TRANSMIT_CNT_REG));

	reg_val = readl(base_addr + SPI_BCC_REG);
	reg_val &= ~SPI_BCC_STC_MASK;
	reg_val |= (SPI_BCC_STC_MASK & stc_len);
	if (nbits == 2)
		reg_val |= SPI_BCC_DUAL_MODE;
	else
		reg_val &= ~SPI_BCC_DUAL_MODE;

	if (nbits == 4)
		reg_val |= SPI_BCC_QUAD_MODE;
	else
		reg_val &= ~SPI_BCC_QUAD_MODE;

	writel(reg_val, base_addr + SPI_BCC_REG);
	//SPI_DBG("\n-- STC = %d --\n", readl(base_addr + SPI_BCC_REG));
}


static int sunxi_spi_xfer_tx_rx(struct spi_device *spi, struct spi_transfer *tx, struct spi_transfer *rx)
{
#define SPI_FIFO_SIZE (64)
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	void __iomem *base_addr = sspi->base_addr;
	unsigned int xcnt = 0;
	unsigned int poll_time = 0;
	int ret = 0;

	unsigned tcnt = tx->len;
	unsigned rcnt = rx->len;

	char *txbuf = (char *)tx->tx_buf;
	char *rxbuf = (char *)rx->rx_buf;

	u8 nbits = 0;

	if (rx->rx_nbits == SPI_NBITS_DUAL)
		nbits = 2;
	else if (rx->rx_nbits == SPI_NBITS_QUAD)
		nbits = 4;
	else
		nbits = 1;


	spi_disable_irq(SPI_INTEN_MASK, base_addr);

	/* write 1 to clear 0 */
	spi_clr_irq_pending(SPI_INT_STA_MASK, base_addr);

	spi_set_bc_tc_stc2(tcnt, rcnt, tcnt, nbits, base_addr);

	/*
	* 1. Tx/Rx error irq,process in IRQ;
	* 2. Transfer Complete Interrupt Enable
	*/
	spi_enable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, base_addr);

	spi_start_xfer(base_addr);

	if (tcnt) {

		/* >64 use DMA transfer, or use cpu */
		if (tcnt <= BULK_DATA_BOUNDARY) {
			xcnt = 0;
			poll_time = 0xfffff;
			dprintk(DEBUG_DATA, "[spi-%d]xfer2 tx --> by ahb\n", spi->master->bus_num);
			while (xcnt < tcnt) {
				while (((readl(base_addr + SPI_FIFO_STA_REG) >> 16) & 0x7f) >= SPI_FIFO_SIZE) {
					if (--poll_time < 0)
						return -ETIMEDOUT;
				}
				writeb(*(txbuf + xcnt), (base_addr + SPI_TXDATA_REG));
				xcnt++;
			}

		} else {
			dprintk(DEBUG_DATA, "[spi-%d]xfer2 tx -> by dma\n", spi->master->bus_num);
			/* txFIFO empty dma request enable */
			sunxi_spi_dma_tx_config(spi, tx);

		}
	}

	if (rcnt) {
		if (rcnt <= BULK_DATA_BOUNDARY) {
			xcnt = 0;
			poll_time = 0xfffff;
			dprintk(DEBUG_DATA, "[spi-%d]xfer2 rx --> by ahb\n", spi->master->bus_num);
			while (xcnt < rcnt) {
				if (((readl(base_addr + SPI_FIFO_STA_REG)) & 0x7f) && (--poll_time > 0)) {
					*(rxbuf + xcnt) = readb((base_addr + SPI_RXDATA_REG));
					xcnt++;
				}
			}
			if (poll_time <= 0) {
				SPI_ERR("cpu receive data timeout!\n");
				return -ETIMEDOUT;
			}
		} else {
			dprintk(DEBUG_INFO, "[spi-%d]xfer2 rx -> by dma\n", spi->master->bus_num);

			/* For Rx mode, the DMA end(not TC flag) is real end. */
			spi_disable_irq(SPI_INTEN_TC, base_addr);
			sunxi_spi_dma_rx_config(spi, rx);
		}
	}

	return ret;
}

/*
 * <= 64 : cpu ;  > 64 : dma
 * wait for done completion in this function, wakup in the irq hanlder
 */
static int sunxi_spi_transfer_two(struct spi_master *master, struct spi_device *spi,
			    struct spi_transfer *t, struct spi_transfer *t2)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);
	unsigned long timeout = 0;
	int ret = 0;
	static int xfer_setup;

	if (!xfer_setup || spi->master->bus_num) {
		if (sunxi_spi_xfer_setup(spi, t) < 0)
			return -EINVAL;
		xfer_setup = 1;
	}

	if (t->tx_buf && t2->rx_buf)
		sunxi_spi_xfer_tx_rx(spi, t, t2);
	else {

		SPI_ERR("[spi%d] begin transfer, t1: txbuf %p, rxbuf %p, len %d t2:  txbuf %p, rxbuf %p, len %d t2:\n",
		spi->master->bus_num, t->tx_buf, t->rx_buf, t->len, t2->tx_buf, t2->rx_buf, t2->len);
		SPI_ERR("[spi%d] xfer mode not support\n", spi->master->bus_num);
		return -EINVAL;
	}


	if ((debug_mask & DEBUG_INIT) && (debug_mask & DEBUG_DATA)) {
		dprintk(DEBUG_DATA, "[spi%d] dump reg:\n", sspi->master->bus_num);
		spi_dump_reg(sspi, 0, 0x40);
	}

	/* wait for xfer complete in the isr. */
	timeout = wait_for_completion_timeout(
				&sspi->done,
				msecs_to_jiffies(XFER_TIMEOUT));
	if (timeout == 0) {
		SPI_ERR("[spi%d] xfer timeout\n", spi->master->bus_num);
		ret = -1;
	} else if (sspi->result < 0) {
		SPI_ERR("[spi%d] xfer failed...\n", spi->master->bus_num);
		ret = -1;
	}

	if (sspi->mode_type != MODE_TYPE_NULL)
		sspi->mode_type = MODE_TYPE_NULL;

	/*
	 *if (sspi->stx.state == TRANSFER_STATE) {
	 *        sunxi_spi_unmap_sg(spi->master, &sspi->stx.tx);
	 *        sspi->stx.state = INIT_STATE;
	 *}
	 */

	return ret;
}



/*
 * sunxi spi flash_transfer_one_message - Default implementation of transfer_one_message()
 *
 * This is a standard implementation of transfer_one_message() for
 * drivers which implement a transfer_one() operation.  It provides
 * standard handling of delays and chip select management.
 */
static int sunxi_spi_transfer_one_message(struct spi_master *master,
				    struct spi_message *msg)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(master);
	void __iomem *base_addr = sspi->base_addr;
	struct spi_transfer *xfer;
	struct spi_transfer *cur_xfer = NULL;
	struct spi_transfer *prev_xfer = NULL;
	int xfer_cnt = 0;
	int xfer_n = 0;
	int ret = 0;
	struct spi_statistics *statm = &master->statistics;
	struct spi_statistics *stats = &msg->spi->statistics;


	SPI_STATISTICS_INCREMENT_FIELD(statm, messages);
	SPI_STATISTICS_INCREMENT_FIELD(stats, messages);


	list_for_each_entry(xfer, &msg->transfers, transfer_list) {

		spi_statistics_add_transfer_stats(statm, xfer, master);
		spi_statistics_add_transfer_stats(stats, xfer, master);

		xfer_cnt++;
		cur_xfer = xfer;

		if (prev_xfer && prev_xfer->tx_buf && !prev_xfer->rx_buf &&
				cur_xfer && cur_xfer->rx_buf && !cur_xfer->tx_buf) {
			/*tx->rx*/
			reinit_completion(&master->xfer_completion);

			ret = master->transfer_two(master, msg->spi, prev_xfer, cur_xfer);
			if (ret < 0) {
				SPI_STATISTICS_INCREMENT_FIELD(statm, errors);
				SPI_STATISTICS_INCREMENT_FIELD(stats, errors);
				SPI_ERR("[spi%d] SPI transfer failed: %d\n", sspi->master->bus_num, ret);
				goto out;
			}

			if (msg->status != -EINPROGRESS)
				goto out;

			msg->actual_length += prev_xfer->len;
			msg->actual_length += cur_xfer->len;
			prev_xfer = NULL;
			cur_xfer = NULL;
			xfer_cnt = 0;

		} else if (!prev_xfer) {
			prev_xfer = xfer;

		} else {
			/*single handle*/

			sunxi_spi_ss_ctrl(base_addr, true);
			master->set_cs(msg->spi, false);
			for (xfer_n = 0; xfer_n < xfer_cnt; xfer_n++) {
				if (xfer_n == 0)
					xfer = prev_xfer;
				else
					xfer = cur_xfer;

				reinit_completion(&master->xfer_completion);

				ret = master->transfer_one(master, msg->spi, xfer);
				if (ret < 0) {
					SPI_STATISTICS_INCREMENT_FIELD(statm,
							errors);
					SPI_STATISTICS_INCREMENT_FIELD(stats,
							errors);
					SPI_ERR("[spi%d] SPI transfer failed: %d\n", sspi->master->bus_num, ret);
					goto out;
				}

				if (msg->status != -EINPROGRESS)
					goto out;

				msg->actual_length += xfer->len;

			}

			master->set_cs(msg->spi, true);
			sunxi_spi_ss_ctrl(base_addr, false);
		}
	}

	/*do last xfer*/
	{
		if (prev_xfer && prev_xfer == cur_xfer) {
			reinit_completion(&master->xfer_completion);

			ret = master->transfer_one(master, msg->spi, cur_xfer);
			if (ret < 0) {
				SPI_STATISTICS_INCREMENT_FIELD(statm,
						errors);
				SPI_STATISTICS_INCREMENT_FIELD(stats,
						errors);
				SPI_ERR("[spi%d] SPI transfer failed: %d\n", sspi->master->bus_num, ret);
				goto out;
			}

			if (msg->status != -EINPROGRESS)
				goto out;

			msg->actual_length += cur_xfer->len;
			prev_xfer = NULL;
			cur_xfer = NULL;
			xfer_cnt = 0;
		}
	}

out:

	if (msg->status == -EINPROGRESS)
		msg->status = ret;

	if (msg->status && master->handle_err)
		master->handle_err(master, msg);

	spi_res_release(master, msg);

	spi_finalize_current_message(master);

	return ret;
}
#endif

/* wake up the sleep thread, and give the result code */
static irqreturn_t sunxi_spi_handler(int irq, void *dev_id)
{
	struct sunxi_spi *sspi = (struct sunxi_spi *)dev_id;
	void __iomem *base_addr = sspi->base_addr;
	unsigned int status = 0, enable = 0;
	unsigned long flags = 0;

	spin_lock_irqsave(&sspi->lock, flags);

	enable = spi_qry_irq_enable(base_addr);
	status = spi_qry_irq_pending(base_addr);
	spi_clr_irq_pending(status, base_addr);
	dprintk(DEBUG_INFO, "[spi%d] irq status = %x\n", sspi->master->bus_num, status);

	sspi->result = 0; /* assume succeed */

	if (sspi->mode) {
		if ((enable & SPI_INTEN_RX_RDY) && (status & SPI_INT_STA_RX_RDY)) {
			dprintk(DEBUG_INFO, "[spi%d] spi data is ready\n", sspi->master->bus_num);
			spi_disable_irq(SPI_INT_STA_RX_RDY, base_addr);
			wake_up_process(sspi->task);
			spin_unlock_irqrestore(&sspi->lock, flags);
			return IRQ_HANDLED;
		}
	}

	/* master mode, Transfer Complete Interrupt */
	if (status & SPI_INT_STA_TC) {
		dprintk(DEBUG_INFO, "[spi%d] SPI TC comes\n", sspi->master->bus_num);
		spi_disable_irq(SPI_INT_STA_TC | SPI_INT_STA_ERR, base_addr);

		/*wakup uplayer, by the sem */
		complete(&sspi->done);
		spin_unlock_irqrestore(&sspi->lock, flags);
		return IRQ_HANDLED;
	} else if (status & SPI_INT_STA_ERR) { /* master mode:err */
		SPI_ERR("[spi%d]  SPI ERR %#x comes\n", sspi->master->bus_num, status);
		/* error process, release dma in the workqueue,should not be here */
		spi_disable_irq(SPI_INT_STA_TC | SPI_INT_STA_ERR, base_addr);
		spi_soft_reset(base_addr);
		sspi->result = -1;
		complete(&sspi->done);
		spin_unlock_irqrestore(&sspi->lock, flags);
		return IRQ_HANDLED;
	}
	if (sspi->dbi_enabled) {
		status = dbi_qry_irq_pending(base_addr);
		dbi_clr_irq_pending(status, base_addr);
		dprintk(DEBUG_INFO, "[dbi%d] irq status = %x\n",
				sspi->master->bus_num, status);
		if ((status & DBI_INT_FIFO_EMPTY) && !(sspi->dbi_config->dbi_mode
					& SPI_DBI_TRANSMIT_VIDEO_)) {
			dprintk(DEBUG_INFO, "[spi%d] DBI Fram TC comes\n",
					sspi->master->bus_num);
			dbi_disable_irq(DBI_FIFO_EMPTY_INT_EN, base_addr);
			/*wakup uplayer, by the sem */
			complete(&sspi->done);
			spin_unlock_irqrestore(&sspi->lock, flags);
			return IRQ_HANDLED;
		} else if (((status & DBI_INT_TE_INT) ||
			    (status & DBI_INT_STA_FRAME)) &&
			   (sspi->dbi_config->dbi_mode & SPI_DBI_TRANSMIT_VIDEO_)) {
			if (sspi->dbi_config->dbi_vsync_handle &&
			    (status & DBI_INT_TE_INT))
				sspi->dbi_config->dbi_vsync_handle(
				    (unsigned long)sspi->spi);
			else
				dbi_disable_irq(DBI_FRAM_DONE_INT_EN, base_addr);
			complete(&sspi->done);
			spin_unlock_irqrestore(&sspi->lock, flags);
			return IRQ_HANDLED;
		} else {
			//TODO: Adapt to other states
			spin_unlock_irqrestore(&sspi->lock, flags);
			return IRQ_HANDLED;
		}
	}
	dprintk(DEBUG_INFO, "[spi%d] SPI NONE comes\n", sspi->master->bus_num);
	spin_unlock_irqrestore(&sspi->lock, flags);
	return IRQ_NONE;
}

static int sunxi_spi_setup(struct spi_device *spi)
{
	struct sunxi_spi *sspi = spi_master_get_devdata(spi->master);

	sspi->spi = spi;

	if (sunxi_spi_xfer_setup(spi, NULL) < 0)
		SPI_ERR("failed to xfer setup\n");

	return 0;
}

static bool sunxi_spi_can_dma(struct spi_master *master, struct spi_device *spi,
				 struct spi_transfer *xfer)
{
	return (xfer->len > BULK_DATA_BOUNDARY);
}

static int sunxi_spi_slave_cpu_tx_config(struct sunxi_spi *sspi)
{
	int ret = 0, i;
	u32 poll_time = 0x7ffffff;
	unsigned long timeout = 0;
	unsigned long flags = 0;
	int len = sspi->slave->head->len;
	int offset = sspi->slave->head->addr;

	if (offset > STORAGE_SIZE) {
		SPI_ERR("The data offset is greater than the storage size\n");
		return -1;
	}

	dprintk(DEBUG_INFO, "[spi%d] receive pkt head ok\n",
			sspi->master->bus_num);

	sspi->slave->data.len = (STORAGE_SIZE - offset) < len ?
				(STORAGE_SIZE - offset) : len;

	sspi->done.done = 0;
	spi_clr_irq_pending(SPI_INT_STA_MASK, sspi->base_addr);
	spi_disable_irq(SPI_INTEN_RX_RDY, sspi->base_addr);
	spi_reset_fifo(sspi->base_addr);
	spi_set_bc_tc_stc(0, 0, 0, 0, sspi->base_addr);
	spi_enable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, sspi->base_addr);

	spin_lock_irqsave(&sspi->lock, flags);
	for (i = 0; i < sspi->slave->head->len; i++) {
		while ((spi_query_txfifo(sspi->base_addr) >= MAX_FIFU) && (--poll_time))
			;
		if (poll_time == 0) {
			dprintk(DEBUG_INFO, "[spi%d]cpu send data timeout\n",
						sspi->master->bus_num);
			goto err;
		}

		writeb(sspi->slave->data.storage[i + offset],
					sspi->base_addr + SPI_TXDATA_REG);
	}
	spin_unlock_irqrestore(&sspi->lock, flags);

	dprintk(DEBUG_DATA, "[debugging only] send data:\n");
	if (debug_mask & DEBUG_DATA)
		spi_dump_data(sspi->slave->data.storage + offset,
				sspi->slave->data.len);

	/* wait for xfer complete in the isr. */
	timeout = wait_for_completion_timeout(
				&sspi->done,
				msecs_to_jiffies(XFER_TIMEOUT));
	if (timeout == 0) {
		SPI_ERR("[spi%d] xfer timeout\n", sspi->master->bus_num);
		ret = -1;
		goto err;
	} else if (sspi->result < 0) {
		SPI_ERR("[spi%d] xfer failed...\n", sspi->master->bus_num);
		ret = -1;
		goto err;
	}

err:
	spi_clr_irq_pending(SPI_INT_STA_MASK, sspi->base_addr);
	spi_disable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, sspi->base_addr);
#ifdef CONFIG_DMA_ENGINE
	spi_disable_dma_irq(SPI_FIFO_CTL_DRQEN_MASK, sspi->base_addr);
#endif
	spi_reset_fifo(sspi->base_addr);

	return ret;
}

static int sunxi_spi_slave_cpu_rx_config(struct sunxi_spi *sspi)
{
	int ret = 0, i;
	u32 poll_time = 0x7ffffff;
	int len = sspi->slave->head->len;
	int offset = sspi->slave->head->addr;

	if (offset > STORAGE_SIZE) {
		SPI_ERR("The data offset is greater than the storage size\n");
		return -1;
	}

	dprintk(DEBUG_INFO, "[spi%d] receive pkt head ok\n",
			sspi->master->bus_num);

	sspi->slave->data.len = (STORAGE_SIZE - offset) < len ?
				(STORAGE_SIZE - offset) : len;

	sspi->done.done = 0;

	spi_set_rx_trig(sspi->slave->data.len/2, sspi->base_addr);
	spi_enable_irq(SPI_INTEN_ERR|SPI_INTEN_RX_RDY, sspi->base_addr);
	spi_set_bc_tc_stc(0, 0, 0, 0, sspi->base_addr);

	for (i = 0; i < sspi->slave->data.len; i++) {
		while (!spi_query_rxfifo(sspi->base_addr) && (--poll_time > 0))
			;
		sspi->slave->data.storage[offset + i] =
			readb(sspi->base_addr + SPI_RXDATA_REG);
	}

	if (poll_time <= 0) {
		SPI_ERR("[spi%d] cpu receive pkt head time out!\n",
				sspi->master->bus_num);
		spi_reset_fifo(sspi->base_addr);
		ret = -1;
		goto err0;
	} else if (sspi->result < 0) {
		SPI_ERR("[spi%d] xfer failed...\n", sspi->master->bus_num);
		spi_reset_fifo(sspi->base_addr);
		ret = -1;
		goto err0;
	}

	dprintk(DEBUG_DATA, "[debugging only] receive data:\n");
	if (debug_mask & DEBUG_DATA)
		spi_dump_data(sspi->slave->data.storage + offset,
				sspi->slave->data.len);

err0:
	spi_clr_irq_pending(SPI_INT_STA_MASK, sspi->base_addr);
	spi_disable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, sspi->base_addr);
#ifdef CONFIG_DMA_ENGINE
	spi_disable_dma_irq(SPI_FIFO_CTL_DRQEN_MASK, sspi->base_addr);
#endif
	spi_reset_fifo(sspi->base_addr);
	return ret;
}
static int sunxi_spi_slave_handle_head(struct sunxi_spi *sspi, u8 *buf)
{
	struct sunxi_spi_slave_head *head;
	int ret = 0;

	head = kzalloc(sizeof(*head), GFP_KERNEL);
	if (IS_ERR_OR_NULL(head)) {
		SPI_ERR("failed to alloc mem\n");
		ret = -ENOMEM;
		goto err0;
	}

	head->op_code = buf[OP_MASK];
	head->addr = (buf[ADDR_MASK_0] << 16) | (buf[ADDR_MASK_1] << 8) | buf[ADDR_MASK_2];
	head->len = buf[LENGTH_MASK];

	dprintk(DEBUG_INFO, "[spi%d] op=0x%x addr=0x%x len=0x%x\n",
			sspi->master->bus_num, head->op_code, head->addr, head->len);

	sspi->slave->head = head;

	if (head->len > 64) {
		dprintk(DEBUG_INFO, "[spi%d] length must less than 64 bytes\n", sspi->master->bus_num);
		ret = -1;
		goto err1;
	}

	if (head->op_code == SUNXI_OP_WRITE) {
		sunxi_spi_slave_cpu_rx_config(sspi);
	} else if (head->op_code == SUNXI_OP_READ) {
		sunxi_spi_slave_cpu_tx_config(sspi);
	} else {
		dprintk(DEBUG_INFO, "[spi%d] pkt head opcode err\n", sspi->master->bus_num);
		ret = -1;
		goto err1;
	}
err1:
	kfree(head);
err0:
	spi_clr_irq_pending(SPI_INT_STA_MASK, sspi->base_addr);
	spi_disable_irq(SPI_INTEN_RX_RDY, sspi->base_addr);
	spi_disable_irq(SPI_INTEN_TC|SPI_INTEN_ERR, sspi->base_addr);
	spi_reset_fifo(sspi->base_addr);

	return ret;
}

static int sunxi_spi_slave_task(void *data)
{
	u8 *pkt_head, i;
	u32 poll_time = 0x7ffffff;
	unsigned long flags = 0;
	struct sunxi_spi *sspi = (struct sunxi_spi *)data;

	pkt_head = kzalloc(HEAD_LEN, GFP_KERNEL);
	if (IS_ERR_OR_NULL(pkt_head)) {
		SPI_ERR("[spi%d] failed to alloc mem\n", sspi->master->bus_num);
		return -ENOMEM;
	}

	allow_signal(SIGKILL);

	while (!kthread_should_stop()) {
		spi_reset_fifo(sspi->base_addr);
		spi_clr_irq_pending(SPI_INT_STA_MASK, sspi->base_addr);
#if IS_ENABLED(CONFIG_DMA_ENGINE)
		spi_disable_dma_irq(SPI_FIFO_CTL_DRQEN_MASK, sspi->base_addr);
#endif
		spi_enable_irq(SPI_INTEN_ERR|SPI_INTEN_RX_RDY, sspi->base_addr);
		spi_set_rx_trig(HEAD_LEN, sspi->base_addr);
		spi_set_bc_tc_stc(0, 0, 0, 0, sspi->base_addr);

		dprintk(DEBUG_INFO, "[spi%d] receive pkt head init ok, sleep and wait for data\n", sspi->master->bus_num);
		set_current_state(TASK_INTERRUPTIBLE);
		schedule();

		dprintk(DEBUG_INFO, "[spi%d] data is come, wake up and receive pkt head\n", sspi->master->bus_num);

		for (i = 0; i < HEAD_LEN ; i++) {
			while (!spi_query_rxfifo(sspi->base_addr) && (--poll_time > 0))
				;
			pkt_head[i] =  readb(sspi->base_addr + SPI_RXDATA_REG);
		}

		if (poll_time <= 0) {
			SPI_ERR("[spi%d] cpu receive pkt head time out!\n", sspi->master->bus_num);
			spi_reset_fifo(sspi->base_addr);
			continue;
		} else if (sspi->result < 0) {
			SPI_ERR("[spi%d] xfer failed...\n", sspi->master->bus_num);
			spi_reset_fifo(sspi->base_addr);
			continue;
		}

		sunxi_spi_slave_handle_head(sspi, pkt_head);
	}

	spin_lock_irqsave(&sspi->lock, flags);
	sspi->task_flag = 1;
	spin_unlock_irqrestore(&sspi->lock, flags);

	kfree(pkt_head);

	return 0;
}

static int sunxi_spi_select_gpio_state(struct pinctrl *pctrl, char *name, u32 no)
{
	int ret = 0;
	struct pinctrl_state *pctrl_state = NULL;

	pctrl_state = pinctrl_lookup_state(pctrl, name);
	if (IS_ERR(pctrl_state)) {
		SPI_ERR("[spi%d] pinctrl_lookup_state(%s) failed! return %p\n", no, name, pctrl_state);
		return -1;
	}

	ret = pinctrl_select_state(pctrl, pctrl_state);
	if (ret < 0)
		SPI_ERR("[spi%d] pinctrl_select_state(%s) failed! return %d\n", no, name, ret);

	return ret;
}

static int sunxi_spi_request_gpio(struct sunxi_spi *sspi)
{
	int bus_no = sspi->pdev->id;

	sspi->pctrl = devm_pinctrl_get(&sspi->pdev->dev);
	if (IS_ERR(sspi->pctrl)) {
		SPI_ERR("[spi%d] devm_pinctrl_get() failed! return %ld\n",
				sspi->master->bus_num, PTR_ERR(sspi->pctrl));
		return -1;
	}

	return sunxi_spi_select_gpio_state(sspi->pctrl, PINCTRL_STATE_DEFAULT, bus_no);
}

/*
static void sunxi_spi_release_gpio(struct sunxi_spi *sspi)
{
	devm_pinctrl_put(sspi->pctrl);
	sspi->pctrl = NULL;
}
*/

static int sunxi_spi_resource_get(struct sunxi_spi *sspi)
{
	int ret;
	struct device_node *np = sspi->pdev->dev.of_node;
	struct sunxi_spi_platform_data *pdata = sspi->pdev->dev.platform_data;
	struct device *dev = &(sspi->pdev->dev);

	ret = spi_regulator_request(pdata, dev);
	if (ret < 0) {
		SPI_ERR("[spi%d] request regulator failed!\n", sspi->master->bus_num);
		return ret;
	}

	ret = of_property_read_u32(sspi->pdev->dev.of_node, "clock-frequency",
			&pdata->sclk_freq_def);
	if (ret) {
		SPI_ERR("[spi%d] Get clock-frequency property failed\n", sspi->master->bus_num);
		return -1;
	}

	ret = of_property_read_u32(np, "spi_slave_mode", &sspi->mode);
	if (sspi->mode)
		dprintk(DEBUG_INIT, "[spi%d] SPI SLAVE MODE\n", sspi->master->bus_num);
	else
		dprintk(DEBUG_INIT, "[spi%d] SPI MASTER MODE\n", sspi->master->bus_num);

	if (sunxi_spi_request_gpio(sspi) < 0) {
		SPI_ERR("[spi%d] Request GPIO failed!\n", sspi->master->bus_num);
		return -1;
	}
	sspi->pclk = devm_clk_get(&sspi->pdev->dev, "pll");
	if (IS_ERR_OR_NULL(sspi->pclk)) {
		SPI_ERR("[spi%d] Unable to acquire module clock '%s', return %x\n",
			sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->pclk));
		return -ENXIO;
	}

	sspi->mclk = devm_clk_get(&sspi->pdev->dev, "mod");
	if (IS_ERR_OR_NULL(sspi->mclk)) {
		SPI_ERR("[spi%d] Unable to acquire module clock '%s', return %x\n",
			sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->mclk));
		return -ENXIO;
	}

	sspi->bus_clk = devm_clk_get(&sspi->pdev->dev, "bus");
	if (IS_ERR_OR_NULL(sspi->bus_clk)) {
		SPI_ERR("[spi%d] Unable to acquire bus clock '%s', return %x\n",
			sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->bus_clk));
		return -ENXIO;
	}

	if (!sspi->reset) {
		sspi->reset = devm_reset_control_get(&sspi->pdev->dev, NULL);
		if (IS_ERR_OR_NULL(sspi->reset)) {
			SPI_ERR("[spi%d] Unable to acquire reset clock '%s', return %x\n",
				sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->reset));
			return -ENXIO;
		}
	}

	ret = of_property_read_u32(np, "sample_mode", &sspi->sample_mode);
	if (ret) {
		SPI_ERR("Failed to get sample mode\n");
		sspi->sample_mode = SAMP_MODE_DL_DEFAULT;
	}
	ret = of_property_read_u32(np, "sample_delay", &sspi->sample_delay);
	if (ret) {
		SPI_ERR("Failed to get sample delay\n");
		sspi->sample_delay = SAMP_MODE_DL_DEFAULT;
	}
	dprintk(DEBUG_INIT, "sample_mode:%d sample_delay:%d\n",
				sspi->sample_mode, sspi->sample_delay);

	return 0;
}

static int sunxi_spi_clk_init(struct sunxi_spi *sspi, u32 mod_clk)
{
	int ret = 0;
	long rate = 0;

	/*assert and deassert constitute a complete hardware reset operation*/
	ret = reset_control_assert(sspi->reset);
	if (ret != 0) {
		SPI_ERR("[spi%d] Unable to assert reset clock '%s', return %x\n",
			sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->mclk));
		return -ENXIO;
	}
	ret = reset_control_deassert(sspi->reset);
	if (ret != 0) {
		SPI_ERR("[spi%d] Unable to deassert reset clock '%s', return %x\n",
			sspi->master->bus_num, sspi->dev_name, PTR_RET(sspi->mclk));
		return -ENXIO;
	}

	if (clk_prepare_enable(sspi->pclk)) {
		SPI_ERR("[spi%d] Couldn't enable pll clock 'spi'\n", sspi->master->bus_num);
		goto err1;
	}

	ret = clk_set_parent(sspi->mclk, sspi->pclk);
	if (ret != 0) {
		SPI_ERR("[spi%d] clk_set_parent() failed! return %d\n",
			sspi->master->bus_num, ret);
		goto err2;
	}

	rate = clk_round_rate(sspi->mclk, mod_clk);
	if (clk_set_rate(sspi->mclk, rate)) {
		SPI_ERR("[spi%d] spi clk_set_rate failed\n", sspi->master->bus_num);
		goto err2;
	}

	dprintk(DEBUG_INIT, "[spi%d] mclk %u\n", sspi->master->bus_num, (unsigned)clk_get_rate(sspi->mclk));

	if (clk_prepare_enable(sspi->mclk)) {
		SPI_ERR("[spi%d] Couldn't enable module clock 'spi'\n", sspi->master->bus_num);
		goto err2;
	}

	if (clk_prepare_enable(sspi->bus_clk)) {
		SPI_ERR("[spi%d] Couldn't enable bus clock 'spi'\n", sspi->master->bus_num);
		goto err3;
	}

	return clk_get_rate(sspi->mclk);

err3:
	clk_disable_unprepare(sspi->bus_clk);
err2:
	clk_disable_unprepare(sspi->mclk);
err1:
	clk_disable_unprepare(sspi->pclk);

	return -1;
}

static int sunxi_spi_clk_exit(struct sunxi_spi *sspi)
{
	if (IS_ERR_OR_NULL(sspi->mclk)) {
		SPI_ERR("[spi%d] SPI mclk handle is invalid!\n", sspi->master->bus_num);
		return -1;
	}

	clk_disable_unprepare(sspi->bus_clk);
	clk_disable_unprepare(sspi->mclk);
	return 0;
}

static int sunxi_spi_hw_init(struct sunxi_spi *sspi,
		struct sunxi_spi_platform_data *pdata, struct device *dev)
{
	void __iomem *base_addr = sspi->base_addr;
	u32 sclk_freq_def = 0;
	int sclk_freq = 0;
	int bus_no = sspi->pdev->id;
#ifdef CONFIG_AW_MTD_SPINAND
	struct device_node *child = NULL;
	const char *st = NULL;
#endif

	spi_regulator_enable(pdata);

	sclk_freq = sunxi_spi_clk_init(sspi, pdata->sclk_freq_def);
	if (sclk_freq < 0) {
		SPI_ERR("[spi%d] sunxi_spi_clk_init(%s) failed!\n", sspi->master->bus_num, sspi->dev_name);
		return -1;
	}

	if (!sspi->dbi_enabled) {
		/* enable the spi module */
		spi_enable_bus(base_addr);
	}

	sunxi_spi_select_gpio_state(sspi->pctrl, PINCTRL_STATE_DEFAULT, bus_no);

	if (sspi->dbi_enabled) {
		spi_set_slave(base_addr);
		spi_set_dbi(base_addr);
		spi_enable_dbi(base_addr);
		spi_set_clk(10000000, sclk_freq, sspi);
		spi_enable_tp(base_addr);
	}
	if (!sspi->mode) {
		/* master: set spi module clock;
		 * set the default frequency	10MHz
		 */
		spi_set_master(base_addr);
		spi_set_clk(10000000, sclk_freq, sspi);
		/* master : set POL,PHA,SSOPL,LMTF,DDB,DHB; default: SSCTL=0,SMC=1,TBW=0. */
		spi_config_tc(1, SPI_MODE_0, base_addr);
		spi_enable_tp(base_addr);
		/* manual control the chip select */

#ifndef CONFIG_AW_MTD_SPINAND
		sunxi_spi_ss_ctrl(base_addr, true);
#else
		child = of_find_node_by_name(dev->of_node, "spi-nand");
		if (child)
			of_property_read_string(child, "status", &st);

		if (st && (!strcmp(st, "okay") || !strcmp(st, "ok"))) {
			sunxi_spi_ss_ctrl(base_addr, false);
		}
#endif
	} else {
		//slave
		spi_set_slave(base_addr);
		/* master : set POL,PHA,SSOPL,LMTF,DDB,DHB; default: SSCTL=0,SMC=1,TBW=0. */
		spi_config_tc(1, SPI_MODE_0, base_addr);
		spi_set_clk(sclk_freq_def, sclk_freq, sspi);

		if (sspi->sample_delay == SAMP_MODE_DL_DEFAULT) {
			if (sclk_freq_def >= SPI_HIGH_FREQUENCY)
				spi_sample_delay(0, 1, 0, base_addr);
			else if (sclk_freq_def <= SPI_LOW_FREQUENCY)
				spi_sample_delay(1, 0, 0, base_addr);
			else
				spi_sample_delay(0, 0, 0, base_addr);
		} else {
			spi_samp_mode_enable(1, base_addr);
			spi_samp_dl_sw_status(1, base_addr);
			spi_set_sample_mode(sspi->sample_mode, base_addr);
			spi_set_sample_delay(sspi->sample_delay, base_addr);
		}
	}

	/* reset fifo */
	spi_reset_fifo(base_addr);

	return 0;
}

static int sunxi_spi_hw_exit(struct sunxi_spi *sspi, struct sunxi_spi_platform_data *pdata)
{
	struct spi_master *master = sspi->master;

	/* release the  gpio */
	//sunxi_spi_release_gpio(sspi);
	sunxi_spi_select_gpio_state(sspi->pctrl, PINCTRL_STATE_SLEEP, master->bus_num);

	/* disable the spi controller */
	spi_disable_bus(sspi->base_addr);

	/* disable module clock */
	sunxi_spi_clk_exit(sspi);

	/* disable regulator */
	spi_regulator_disable(pdata);

	return 0;
}

static ssize_t sunxi_spi_info_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	struct platform_device *pdev = container_of(dev, struct platform_device, dev);
	struct sunxi_spi_platform_data *pdata = dev->platform_data;

	return snprintf(buf, PAGE_SIZE,
		"pdev->id   = %d\n"
		"pdev->name = %s\n"
		"pdev->num_resources = %u\n"
		"pdev->resource.mem = [%pa, %pa]\n"
		"pdev->resource.irq = %pa\n"
		"pdev->dev.platform_data.cs_num    = %d\n"
		"pdev->dev.platform_data.regulator = 0x%p\n"
		"pdev->dev.platform_data.regulator_id = %s\n",
		pdev->id, pdev->name, pdev->num_resources,
		&pdev->resource[0].start, &pdev->resource[0].end,
		&pdev->resource[1].start, pdata->cs_num, pdata->regulator,
		pdata->regulator_id);
}
static struct device_attribute sunxi_spi_info_attr =
	__ATTR(info, S_IRUGO, sunxi_spi_info_show, NULL);

static ssize_t sunxi_spi_status_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct sunxi_spi *sspi = (struct sunxi_spi *)&master[1];
	char const *spi_mode[] = {"Single mode, half duplex read",
				  "Single mode, half duplex write",
				  "Single mode, full duplex read and write",
				  "Dual mode, half duplex read",
				  "Dual mode, half duplex write",
				  "Null"};
	char const *busy_state[] = {"Unknown", "Free", "Suspend", "Busy"};
	char const *result_str[] = {"Success", "Fail"};
#if IS_ENABLED(CONFIG_DMA_ENGINE)
	char const *dma_dir[] = {"DMA NULL", "DMA read", "DMA write"};
#endif

	if (master == NULL)
		return snprintf(buf, PAGE_SIZE, "%s\n", "spi_master is NULL!");

	return snprintf(buf, PAGE_SIZE,
			"master->bus_num = %d\n"
			"master->num_chipselect = %d\n"
			"master->dma_alignment  = %d\n"
			"master->mode_bits = %d\n"
			"master->flags = 0x%x, ->bus_lock_flag = 0x%x\n"
			"master->busy = %d, ->running = %d, ->rt = %d\n"
			"sspi->mode_type = %d [%s]\n"
			"sspi->irq = %d [%s]\n"
#if IS_ENABLED(CONFIG_DMA_ENGINE)
			"sspi->dma_tx.dir = %d [%s]\n"
			"sspi->dma_rx.dir = %d [%s]\n"
#endif
			"sspi->busy = %d [%s]\n"
			"sspi->result = %d [%s]\n"
			"sspi->base_addr = 0x%p, the SPI control register:\n"
			"[VER] 0x%02x = 0x%08x, [GCR] 0x%02x = 0x%08x, [TCR] 0x%02x = 0x%08x\n"
			"[ICR] 0x%02x = 0x%08x, [ISR] 0x%02x = 0x%08x, [FCR] 0x%02x = 0x%08x\n"
			"[FSR] 0x%02x = 0x%08x, [WCR] 0x%02x = 0x%08x, [CCR] 0x%02x = 0x%08x\n"
			"[BCR] 0x%02x = 0x%08x, [TCR] 0x%02x = 0x%08x, [BCC] 0x%02x = 0x%08x\n"
			"[DMA] 0x%02x = 0x%08x, [TXR] 0x%02x = 0x%08x, [RXD] 0x%02x = 0x%08x\n",
			master->bus_num, master->num_chipselect, master->dma_alignment,
			master->mode_bits, master->flags, master->bus_lock_flag,
			master->busy, master->running, master->rt,
			sspi->mode_type, spi_mode[sspi->mode_type],
			sspi->irq, sspi->dev_name,
#if IS_ENABLED(CONFIG_DMA_ENGINE)
			sspi->dma_tx.dir, dma_dir[sspi->dma_tx.dir],
			sspi->dma_rx.dir, dma_dir[sspi->dma_rx.dir],
#endif
			sspi->busy, busy_state[sspi->busy],
			sspi->result, result_str[sspi->result],
			sspi->base_addr,
			SPI_VER_REG, readl(sspi->base_addr + SPI_VER_REG),
			SPI_GC_REG, readl(sspi->base_addr + SPI_GC_REG),
			SPI_TC_REG, readl(sspi->base_addr + SPI_TC_REG),
			SPI_INT_CTL_REG, readl(sspi->base_addr + SPI_INT_CTL_REG),
			SPI_INT_STA_REG, readl(sspi->base_addr + SPI_INT_STA_REG),

			SPI_FIFO_CTL_REG, readl(sspi->base_addr + SPI_FIFO_CTL_REG),
			SPI_FIFO_STA_REG, readl(sspi->base_addr + SPI_FIFO_STA_REG),
			SPI_WAIT_CNT_REG, readl(sspi->base_addr + SPI_WAIT_CNT_REG),
			SPI_CLK_CTL_REG, readl(sspi->base_addr + SPI_CLK_CTL_REG),
			SPI_BURST_CNT_REG, readl(sspi->base_addr + SPI_BURST_CNT_REG),

			SPI_TRANSMIT_CNT_REG, readl(sspi->base_addr + SPI_TRANSMIT_CNT_REG),
			SPI_BCC_REG, readl(sspi->base_addr + SPI_BCC_REG),
			SPI_DMA_CTL_REG, readl(sspi->base_addr + SPI_DMA_CTL_REG),
			SPI_TXDATA_REG, readl(sspi->base_addr + SPI_TXDATA_REG),
			SPI_RXDATA_REG, readl(sspi->base_addr + SPI_RXDATA_REG));
}
static struct device_attribute sunxi_spi_status_attr =
	__ATTR(status, S_IRUGO, sunxi_spi_status_show, NULL);

static void sunxi_spi_create_sysfs(struct platform_device *_pdev)
{
	device_create_file(&_pdev->dev, &sunxi_spi_info_attr);
	device_create_file(&_pdev->dev, &sunxi_spi_status_attr);
}

static void sunxi_spi_remove_sysfs(struct platform_device *_pdev)
{
	device_remove_file(&_pdev->dev, &sunxi_spi_info_attr);
	device_remove_file(&_pdev->dev, &sunxi_spi_status_attr);
}

static int sunxi_spi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct resource	*mem_res;
	struct sunxi_spi *sspi;
	struct sunxi_spi_platform_data *pdata;
	struct spi_master *master;
	struct sunxi_slave *slave = NULL;
	char spi_para[16] = {0};
	int ret = 0, err = 0, irq;
#ifdef CONFIG_AW_MTD_SPINAND
	struct device_node *child = NULL;
	const char *st = NULL;
#endif

	if (np == NULL) {
		SPI_ERR("SPI failed to get of_node\n");
		return -ENODEV;
	}

	pdev->id = of_alias_get_id(np, "spi");
	if (pdev->id < 0) {
		SPI_ERR("SPI failed to get alias id\n");
		return -EINVAL;
	}

#if IS_ENABLED(CONFIG_DMA_ENGINE)
	pdev->dev.dma_mask = &sunxi_spi_dma_mask;
	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
#endif

	pdata = kzalloc(sizeof(struct sunxi_spi_platform_data), GFP_KERNEL);
	if (pdata == NULL) {
		SPI_ERR("SPI failed to alloc mem\n");
		return -ENOMEM;
	}
	pdev->dev.platform_data = pdata;

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem_res == NULL) {
		SPI_ERR("Unable to get spi MEM resource\n");
		ret = -ENXIO;
		goto err0;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		SPI_ERR("No spi IRQ specified\n");
		ret = -ENXIO;
		goto err0;
	}

	snprintf(spi_para, sizeof(spi_para), "spi%d_cs_number", pdev->id);
	ret = of_property_read_u32(np, spi_para, &pdata->cs_num);
	if (ret) {
		SPI_ERR("Failed to get cs_number property\n");
		ret = -EINVAL;
		goto err0;
	}


	/* create spi master */
	master = spi_alloc_master(&pdev->dev, sizeof(struct sunxi_spi));
	if (master == NULL) {
		SPI_ERR("Unable to allocate SPI Master\n");
		ret = -ENOMEM;
		goto err0;
	}


	platform_set_drvdata(pdev, master);
	sspi = spi_master_get_devdata(master);
	memset(sspi, 0, sizeof(struct sunxi_spi));

	sspi->master        = master;
#if IS_ENABLED(CONFIG_DMA_ENGINE)
	sspi->dma_rx.dir		= SPI_DMA_RWNULL;
	sspi->dma_tx.dir		= SPI_DMA_RWNULL;
#endif
	sspi->busy			= SPI_FREE;
	sspi->mode_type			= MODE_TYPE_NULL;
	sspi->irq			= irq;

	master->max_speed_hz		= SPI_MAX_FREQUENCY;
	master->dev.of_node		= pdev->dev.of_node;
	master->bus_num			= pdev->id;
	master->setup			= sunxi_spi_setup;
	master->can_dma			= sunxi_spi_can_dma;
	master->transfer_one		= sunxi_spi_transfer_one;
	master->use_gpio_descriptors	= true;
	master->set_cs			= sunxi_spi_set_cs;
	master->num_chipselect		= pdata->cs_num;
	master->bits_per_word_mask	= SPI_BPW_MASK(8);
	/* the spi->mode bits understood by this driver: */
	master->mode_bits	= SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
				| SPI_LSB_FIRST | SPI_TX_DUAL | SPI_TX_QUAD
				| SPI_RX_DUAL | SPI_RX_QUAD;

#ifdef CONFIG_AW_MTD_SPINAND
	child = of_find_node_by_name(np, "spi-nand");
	if (child)
		of_property_read_string(child, "status", &st);

	if (st && (!strcmp(st, "okay") || !strcmp(st, "ok"))) {
		master->transfer_one_message = sunxi_spi_transfer_one_message;
		master->transfer_two = sunxi_spi_transfer_two;

	}
#endif
    
	ret = of_property_read_u32(np, "spi_dbi_enable", &sspi->dbi_enabled);
	if (ret)
		sspi->dbi_enabled = 0;
	else
		dprintk(DEBUG_INIT, "[spi%d] SPI DBI INTERFACE\n", sspi->master->bus_num);

	if (sspi->dbi_enabled)
		sspi->dbi_config = kzalloc(sizeof(struct spi_dbi_config), GFP_KERNEL);

	snprintf(sspi->dev_name, sizeof(sspi->dev_name), SUNXI_SPI_DEV_NAME"%d", pdev->id);

	err = devm_request_irq(&pdev->dev, irq, sunxi_spi_handler, 0,
			sspi->dev_name, sspi);
	if (err) {
		SPI_ERR("[spi%d] Cannot request IRQ\n", sspi->master->bus_num);
		ret = -EINVAL;
		goto err1;
	}

	if (request_mem_region(mem_res->start,
			resource_size(mem_res), pdev->name) == NULL) {
		SPI_ERR("[spi%d] Req mem region failed\n", sspi->master->bus_num);
		ret = -ENXIO;
		goto err2;
	}

	sspi->base_addr = ioremap(mem_res->start, resource_size(mem_res));
	if (sspi->base_addr == NULL) {
		SPI_ERR("[spi%d] Unable to remap IO\n", sspi->master->bus_num);
		ret = -ENXIO;
		goto err3;
	}

	sspi->base_addr_phy = mem_res->start;
	sspi->pdev = pdev;
	pdev->dev.init_name = sspi->dev_name;

	err = sunxi_spi_resource_get(sspi);
	if (err) {
		SPI_ERR("[spi%d] resource get error\n", sspi->master->bus_num);
		ret = -EINVAL;
		goto err1;
	}

	/* Setup Deufult Mode */
	ret = sunxi_spi_hw_init(sspi, pdata, &pdev->dev);
	if (ret != 0) {
		SPI_ERR("[spi%d] spi hw init failed!\n", sspi->master->bus_num);
		ret = -EINVAL;
		goto err4;
	}

	spin_lock_init(&sspi->lock);
	init_completion(&sspi->done);

	if (sspi->mode) {
		slave = kzalloc(sizeof(*slave), GFP_KERNEL);
		if (IS_ERR_OR_NULL(slave)) {
			SPI_ERR("[spi%d] failed to alloc mem\n", sspi->master->bus_num);
			ret = -ENOMEM;
			goto err5;
		}
		slave->data.storage = kzalloc(STORAGE_SIZE, GFP_KERNEL);
		if (IS_ERR_OR_NULL(slave->data.storage)) {
			SPI_ERR("failed to alloc mem\n");
			ret = -ENOMEM;
			goto err0;
		}
		sspi->slave = slave;
		sspi->task = kthread_create(sunxi_spi_slave_task, sspi, "spi_slave");
		if (IS_ERR(sspi->task)) {
			SPI_ERR("[spi%d] unable to start kernel thread.\n", sspi->master->bus_num);
			ret = PTR_ERR(sspi->task);
			sspi->task = NULL;
			ret = -EINVAL;
			goto err6;
		}

		wake_up_process(sspi->task);
	} else {
		if (spi_register_master(master)) {
			SPI_ERR("[spi%d] cannot register SPI master\n", sspi->master->bus_num);
			ret = -EBUSY;
			goto err6;
		}
	}

	sunxi_spi_create_sysfs(pdev);

	dprintk(DEBUG_INFO, "[spi%d] loaded for Bus with %d Slaves at most\n",
		master->bus_num, master->num_chipselect);
	dprintk(DEBUG_INIT, "[spi%d]: driver probe succeed, base %px, irq %d\n",
		master->bus_num, sspi->base_addr, sspi->irq);
	return 0;

err6:
	if (sspi->mode)
		if (!IS_ERR_OR_NULL(slave))
			kfree(slave);
err5:
	sunxi_spi_hw_exit(sspi, pdev->dev.platform_data);

err4:
	iounmap(sspi->base_addr);
err3:
	release_mem_region(mem_res->start, resource_size(mem_res));
err2:
	free_irq(sspi->irq, sspi);
err1:
	if (sspi->dbi_enabled)
		kfree(sspi->dbi_config);
	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
err0:
	kfree(pdev->dev.platform_data);

	return ret;
}

static int sunxi_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct sunxi_spi *sspi = spi_master_get_devdata(master);
	struct resource	*mem_res;
	unsigned long flags;

	spin_lock_irqsave(&sspi->lock, flags);
	sspi->busy |= SPI_FREE;
	spin_unlock_irqrestore(&sspi->lock, flags);

	while (sspi->busy & SPI_BUSY)
		msleep(10);

	sunxi_spi_remove_sysfs(pdev);
	spi_unregister_master(master);

	if (sspi->mode)
		if (!sspi->task_flag)
			if (!IS_ERR(sspi->task))
				kthread_stop(sspi->task);

	sunxi_spi_hw_exit(sspi, pdev->dev.platform_data);
	iounmap(sspi->base_addr);

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem_res != NULL)
		release_mem_region(mem_res->start, resource_size(mem_res));
	free_irq(sspi->irq, sspi);

	if (sspi->dbi_enabled)
		kfree(sspi->dbi_config);

	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
	kfree(pdev->dev.platform_data);

	return 0;
}

#if IS_ENABLED(CONFIG_PM)
static int sunxi_spi_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct sunxi_spi *sspi = spi_master_get_devdata(master);
	unsigned long flags;

	spin_lock_irqsave(&sspi->lock, flags);
	sspi->busy |= SPI_SUSPND;
	spin_unlock_irqrestore(&sspi->lock, flags);

	while (sspi->busy & SPI_BUSY)
		msleep(10);

	sunxi_spi_hw_exit(sspi, pdev->dev.platform_data);

	dprintk(DEBUG_SUSPEND, "[spi%d] suspend finish\n", master->bus_num);

	return 0;
}

static int sunxi_spi_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct sunxi_spi  *sspi = spi_master_get_devdata(master);
	unsigned long flags;

	sunxi_spi_hw_init(sspi, pdev->dev.platform_data, dev);

	spin_lock_irqsave(&sspi->lock, flags);
	sspi->busy = SPI_FREE;
	spin_unlock_irqrestore(&sspi->lock, flags);
	dprintk(DEBUG_SUSPEND, "[spi%d] resume finish\n", master->bus_num);

	return 0;
}

static const struct dev_pm_ops sunxi_spi_dev_pm_ops = {
	.suspend = sunxi_spi_suspend,
	.resume  = sunxi_spi_resume,
};

#define SUNXI_SPI_DEV_PM_OPS (&sunxi_spi_dev_pm_ops)
#else
#define SUNXI_SPI_DEV_PM_OPS NULL
#endif /* CONFIG_PM */

static const struct of_device_id sunxi_spi_match[] = {
	{ .compatible = "allwinner,sun8i-spi", },
	{ .compatible = "allwinner,sun20i-spi", },
	{ .compatible = "allwinner,sun50i-spi", },
	{},
};
MODULE_DEVICE_TABLE(of, sunxi_spi_match);


static struct platform_driver sunxi_spi_driver = {
	.probe   = sunxi_spi_probe,
	.remove  = sunxi_spi_remove,
	.driver = {
		.name	= SUNXI_SPI_DEV_NAME,
		.owner	= THIS_MODULE,
		.pm		= SUNXI_SPI_DEV_PM_OPS,
		.of_match_table = sunxi_spi_match,
	},
};

static int __init sunxi_spi_init(void)
{
	return platform_driver_register(&sunxi_spi_driver);
}

static void __exit sunxi_spi_exit(void)
{
	platform_driver_unregister(&sunxi_spi_driver);
}

fs_initcall_sync(sunxi_spi_init);
module_exit(sunxi_spi_exit);
module_param_named(debug, debug_mask, int, 0664);

MODULE_AUTHOR("pannan");
MODULE_DESCRIPTION("SUNXI SPI BUS Driver");
MODULE_ALIAS("platform:"SUNXI_SPI_DEV_NAME);
MODULE_LICENSE("GPL");

&spi1_pins_a {
	allwinner,pins = "PD11", "PD12", "PD13";
	allwinner,pname = "spi1_sclk", "spi1_mosi",
			"spi1_miso";
	allwinner,function = "spi1";
	allwinner,muxsel = <4>;
	allwinner,drive = <1>;
	allwinner,pull = <0>;
};

&spi1_pins_b {
	allwinner,pins = "PD10";
	allwinner,pname = "spi1_cs0";
	allwinner,function = "spi1";
	allwinner,muxsel = <4>;
	allwinner,drive = <1>;
	allwinner,pull = <1>;   // only CS should be pulled up
};

&spi1_pins_c {
	allwinner,pins = "PD10", "PD11", "PD12", "PD13";
	allwinner,function = "gpio_in";
	allwinner,muxsel = <0>;
	allwinner,drive = <1>;
	allwinner,pull = <0>;
};

&spi1 {
	clock-frequency = <100000000>;
	pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
	pinctrl-1 = <&spi1_pins_c>;
	pinctrl-names = "default", "sleep";
	spi_slave_mode = <0>;
    spi_dbi_enable = <0>;
	status = "okay";
};

static void lcd_panel_st7789v_init(void)
{
    int ret;
    spi = spi_setup_slave(1, 0, 12000000, SPI_MODE_0);
    if (!spi)
    {
        printf("SPI setup failed\n");
        // return -1;
    }
    // ret = spi_get_bus_and_cs(1, 0, 12000000, SPI_MODE_0, "spi_generic", "spi_generic", &dev, &spi);
    ret = spi_claim_bus(spi);
    if (ret)
    {
        printf("SPI claim failed\n");
    }
...

static void st7789v_spi_write_cmd(u8 value)
{
    spi_dc_0;
    uint8_t tx_buf[1] = {value};
    uint8_t rx_buf[1];
    spi_xfer(spi, 1, tx_buf, rx_buf, 0);
    // spi_write(spi, tx_buf, 1);
    spi_dc_1;
}

[00.446]drv_disp_init                                                                                       
[00.456]get fdt s_pwm.pwm-base fail                                                                         
fdt get node offset faill: hdmi                                                                             
[00.462]drv_disp_init finish                                                                                
[00.467]Loading Environment from SUNXI_FLASH... OK                                                          
[00.480]boot_gui_init:start                                                                                 
[00.483]set disp.dev2_output_type fail. using defval=0                                                      
============                                                                                                
st7789 lcd open flowr                                                                                       
============                                                                                                
FDT ERROR:fdt_get_all_pin:get property handle pinctrl-0 error:FDT_ERR_INTERNAL                              
disp_sys_pin_set_state, fdt_set_all_pin, ret=-1                                                             
[00.504]set disp.fb0_rot_used fail. using defval=0                                                          
[00.509]set disp.fb0_rot_degree fail. using defval=0                                                        
[00.513]boot_gui_init:finish                                                                                
partno erro : can't find partition bootloader                                                               
[00.521]bmp_name=bootlogo.bmp size 84870                                                                    
data abort                                                                                                  
pc : [<47f0bb22>]          lr : [<47ef1041>]                                                                
reloc pc : [<43042b22>]    lr : [<43028041>]                                                                
sp : 43e66ce0  ip : 00000000     fp : 00000000                                                              
r10: 47fb4924  r9 : 43ea8e70     r8 : 00000000                                                              
r7 : 43e66d0c  r6 : 43e66d08     r5 : 00000000  r4 : eb00007d                                               
r3 : 00000000  r2 : 00000000     r1 : 00000000  r0 : 00000000                                               
Flags: nZcv  IRQs on  FIQs off  Mode SVC_32                                                                 
Code: 2e00d057 46a8bf14 0800f04f bf082f00 (69232500)                                                        
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
SPI_ISR time_out                                                                                            
partno erro : can't find partition bootloader                                                               
[06.679]bmp_name=bootlogo.bmp size 84870                                                                    
fb_lock: fb_id(0), lock=2                                                                                   
cv=00000000, base= 00000000                                                                                 
[06.690]show bmp on fb failed !-1                                                                           
[07.043]LCD open finish    

U-Boot 2018.07-ge987def5-dirty (Jan 02 2025 - 13:05:01 +0800) Allwinner Technology                          
                                                                                                            
[00.319]CPU:   Allwinner Family                                                                             
[00.322]Model: sun8iw20                                                                                     
I2C:   FDT ERROR:fdt_set_all_pin:[twi0]-->FDT_ERR_BADPATH                                                   
FDT ERROR:fdt_set_all_pin:[twi1]-->FDT_ERR_BADPATH                                                          
ready                                                                                                       
[00.343]DRAM:  128 MiB                                                                                      
[00.346]Relocation Offset is: 04eca000                                                                      
[00.371]secure enable bit: 0                                                                                
[00.373]smc_tee_inform_fdt failed with: ffff000a                                                            
[00.379]CPU=1008 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz  MBus=300Mhz                                     
[00.385]gic: sec monitor mode                                                                               
sunxi flash map init                                                                                        
[00.390]flash init start                                                                                    
[00.392]workmode = 0,storage type = 2                                                                       
[00.396][mmc]: mmc driver ver uboot2018:2021-12-20 13:35:00                                                 
[00.402][mmc]: SUNXI SDMMC Controller Version:0x50310                                                       
[00.429][mmc]: Best spd md: 2-HSDDR52/DDR50, freq: 2-50000000, Bus width: 4                                 
[00.435]sunxi flash init ok                                                                                 
[00.438]line:703 init_clocks                                                                                
[00.441]drv_disp_init                                                                                       
[00.451]get fdt s_pwm.pwm-base fail                                                                         
fdt get node offset faill: hdmi                                                                             
[00.457]drv_disp_init finish                                                                                
[00.462]Loading Environment from SUNXI_FLASH... OK                                                          
[00.476]boot_gui_init:start                                                                                 
[00.478]set disp.dev2_output_type fail. using defval=0                                                      
[00.483]LCD open finish                                                                                     
[00.485]set disp.fb0_rot_used fail. using defval=0                                                          
[00.490]set disp.fb0_rot_degree fail. using defval=0                                                        
[00.495]boot_gui_init:finish                                                                                
partno erro : can't find partition bootloader                                                               
[00.502]bmp_name=bootlogo.bmp size 38454                                                                    
[00.508]Item0 (Map) magic is bad                                                                            
[00.511]the secure storage item0 copy0 magic is bad                                                         
[00.516]Item0 (Map) magic is bad                                                                            
[00.518]the secure storage item0 copy1 magic is bad                                                         
[00.523]Item0 (Map) magic is bad                                                                            
secure storage read widevine fail                                                                           
[00.529]secure storage read widevine fail with:-1                                                           
secure storage read ec_key fail                                                                             
[00.536]secure storage read ec_key fail with:-1                                                             
secure storage read ec_cert1 fail                                                                           
[00.544]secure storage read ec_cert1 fail with:-1                                                           
secure storage read ec_cert2 fail                                                                           
[00.551]secure storage read ec_cert2 fail with:-1                                                           
secure storage read ec_cert3 fail                                                                           
[00.558]secure storage read ec_cert3 fail with:-1                                                           
secure storage read rsa_key fail                                                                            
[00.566]secure storage read rsa_key fail with:-1                                                            
secure storage read rsa_cert1 fail                                                                          
[00.573]secure storage read rsa_cert1 fail with:-1                                                          
secure storage read rsa_cert2 fail                                                                          
[00.581]secure storage read rsa_cert2 fail with:-1                                                          
secure storage read rsa_cert3 fail                                                                          
[00.588]secure storage read rsa_cert3 fail with:-1                                                          
[00.593]out of usb burn from boot: not need burn key                                                        
root_partition is rootfs                                                                                    
set root to /dev/mmcblk0p5                                                                                  
[00.603]update part info                                                                                    
[00.605]update bootcmd                                                                                      
[00.608]change working_fdt 0x43e89e70 to 0x43e69e70                                                         
[00.613][mmc]: no mmc-hs400-1_8v!                                                                           
[00.616][mmc]: delete mmc-hs200-1_8v from dtb                                                               
[00.620][mmc]: get max-frequency ok 50000000 Hz                                                             
disable nand error: FDT_ERR_BADPATH                                                                         
[00.639]update dts                                                                                          
Hit any key to stop autoboot:  0                                                                            
[01.729]no vendor_boot partition is found                                                                   
Android's image name: t113-nezha                                                                            
ERROR: reserving fdt memory region failed (addr=43f14000 size=1fa40)                                        
[01.747]Starting kernel ...                               

[00.444]drv_disp_init                                                                                       
[00.454]get fdt s_pwm.pwm-base fail                                                                         
fdt get node offset faill: hdmi                                                                             
[00.460]drv_disp_init finish                                                                                
[00.466]Loading Environment from SUNXI_FLASH... OK                                                          
[00.479]boot_gui_init:start                                                                                 
[00.482]set disp.dev2_output_type fail. using defval=0                                                      
FDT ERROR:fdt_get_all_pin:get property handle pinctrl-0 error:FDT_ERR_INTERNAL                              
disp_sys_pin_set_state, fdt_set_all_pin, ret=-1                                                             
[00.498]set disp.fb0_rot_used fail. using defval=0                                                          
[00.503]set disp.fb0_rot_degree fail. using defval=0                                                        
[00.507]boot_gui_init:finish                                                                                
partno erro : can't find partition bootloader                                                               
[00.515]bmp_name=bootlogo.bmp size 38454  

disp
screen 0:
de_rate 300000000 hz, ref_fps:59
mgr0: 240x135 fmt[rgb] cs[0x204] range[full] eotf[0x4] bits[8bits] err[1] force_sync[0] unblank direct_show[false] iommu[0]
        lcd output      backlight(197)  fps:76.4         240x 135
        err:0   skip:0  irq:25296       vsync:0 vsync_skip:0

   BUF    enable ch[1] lyr[0] z[0] prem[N] a[globl 255] fmt[  0] fb[ 240, 135;   0,   0;   0,   0] crop[   0,   0, 240, 135] frame[   0,   0, 240, 135] addr[43f13000,       0,       0] flags[0x       0] trd[0,0]

root@TinaLinux:/# [    6.879707] sunxi_usb_udc 4100000.udc-controller: 4100000.udc-controller supply udc not f   

secure storage read rsa_cert1 fail                                                                          
[00.615]secure storage read rsa_cert1 fail with:-1                                                          
secure storage read rsa_cert2 fail                                                                          
[00.623]secure storage read rsa_cert2 fail with:-1                                                          
secure storage read rsa_cert3 fail                                                                          
[00.630]secure storage read rsa_cert3 fail with:-1                                                          
[00.635]out of usb burn from boot: not need burn key                                                        
root_partition is rootfs                                                                                    
set root to /dev/mmcblk0p5                                                                                  
[00.644]update part info                                                                                    
[00.647]update bootcmd                                                                                      
[00.649]change working_fdt 0x43ebee70 to 0x43e9ee70                                                         
[00.655][mmc]: no mmc-hs400-1_8v!                                                                           
[00.657][mmc]: delete mmc-hs200-1_8v from dtb                                                               
[00.662][mmc]: get max-frequency ok 50000000 Hz                                                             
disable nand error: FDT_ERR_BADPATH                                                                         
[00.678]update dts                                                                                          
Hit any key to stop autoboot:  0                                                                            
=>                                                                                                          
=>                                                                                                          
=> @@ @ @A@ @@@B$ @
  @@)@@$@ I           d &
                              FQ0",Hds0#2v, !!$`",b63 !                     ɲ

[4379][AUTO DEBUG] rank 0 row = 13 
[4382][AUTO DEBUG] rank 0 bank = 8 
[4385][AUTO DEBUG] rank 0 page size = 2 KB 
[4389]DRAM BOOT DRIVE INFO: V0.33
[4392]DRAM CLK = 936 MHz
[4395]DRAM Type = 3 (2:DDR2,3:DDR3)
[4398]DRAMC read ODT  off.                                                                                  
[4401]DRAM ODT value: 0x42.                                                                                 
[4403]ddr_efuse_type: 0xa                                                                                   
[4407]DRAM SIZE =128 M                                                                                      
[4409]dram_tpr4:0x0                                                                                         
[4411]PLL_DDR_CTRL_REG:0xf8004d00                                                                           
[4414]DRAM_CLK_REG:0xc0000000                                                                               
[4416][TIMING DEBUG] MR2= 0x20                                                                              
[4421]DRAM simple test OK.                                                                                  
[4423]rtc standby flag is 0x0, super standby flag is 0x0                                                    
[4428]init dram ok    

--------------Init Called------------------
workDir	/home/any/mpu/t113s3/sunxi-livesuite-master/x86-64/LiveSuit
ImgLenHigh	0
ImgLenLow	141215744
Mode	8
hWnd	0
imgFilePath	/home/any/mpu/t113s3/sdk_2_1/tina-d1-2.1/out/t113-nezha/tina_t113-nezha_uart0.img
[TL_MSG]:Mode = 8, ImgLenHigh=0, ImgLenLow = 86ac800, imgFilePath = /home/any/mpu/t113s3/sdk_2_1/tina-d1-2.1/out/t113-nezha/tina_t113-nezha_uart0.img

IMAGEWTY
ItemTableSize = 1048576
[TL_MSG]:Tools Open Img

---fun end---
--------------entry-fel2fes Called-----------
felDevName	/dev/aw_efex0
[TL_MSG]:Hi, I'm fel, dev=/dev/aw_efex0

[TL_MSG]:To down and Run fes1-1

[TL_MSG]:fes1 down addr = 0x28000, retAddr =0x28340

[TL_MSG]:tlFelDev.FelRun finish

[TL_MSG]:hasRetLog finish

[TL_MSG]:Tools_Buffer finish

[TL_FEX]:fel UP addr=0x28340, len=136

Fex_Send error: 没有那个设备
Fex_transmit_receive Error: ./eFexCore.cpp, 318
Fex_command Error ./eFexCore.cpp 409
[TL_FEX]:fexCdmRet = 200

<TL_ERR>:usbtool.lua_1951>:FAil to UP fes aide log area, times=1

<TL_ERR>:usbtool.lua_3471>:fes1-1 failed

L225, Exception, returned value of Tools.entry_fel2fes is error.
FelThreadEntry g_Tools_if->Fel2Fes 227

[01:45:45.257]收←◆->
\0
[01:45:45.380]收←◆
boot rom try normal boot start!
\0
[01:45:45.464]收←◆Start power on debounce. Delay=500

[01:45:45.964]收←◆

(E) Welcome to EiGENCOM D-Fota Time!
 ___      _____ ___
[01:45:46.011]收←◆ _____  _        
| _ \    |  ___/ _ \_   _|/ \      
|| \| -- | |_  || || | | / _ \      
||_/| -- |  _| ||_|| | |/ ___ \     
|___/    |_|   \___/ |_/_/   \_\  

(C) Copyright 2020, All Rights Reserved.
(V) Version(2.5), Built @Dec 18 2023 10:21:59

uart(1) urc baud: 115200
total length(40): 
[1/1] ffffff3feeffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
no par(0xffff) found!
exit...
bootloader flashXIPLimit(0x809a90), try normal boot system start!
[01:45:46.080]收←◆?郔恇*゛ (傴:0 :!  ? !*0* @!｀p!€
B
[01:45:46.164]收←◆郻0?郻聵1#?1t?`"?0娿酭?€0i?8?($鴕` (\0?悁# ?狲 溤?? <!肎豇0??!r鼝20`d?`j儼" ?!俰4!!?""倻"醼*??    ??ⅳ€?*??(2#c ?`(\0? ?!?\0h翇??(?8)"皃炔1?2"?\"(+箙)C0!3? ??俼€)0'饍"瞏€( !?"?
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(E) Welcome to EiGENCOM D-Fota Time!
 ___      _____ ___ _____  _        
| _ \    |  ___/ _ \_   _|/ \      
|| \| -- | |_  || || | | / _ \      
||_/| -- |  _| ||_|| | |/ ___ \     
|___/    |_|   \___/ |_/_/   \_\  

(C) Copyright 2020, All Rights Reserved.
(V) Version(2.5), Built @Dec 18 2023 10:21:59

uart(1) urc baud: 115200
total length(40): 
[1/1] ffffff3feeffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
no par(0xffff) found!
exit...
bootloader flashXIPLimit(0x809a90), try normal boot system start!
[01:49:41.136]收←◆@鳬?#(1竝`h"?€" $$r(1!`q??(1殹
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[01:49:41.378]收←◆ 篌蝥?怿
[01:49:41.410]收←◆筱螓??篁篼簋簋?赈!桠?颃!聩鵼 t?嗖惛冢\0?0?" 鋋?€?!xia爳)$\0"%a*!? 2 t凙癓@\0
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[01:49:41.641]收←◆ 瘘x)狳狴1???狴豉?騬
[01:49:41.679]收←◆#膱?!'1)q"??H皠? ` hJ1t( E乣 ?!
 0 逍唷s      ? 7 R\0!(?亨 b!b 0	!x#D\0") 幝 d"Z凫q鴵癭&1xY0 p\0
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            /* bt_rst_n      = <&pio PE 13 GPIO_ACTIVE_LOW>; */

   /* usb_id_gpio = <&pio PE 12 GPIO_ACTIVE_HIGH>; */

[30]HELLO! BOOT0 is starting!
[33]BOOT0 commit : 88480af-dirty
[36]set pll start
[42]periph0 has been enabled
[45]set pll end
[46][pmu]: bus read error
[49]board init ok
[51]ZQ value = 0x2f
[52]get_pmu_exist() = -1
[55]DRAM BOOT DRIVE INFO: V0.33
[58]DRAM CLK = 936 MHz
[60]DRAM Type = 3 (2:DDR2,3:DDR3)
[63]DRAMC read ODT  off.
[65]DRAM ODT value: 0x42.
[68]ddr_efuse_type: 0xa
[71]DRAM SIZE =128 M
[73]dram_tpr4:0x0
[75]PLL_DDR_CTRL_REG:0xf8004d00
[78]DRAM_CLK_REG:0xc0000000
[80][TIMING DEBUG] MR2= 0x20
[88]DRAM simple test OK.
[90]rtc standby flag is 0x0, super standby flag is 0x0
[95]dram size =128
[98]card no is 2
[100]sdcard 2 line count 4
[102][mmc]: mmc driver ver 2021-05-21 14:47
[112][mmc]: Wrong media type 0x0, but host sdc2, try mmc first
[117][mmc]: ***Try MMC card 2***
[140][mmc]: RMCA OK!
[142][mmc]: mmc 2 bias 0
[154][mmc]: MMC 5.1
[156][mmc]: HSSDR52/SDR25 4 bit
[159][mmc]: 50000000 Hz
[161][mmc]: 3700 MB
[163][mmc]: ***SD/MMC 2 init OK!!!***
[234]Loading boot-pkg Succeed(index=0).
[238]Entry_name        = u-boot
[243]Entry_name        = optee
[247]Entry_name        = dtb
[250]tunning data addr:0x430003e8
[253]Jump to second Boot.
M/TC: OP-TEE version: 6aef7bb2-dirty (gcc version 5.3.1 20160412 (Linaro GCC 5.3-2016.05)) #1 Fri Jul 23 09:25:                                                                                                        m


U-Boot 2018.07-ge987def5-dirty (Nov 27 2024 - 10:42:25 +0800) Allwinner Technology

[00.307]CPU:   Allwinner Family
[00.309]Model: sun8iw20
I2C:   FDT ERROR:fdt_set_all_pin:[twi0]-->FDT_ERR_BADPATH
FDT ERROR:fdt_set_all_pin:[twi1]-->FDT_ERR_BADPATH
ready
[00.331]DRAM:  128 MiB
[00.334]Relocation Offset is: 04eff000
[00.353]secure enable bit: 0
[00.356]smc_tee_inform_fdt failed with: ffff000a
[00.362]CPU=1008 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz  MBus=300Mhz
[00.368]gic: sec monitor mode
sunxi flash map init
[00.373]flash init start
[00.375]workmode = 0,storage type = 2
[00.378][mmc]: mmc driver ver uboot2018:2021-12-20 13:35:00
[00.385][mmc]: SUNXI SDMMC Controller Version:0x50310
[00.413][mmc]: Best spd md: 2-HSDDR52/DDR50, freq: 2-50000000, Bus width: 4
[00.420]sunxi flash init ok
[00.425]Loading Environment from SUNXI_FLASH... OK
[00.439]Item0 (Map) magic is bad
[00.442]the secure storage item0 copy0 magic is bad
[00.446]Item0 (Map) magic is bad
[00.449]the secure storage item0 copy1 magic is bad
[00.454]Item0 (Map) magic is bad
secure storage read widevine fail
[00.460]secure storage read widevine fail with:-1
secure storage read ec_key fail
[00.467]secure storage read ec_key fail with:-1
secure storage read ec_cert1 fail
[00.474]secure storage read ec_cert1 fail with:-1
secure storage read ec_cert2 fail
[00.482]secure storage read ec_cert2 fail with:-1
secure storage read ec_cert3 fail
[00.489]secure storage read ec_cert3 fail with:-1
secure storage read rsa_key fail
[00.496]secure storage read rsa_key fail with:-1
secure storage read rsa_cert1 fail
[00.504]secure storage read rsa_cert1 fail with:-1
secure storage read rsa_cert2 fail
[00.512]secure storage read rsa_cert2 fail with:-1
secure storage read rsa_cert3 fail
[00.519]secure storage read rsa_cert3 fail with:-1
[00.524]out of usb burn from boot: not need burn key
root_partition is rootfs
set root to /dev/mmcblk0p5
[00.533]update part info
[00.536]update bootcmd
[00.538]change working_fdt 0x43ebee70 to 0x43e9ee70
[00.543][mmc]: no mmc-hs400-1_8v!
[00.546][mmc]: delete mmc-hs200-1_8v from dtb
[00.550][mmc]: get max-frequency ok 50000000 Hz
disable nand error: FDT_ERR_BADPATH
[00.568]update dts
Hit any key to stop autoboot:  0 
[05.667]no vendor_boot partition is found
Android's image name: t113-nezha
[05.679]Starting kernel ...

[05.681][mmc]: mmc exit start
[05.698][mmc]: mmc 2 exit ok

=> printenv
boot_dsp0=sunxi_flash read 45000000 ${dsp0_partition};bootr 45000000 0 0
boot_fastboot=fastboot
boot_normal=sunxi_flash read 45000000 ${boot_partition};bootm 45000000
boot_partition=boot
boot_recovery=sunxi_flash read 45000000 recovery;bootm 45000000
bootcmd=run setargs_mmc boot_normal
bootdelay=5
cma=8M
console=ttyS0,115200
dsp0_partition=dsp0
earlyprintk=sunxi-uart,0x02500000
fdtcontroladdr=43ebee70
force_normal_boot=1
init=/pseudo_init
initcall_debug=0
keybox_list=widevine,ec_key,ec_cert1,ec_cert2,ec_cert3,rsa_key,rsa_cert1,rsa_cert2,rsa_cert3
loglevel=8
mmc_root=/dev/mmcblk0p5
mtd_name=sys
mtdids=
mtdparts=
nand_root=/dev/ubiblock0_5
partition=
partitions=boot-resource@mmcblk0p1:env@mmcblk0p2:env-redund@mmcblk0p3:boot@mmcblk0p4:rootfs@mmcblk0p5:private@m                                                                                                        8
root_partition=rootfs
rootfstype=ext4
setargs_mmc=setenv  bootargs earlyprintk=${earlyprintk} clk_ignore_unused initcall_debug=${initcall_debug} cons                                                                                                        1
setargs_nand=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} clk_i                                                                                                        1
setargs_nand_ubi=setenv bootargs ubi.mtd=${mtd_name} ubi.block=0,${root_partition} earlyprintk=${earlyprintk} c                                                                                                        1

Environment size: 2005/131067 bytes

[30]HELLO! BOOT0 is starting!                                                 
[33]BOOT0 commit : 88480af-dirty                                                                            
[36]set pll start                                                                                           
[42]periph0 has been enabled                                                                                
[45]set pll end                                                                                             
[46][pmu]: bus read error                                                                                   
[49]board init ok                                                                                           
[51]ZQ value = 0x2f                                                                                         
[52]get_pmu_exist() = -1                                                                                    
[55]DRAM BOOT DRIVE INFO: V0.33                                                                             
[58]DRAM CLK = 936 MHz                                                                                      
[60]DRAM Type = 3 (2:DDR2,3:DDR3)                                                                           
[63]DRAMC read ODT  off.                                                                                    
[65]DRAM ODT value: 0x42.                                                                                   
[68]ddr_efuse_type: 0xa                                                                                     
[71]DRAM SIZE =128 M                                                                                        
[73]dram_tpr4:0x0                                                                                           
[75]PLL_DDR_CTRL_REG:0xf8004d00                                                                             
[78]DRAM_CLK_REG:0xc0000000                                                                                 
[80][TIMING DEBUG] MR2= 0x20                                                                                
[88]DRAM simple test OK.                                                                                    
[90]rtc standby flag is 0x0, super standby flag is 0x0                                                      
[95]dram size =128                                                                                          
[98]card no is 2                                                                                            
[100]sdcard 2 line count 4                                                                                  
[102][mmc]: mmc driver ver 2021-05-21 14:47                                                                 
[111][mmc]: Wrong media type 0x0, but host sdc2, try mmc first                                              
[117][mmc]: ***Try MMC card 2***                                                                            
[140][mmc]: RMCA OK!                                                                                        
[142][mmc]: mmc 2 bias 0                                                                                    
[154][mmc]: MMC 5.1                                                                                         
[156][mmc]: HSSDR52/SDR25 4 bit                                                                             
[158][mmc]: 50000000 Hz                                                                                     
[161][mmc]: 3700 MB                                                                                         
[163][mmc]: ***SD/MMC 2 init OK!!!***                                                                       
[234]Loading boot-pkg Succeed(index=0).                                                                     
[237]Entry_name        = u-boot                                                                             
[243]Entry_name        = optee                                                                              
[247]Entry_name        = dtb                                                                                
[250]tunning data addr:0x430003e8                                                                           
[253]Jump to second Boot.                                                                                   
M/TC: OP-TEE version: 6aef7bb2-dirty (gcc version 5.3.1 20160412 (Linaro GCC 5.3-2016.05)) #1 Fri Jul 23 09m
                                                                                                            
                                                                                                            
U-Boot 2018.07-ge987def5-dirty (Nov 27 2024 - 14:56:37 +0800) Allwinner Technology                          
                                                                                                            
[00.306]CPU:   Allwinner Family                                                                             
[00.309]Model: sun8iw20                                                                                     
I2C:   FDT ERROR:fdt_set_all_pin:[twi0]-->FDT_ERR_BADPATH                                                   
FDT ERROR:fdt_set_all_pin:[twi1]-->FDT_ERR_BADPATH                                                          
ready                                                                                                       
[00.330]DRAM:  128 MiB                                                                                      
[00.334]Relocation Offset is: 04eff000                                                                      
[00.353]secure enable bit: 0                                                                                
[00.356]smc_tee_inform_fdt failed with: ffff000a                                                            
[00.361]CPU=1008 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz  MBus=300Mhz                                     
[00.367]gic: sec monitor mode                                                                               
sunxi flash map init                                                                                        
[00.372]flash init start                                                                                    
[00.374]workmode = 0,storage type = 2                                                                       
[00.378][mmc]: mmc driver ver uboot2018:2021-12-20 13:35:00                                                 
[00.384][mmc]: SUNXI SDMMC Controller Version:0x50310                                                       
[00.413][mmc]: Best spd md: 2-HSDDR52/DDR50, freq: 2-50000000, Bus width: 4                                 
[00.420]sunxi flash init ok                                                                                 
[00.425]Loading Environment from SUNXI_FLASH... OK                                                          
[00.439]Item0 (Map) magic is bad                                                                            
[00.441]the secure storage item0 copy0 magic is bad                                                         
[00.446]Item0 (Map) magic is bad                                                                            
[00.449]the secure storage item0 copy1 magic is bad                                                         
[00.454]Item0 (Map) magic is bad                                                                            
secure storage read widevine fail                                                                           
[00.460]secure storage read widevine fail with:-1                                                           
secure storage read ec_key fail                                                                             
[00.467]secure storage read ec_key fail with:-1                                                             
secure storage read ec_cert1 fail                                                                           
[00.474]secure storage read ec_cert1 fail with:-1                                                           
secure storage read ec_cert2 fail                                                                           
[00.482]secure storage read ec_cert2 fail with:-1                                                           
secure storage read ec_cert3 fail                                                                           
[00.489]secure storage read ec_cert3 fail with:-1                                                           
secure storage read rsa_key fail                                                                            
[00.496]secure storage read rsa_key fail with:-1                                                            
secure storage read rsa_cert1 fail                                                                          
[00.504]secure storage read rsa_cert1 fail with:-1                                                          
secure storage read rsa_cert2 fail                                                                          
[00.511]secure storage read rsa_cert2 fail with:-1                                                          
secure storage read rsa_cert3 fail                                                                          
[00.519]secure storage read rsa_cert3 fail with:-1                                                          
[00.524]out of usb burn from boot: not need burn key                                                        
root_partition is rootfs                                                                                    
set root to /dev/mmcblk0p5                                                                                  
[00.533]update part info                                                                                    
[00.536]update bootcmd                                                                                      
[00.538]change working_fdt 0x43ebee70 to 0x43e9ee70                                                         
[00.543][mmc]: no mmc-hs400-1_8v!                                                                           
[00.546][mmc]: delete mmc-hs200-1_8v from dtb                                                               
[00.550][mmc]: get max-frequency ok 50000000 Hz                                                             
disable nand error: FDT_ERR_BADPATH                                                                         
[00.568]update dts                                                                                          
Hit any key to stop autoboot:  0                                                                            
[01.659]no vendor_boot partition is found                                                                   
Android's image name: t113-nezha                                                                            
[01.670]Starting kernel ...                                                                                 
                                                                                                            
[01.673][mmc]: mmc exit start                                                                               
[01.690][mmc]: mmc 2 exit ok                                                                                
[    0.000000] Booting Linux on physical CPU 0x0                                                            
[    0.000000] Linux version 5.4.61 (any@Any-PC) (arm-openwrt-linux-muslgnueabi-gcc.bin (OpenWrt/Linaro GCC4
[    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d                              
[    0.000000] CPU: div instructions available: patching division code                                      
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache                     
[    0.000000] OF: fdt: Machine model: sun8iw20                                                             
[    0.000000] printk: bootconsole [earlycon0] enabled                                                      
[    0.000000] Memory policy: Data cache writealloc                                                         
[    0.000000] cma: Reserved 8 MiB at 0x47800000                                                            
[    0.000000] On node 0 totalpages: 32768                                                                  
[    0.000000]   Normal zone: 256 pages used for memmap                                                     
[    0.000000]   Normal zone: 0 pages reserved                                                              
[    0.000000]   Normal zone: 32768 pages, LIFO batch:7                                                     
[    0.000000] psci: probing for conduit method from DT.                                                    
[    0.000000] psci: PSCIv1.0 detected in firmware.                                                         
[    0.000000] psci: Using standard PSCI v0.2 function IDs                                                  
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.                                                       
[    0.000000] psci: SMC Calling Convention v1.0                                                            
[    0.000000] percpu: Embedded 15 pages/cpu s30348 r8192 d22900 u61440                                     
[    0.000000] pcpu-alloc: s30348 r8192 d22900 u61440 alloc=15*4096                                         
[    0.000000] pcpu-alloc: [0] 0 [0] 1                                                                      
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32512                                 
[    0.000000] Kernel command line: earlyprintk=sunxi-uart,0x02500000 clk_ignore_unused initcall_debug=0 co 
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)                       
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)                         
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off                                      
[    0.000000] Memory: 109652K/131072K available (6144K kernel code, 254K rwdata, 1484K rodata, 1024K init,)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1                                   
[    0.000000] rcu: Preemptible hierarchical RCU implementation.                                            
[    0.000000]  Tasks RCU enabled.                                                                          
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.                       
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16                                              
[    0.000000] random: get_random_bytes called from start_kernel+0x264/0x3e8 with crng_init=0               
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).                                        
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: s
[    0.000006] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns                  
[    0.008007] Switching to timer-based delay loop, resolution 41ns                                         
[    0.014184] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns     
[    0.023886] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (l)
[    0.034267] pid_max: default: 32768 minimum: 301                                                         
[    0.039015] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)                          
[    0.046348] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)                     
[    0.054665] CPU: Testing write buffer coherency: ok                                                      
[    0.059878] /cpus/cpu@0 missing clock-frequency property                                                 
[    0.065193] /cpus/cpu@1 missing clock-frequency property                                                 
[    0.070540] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000                                             
[    0.076704] Setting up static identity map for 0x40100000 - 0x40100060                                   
[    0.083365] rcu: Hierarchical SRCU implementation.                                                       
[    0.088565] smp: Bringing up secondary CPUs ...                                                          
[    0.094185] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001                                             
[    0.094303] smp: Brought up 1 node, 2 CPUs                                                               
[    0.104149] SMP: Total of 2 processors activated (96.00 BogoMIPS).                                       
[    0.110344] CPU: All CPU(s) started in SVC mode.                                                         
[    0.115414] devtmpfs: initialized                                                                        
[    0.130076] VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 5                      
[    0.138205] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000s
[    0.148069] futex hash table entries: 512 (order: 3, 32768 bytes, linear)                                
[    0.155302] pinctrl core: initialized pinctrl subsystem                                                  
[    0.161482] NET: Registered protocol family 16                                                           
[    0.167335] DMA: preallocated 256 KiB pool for atomic coherent allocations                               
[    0.203258] rtc_ccu: sunxi ccu init OK                                                                   
[    0.209320] ccu: sunxi ccu init OK                                                                       
[    0.213146] r_ccu: sunxi ccu init OK                                                                     
[    0.233999] sun6i-dma 3002000.dma-controller: sunxi dma probed                                           
[    0.241582] iommu: Default domain type: Translated                                                       
[    0.246618] sunxi iommu: irq = 24                                                                        
[    0.250832] SCSI subsystem initialized                                                                   
[    0.254790] usbcore: registered new interface driver usbfs                                               
[    0.260352] usbcore: registered new interface driver hub                                                 
[    0.265739] usbcore: registered new device driver usb                                                    
[    0.271613] Advanced Linux Sound Architecture Driver Initialized.                                        
[    0.278432] Bluetooth: Core ver 2.22                                                                     
[    0.282073] NET: Registered protocol family 31                                                           
[    0.286519] Bluetooth: HCI device and connection manager initialized                                     
[    0.292925] Bluetooth: HCI socket layer initialized                                                      
[    0.297798] Bluetooth: L2CAP socket layer initialized                                                    
[    0.302865] Bluetooth: SCO socket layer initialized                                                      
[    0.308010] pwm module init!                                                                             
[    0.312054] g2d 5410000.g2d: Adding to iommu group 0                                                     
[    0.317317] G2D: rcq version initialized.major:252                                                       
[    0.322868] clocksource: Switched to clocksource arch_sys_counter                                        
[    0.337301] sun8iw20-pinctrl 2000000.pinctrl: initialized sunXi PIO driver                               
[    0.346605] NET: Registered protocol family 2                                                            
[    0.351522] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)              
[    0.359946] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)                      
[    0.367643] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear)                             
[    0.374747] TCP: Hash tables configured (established 1024 bind 1024)                                     
[    0.381194] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)                                   
[    0.387775] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)                              
[    0.394967] NET: Registered protocol family 1                                                            
[    0.400265] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pc not found, using dummy regulr
[    0.410577] spi spi0: spi0 supply spi not found, using dummy regulator                                   
[    0.417298] sunxi_spi_resource_get()2438 - [spi0] SPI MASTER MODE                                        
[    0.423461] sunxi_spi_resource_get()2476 - Failed to get sample mode                                     
[    0.429822] sunxi_spi_resource_get()2481 - Failed to get sample delay                                    
[    0.436277] sunxi_spi_resource_get()2485 - sample_mode:-1431633921 sample_delay:-1431633921              
[    0.444703] sunxi_spi_clk_init()2527 - [spi0] mclk 100000000                                             
[    0.450956] sunxi_spi_probe()2978 - [spi0]: driver probe succeed, base c881f000, irq 41                  
[    0.460525] workingset: timestamp_bits=30 max_order=15 bucket_order=0                                    
[    0.471877] squashfs: version 4.0 (2009/01/31) Phillip Lougher                                           
[    0.477898] ntfs: driver 2.1.32 [Flags: R/W].                                                            
[    0.511002] io scheduler mq-deadline registered                                                          
[    0.515564] io scheduler kyber registered                                                                
[    0.520592] [DISP]disp_module_init                                                                       
[    0.524569] disp 5000000.disp: Adding to iommu group 0                                                   
[    0.530243] [DISP] parser_disp_init_para,line:1430:                                                      
[    0.530247] of_property_read fb0_width fail                                                              
[    0.550519] disp 5000000.disp: 5000000.disp supply vcc-lcd not found, using dummy regulator              
[    0.559092] disp 5000000.disp: 5000000.disp supply vcc-pd not found, using dummy regulator               
[    0.572289] [DISP] disp_sys_pwm_request,line:442:                                                        
[    0.572294] disp_sys_pwm_request pwm 8 fail! -517                                                        
[    0.581720] [DISP] disp_sys_pwm_config,line:509:                                                         
[    0.581723] disp_sys_pwm_Config, handle is NULL!                                                         
[    0.591394] display_fb_request,fb_id:0                                                                   
[    0.595407] [DISP] Fb_copy_boot_fb,line:1445:                                                            
[    0.595411] no boot_fb0                                                                                  
[    0.602627] disp_al_manager_apply ouput_type:0                                                           
[    0.607601] [DISP]disp_module_init finish                                                                
[    0.612414] [DISP] lcd_clk_config,line:774:                                                              
[    0.612425] disp 0, clk: pll(114000000),clk(114000000),dclk(19000000) dsi_rate(114000000)                
[    0.612425]      clk real:pll(288000000),clk(288000000),dclk(24000000) dsi_rate(0)                       
[    0.612722] sunxi_sid_init()783 - insmod ok                                                              
[    0.616688] [DISP] disp_sys_pwm_request,line:442:                                                        
[    0.616692] disp_sys_pwm_request pwm 8 fail! -517                                                        
[    0.633579] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pe not found, using dummy regulr
[    0.636671] [DISP] disp_sys_pwm_config,line:509:                                                         
[    0.636673] disp_sys_pwm_Config, handle is NULL!                                                         
[    0.641700] uart uart0: uart0 supply uart not found, using dummy regulator                               
[    0.646108] [DISP] disp_sys_pwm_set_polarity,line:528:                                                   
[    0.646112] disp_sys_pwm_Set_Polarity, handle is NULL!                                                   
[    0.682642] uart0: ttyS0 at MMIO 0x2500000 (irq = 34, base_baud = 1500000) is a SUNXI                    
[    0.690545] sw_console_setup()1807 - console setup baud 115200 parity n bits 8, flow n                   
[    0.698526] printk: console [ttyS0] enabled                                                              
[    0.698526] printk: console [ttyS0] enabled                                                              
[    0.707401] printk: bootconsole [earlycon0] disabled                                                     
[    0.707401] printk: bootconsole [earlycon0] disabled                                                     
[    0.718734] misc dump reg init                                                                           
[    0.723315] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pg not found, using dummy regulr
[    0.734524] sunxi-rfkill soc@3000000:rfkill@0: module version: v1.0.9                                    
[    0.741764] sunxi-rfkill soc@3000000:rfkill@0: get gpio chip_en failed                                   
[    0.749118] sunxi-rfkill soc@3000000:rfkill@0: get gpio power_en failed                                  
[    0.756557] sunxi-rfkill soc@3000000:rfkill@0: wlan_busnum (1)                                           
[    0.763114] sunxi-rfkill soc@3000000:rfkill@0: Missing wlan_power.                                       
[    0.770060] sunxi-rfkill soc@3000000:rfkill@0: wlan clock[0] (32k-fanout1)                               
[    0.777818] sunxi-rfkill soc@3000000:rfkill@0: wlan_regon gpio=204 assert=1                              
[    0.785682] sunxi-rfkill soc@3000000:rfkill@0: wlan_hostwake gpio=202 assert=1                           
[    0.793813] sunxi-rfkill soc@3000000:rfkill@0: wakeup source is enabled                                  
[    0.801437] sunxi-rfkill soc@3000000:rfkill@0: Missing bt_power.                                         
[    0.808214] sunxi-rfkill soc@3000000:rfkill@0: bt clock[0] (32k-fanout1)                                 
[    0.815763] sunxi-rfkill soc@3000000:rfkill@0: bt_rst gpio=141 assert=0                                  
[    0.823768] [ADDR_MGT] addr_mgt_probe: module version: v1.0.11                                           
[    0.830930] [ADDR_MGT] addr_mgt_probe: success.                                                          
[    0.836313] dma-buf: Running sanitycheck                                                                 
[    0.840710] dma-buf: Running dma_fence                                                                   
[    0.844971] sizeof(dma_fence)=48                                                                         
[    0.848682] dma-buf: Running dma_fence/sanitycheck                                                       
[    0.854081] dma-buf: Running dma_fence/test_signaling                                                    
[    0.859745] dma-buf: Running dma_fence/test_add_callback                                                 
[    0.865742] dma-buf: Running dma_fence/test_late_add_callback                                            
[    0.872187] dma-buf: Running dma_fence/test_rm_callback                                                  
[    0.878067] dma-buf: Running dma_fence/test_late_rm_callback                                             
[    0.884428] dma-buf: Running dma_fence/test_status                                                       
[    0.889799] dma-buf: Running dma_fence/test_error                                                        
[    0.895085] dma-buf: Running dma_fence/test_wait                                                         
[    0.900263] dma-buf: Running dma_fence/test_wait_timeout                                                 
[    0.942879] dma-buf: Running dma_fence/test_stub                                                         
[    0.948075] dma-buf: Running dma_fence/race_signal_callback                                              
[    1.022884] thread_signal_callback[0] completed 36031 passes, 196 misses                                 
[    1.030423] thread_signal_callback[1] completed 36038 passes, 204 misses                                 
[    1.102886] thread_signal_callback[0] completed 39420 passes, 39420 misses                               
[    1.110627] thread_signal_callback[1] completed 39379 passes, 39378 misses                               
[    1.118903] libphy: Fixed MDIO Bus: probed                                                               
[    1.124218] sun8iw20-pinctrl 2000000.pinctrl: pin PE2 already requested by 2500000.uart; cannot claim foh
[    1.136206] sun8iw20-pinctrl 2000000.pinctrl: pin-130 (4500000.eth) status -22                           
[    1.144382] sun8iw20-pinctrl 2000000.pinctrl: could not request pin 130 (PE2) from group PE2  on device l
[    1.156499] sunxi-gmac 4500000.eth: Error applying setting, reverse things back                          
[    1.164750] sunxi-gmac: probe of 4500000.eth failed with error -22                                       
[    1.171853] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver                                   
[    1.179218] sunxi-ehci: EHCI SUNXI driver                                                                
[    1.184283] get ehci1-controller wakeup-source is fail.                                                  
[    1.190241] sunxi ehci1-controller don't init wakeup source                                              
[    1.196582] [sunxi-ehci1]: probe, pdev->name: 4200000.ehci1-controller, sunxi_ehci: 0xc0b5a928, 0x:c8835d
[    1.208635] sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply drvvbus not found, usinr
[    1.221121] sunxi-ehci 4200000.ehci1-controller: 4200000.ehci1-controller supply hci not found, using dur
[    1.233304] sunxi-ehci 4200000.ehci1-controller: EHCI Host Controller                                    
[    1.240558] sunxi-ehci 4200000.ehci1-controller: new USB bus registered, assigned bus number 1           
[    1.250561] sunxi-ehci 4200000.ehci1-controller: irq 61, io mem 0x04200000                               
[    1.282895] sunxi-ehci 4200000.ehci1-controller: USB 2.0 started, EHCI 1.00                              
[    1.291529] hub 1-0:1.0: USB hub found                                                                   
[    1.295791] hub 1-0:1.0: 1 port detected                                                                 
[    1.300736] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver                                       
[    1.307721] sunxi-ohci: OHCI SUNXI driver                                                                
[    1.312693] get ohci1-controller wakeup-source is fail.                                                  
[    1.318671] sunxi ohci1-controller don't init wakeup source                                              
[    1.324941] [sunxi-ohci1]: probe, pdev->name: 4200400.ohci1-controller, sunxi_ohci: 0xc0b5abb8           
[    1.334635] sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply drvvbus not found, usinr
[    1.347137] sunxi-ohci 4200400.ohci1-controller: 4200400.ohci1-controller supply hci not found, using dur
[    1.359333] sunxi-ohci 4200400.ohci1-controller: OHCI Host Controller                                    
[    1.366616] sunxi-ohci 4200400.ohci1-controller: new USB bus registered, assigned bus number 2           
[    1.379560] sunxi-ohci 4200400.ohci1-controller: irq 62, io mem 0x04200400                               
[    1.457656] hub 2-0:1.0: USB hub found                                                                   
[    1.461906] hub 2-0:1.0: 1 port detected                                                                 
[    1.466984] i2c /dev entries driver                                                                      
[    1.470971] sunxi cedar version 1.1                                                                      
[    1.475093] sunxi-cedar 1c0e000.ve: Adding to iommu group 0                                              
[    1.481406] VE: sunxi_cedar_probe power-domain init!!!                                                   
[    1.487266] VE: install start!!!                                                                         
[    1.487266]                                                                                              
[    1.492752] VE: cedar-ve the get irq is 42                                                               
[    1.492752]                                                                                              
[    1.499209] VE: ve_debug_proc_info:(ptrval), data:(ptrval), lock:(ptrval)                                
[    1.499209]                                                                                              
[    1.508503] VE: install end!!!                                                                           
[    1.508503]                                                                                              
[    1.513593] VE: sunxi_cedar_probe                                                                        
[    1.517554] Bluetooth: HCI UART driver ver 2.3                                                           
[    1.522539] Bluetooth: HCI UART protocol H4 registered                                                   
[    1.528322] Bluetooth: HCI UART protocol BCSP registered                                                 
[    1.534576] Bluetooth: XRadio Bluetooth LPM Mode Driver Ver 1.0.10                                       
[    1.542508] sun8iw20-pinctrl 2000000.pinctrl: pin PC2 already requested by 4025000.spi; cannot claim forc
[    1.554542] sun8iw20-pinctrl 2000000.pinctrl: pin-66 (4022000.sdmmc) status -22                          
[    1.562745] sun8iw20-pinctrl 2000000.pinctrl: could not request pin 66 (PC2) from group PC2  on device 2l
[    1.574764] sunxi-mmc 4022000.sdmmc: Error applying setting, reverse things back                         
[    1.583103] sunxi-mmc: probe of 4022000.sdmmc failed with error -22                                      
[    1.591116] sunxi-mmc 4020000.sdmmc: SD/MMC/SDIO Host Controller Driver(v4.25 2022-6-21 13:40)           
[    1.601006] sunxi-mmc 4020000.sdmmc: ***ctl-spec-caps*** 8                                               
[    1.607214] sunxi-mmc 4020000.sdmmc: No vmmc regulator found                                             
[    1.613576] sunxi-mmc 4020000.sdmmc: No vqmmc regulator found                                            
[    1.620020] sunxi-mmc 4020000.sdmmc: No vdmmc regulator found                                            
[    1.626477] sunxi-mmc 4020000.sdmmc: No vd33sw regulator found                                           
[    1.633030] sunxi-mmc 4020000.sdmmc: No vd18sw regulator found                                           
[    1.639571] sunxi-mmc 4020000.sdmmc: No vq33sw regulator found                                           
[    1.646122] sunxi-mmc 4020000.sdmmc: No vq18sw regulator found                                           
[    1.653103] sunxi-mmc 4020000.sdmmc: Got CD GPIO                                                         
[    1.658466] sunxi-mmc 4020000.sdmmc: set cd-gpios as 24M fail                                            
[    1.665119] sunxi-mmc 4020000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12)B
[    1.676301] sunxi-mmc 4020000.sdmmc: no vqmmc,Check if there is regulator                                
[    1.696461] sunxi-mmc 4020000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SB
[    1.720873] sunxi-mmc 4020000.sdmmc: detmode:gpio irq                                                    
[    1.726604] sunxi-mmc 4020000.sdmmc: sdc set ios:clk 0Hz bm PP pm OFF vdd 0 width 1 timing LEGACY(SDR12)B
[    1.738216] sunxi-mmc 4021000.sdmmc: SD/MMC/SDIO Host Controller Driver(v4.25 2022-6-21 13:40)           
[    1.748096] sunxi-mmc 4021000.sdmmc: ***ctl-spec-caps*** 8                                               
[    1.754311] sunxi-mmc 4021000.sdmmc: No vmmc regulator found                                             
[    1.760659] sunxi-mmc 4021000.sdmmc: No vqmmc regulator found                                            
[    1.767117] sunxi-mmc 4021000.sdmmc: No vdmmc regulator found                                            
[    1.773572] sunxi-mmc 4021000.sdmmc: No vd33sw regulator found                                           
[    1.780113] sunxi-mmc 4021000.sdmmc: No vd18sw regulator found                                           
[    1.786666] sunxi-mmc 4021000.sdmmc: No vq33sw regulator found                                           
[    1.793218] sunxi-mmc 4021000.sdmmc: No vq18sw regulator found                                           
[    1.799776] sunxi-mmc 4021000.sdmmc: Cann't get pin bias hs pinstate,check if needed                     
[    1.809140] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12)B
[    1.820365] sunxi-mmc 4021000.sdmmc: no vqmmc,Check if there is regulator                                
[    1.840527] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SB
[    1.864764] sunxi-mmc 4021000.sdmmc: detmode:manually by software                                        
[    1.872437] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 52, RTO !!                                        
[    1.872590] sunxi_led_probe()1749 - start                                                                
[    1.883882] sunxi_get_str_of_property()1595 - failed to get the string of propname led_regulator!        
[    1.884645] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 52, RTO !!                                        
[    1.893859] sunxi_register_led_classdev()1483 - led_classdev start                                       
[    1.907625] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SB
[    1.920227] sunxi_led_probe()1845 - finish                                                               
[    1.925082] exFAT: Version 1.3.0                                                                         
[    1.926145] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SB
[    1.930597] [AUDIOCODEC][sunxi_codec_parse_params][2437]:digital_vol:0, lineout_vol:26, mic1gain:31, mic1
[    1.930597]                                                                                              
[    1.957562] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 5, RTO !!                                         
[    1.964346] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 5, RTO !!                                         
[    1.971096] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 5, RTO !!                                         
[    1.977864] sunxi-mmc 4021000.sdmmc: smc 1 p1 err, cmd 5, RTO !!                                         
[    1.977889] sunxi-mmc 4021000.sdmmc: sdc set ios:clk 0Hz bm PP pm OFF vdd 0 width 1 timing LEGACY(SDR12)B
[    1.984649] [AUDIOCODEC][sunxi_codec_parse_params][2473]:adcdrc_cfg:0, adchpf_cfg:1, dacdrc_cfg:0, dachp0
[    1.995775] [DISP] disp_sys_pwm_request,line:442:                                                        
[    1.995783] disp_sys_pwm_request pwm 8 fail! -517                                                        
[    2.007152] [AUDIOCODEC][sunxi_internal_codec_probe][2634]:codec probe finished                          
[    2.011984] [DISP] disp_lcd_pwm_enable,line:1271:                                                        
[    2.011987] pwm device hdl is NULL                                                                       
[    2.018174] debugfs: Directory '203034c.dummy_cpudai' with parent 'audiocodec' already present!          
[    2.025561] [DISP] disp_device_attached_and_enable,line:233:                                             
[    2.025566] attached ok, mgr0<-->dev0                                                                    
[    2.030865] [SNDCODEC][sunxi_card_init][583]:card init finished                                          
[    2.034652] [DISP] disp_device_attached_and_enable,line:236:                                             
[    2.034660] type:1,mode:0,fmt:rgb,bits:8bits,eotf:4,cs:0 dvi_hdmi:2, range:2 scan:0 ratio:8              
[    2.077562] sunxi-codec-machine 2030340.sound: 2030000.codec <-> 203034c.dummy_cpudai mapping ok         
[    2.088477] input: audiocodec sunxi Audio Jack as /devices/platform/soc@3000000/2030340.sound/sound/card0
[    2.100427] [SNDCODEC][sunxi_card_dev_probe][836]:register card finished                                 
[    2.108800] NET: Registered protocol family 10                                                           
[    2.113854] [SNDCODEC][sunxi_hs_init_work][259]:resume-->report switch                                   
[    2.122088] Segment Routing with IPv6                                                                    
[    2.126324] NET: Registered protocol family 17                                                           
[    2.131469] Bluetooth: RFCOMM TTY layer initialized                                                      
[    2.137000] Bluetooth: RFCOMM socket layer initialized                                                   
[    2.142791] Bluetooth: RFCOMM ver 1.11                                                                   
[    2.147573] Registering SWP/SWPB emulation handler                                                       
[    2.167211] sun8iw20-pinctrl 2000000.pinctrl: pin PE2 already requested by 2500000.uart; cannot claim foh
[    2.179190] sun8iw20-pinctrl 2000000.pinctrl: pin-130 (4500000.eth) status -22                           
[    2.187317] sun8iw20-pinctrl 2000000.pinctrl: could not request pin 130 (PE2) from group PE2  on device l
[    2.199447] sunxi-gmac 4500000.eth: Error applying setting, reverse things back                          
[    2.207708] sunxi-gmac: probe of 4500000.eth failed with error -22                                       
[    2.214954] sun8iw20-pinctrl 2000000.pinctrl: pin PC2 already requested by 4025000.spi; cannot claim forc
[    2.226973] sun8iw20-pinctrl 2000000.pinctrl: pin-66 (4022000.sdmmc) status -22                          
[    2.235187] sun8iw20-pinctrl 2000000.pinctrl: could not request pin 66 (PC2) from group PC2  on device 2l
[    2.247196] sunxi-mmc 4022000.sdmmc: Error applying setting, reverse things back                         
[    2.255525] sunxi-mmc: probe of 4022000.sdmmc failed with error -22                                      
[    2.263933] sun8iw20-pinctrl 2000000.pinctrl: 2000000.pinctrl supply vcc-pb not found, using dummy regulr
[    2.276306] get ehci0-controller wakeup-source is fail.                                                  
[    2.282265] sunxi ehci0-controller don't init wakeup source                                              
[    2.288541] [sunxi-ehci0]: probe, pdev->name: 4101000.ehci0-controller, sunxi_ehci: 0xc0b5a408, 0x:c88b8b
[    2.300557] [sunxi-ehci0]: Not init ehci0                                                                
[    2.305397] get ohci0-controller wakeup-source is fail.                                                  
[    2.311345] sunxi ohci0-controller don't init wakeup source                                              
[    2.317648] [sunxi-ohci0]: probe, pdev->name: 4101400.ohci0-controller, sunxi_ohci: 0xc0b5a698           
[    2.327323] [sunxi-ohci0]: Not init ohci0                                                                
[    2.332525] otg manager soc@3000000:usbc0@0: soc@3000000:usbc0@0 supply usbc not found, using dummy regur
[    2.346128] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2           
[    2.355863] cfg80211: failed to load regulatory.db                                                       
[    2.355877] clk: Not disabling unused clocks                                                             
[    2.366051] ALSA device list:                                                                            
[    2.369377]   #0: audiocodec                                                                             
[    2.372610] alloc_fd: slot 0 not NULL!                                                                   
[    2.377191] VFS: Cannot open root device "mmcblk0p5" or unknown-block(0,0): error -6                     
[    2.385895] Please append a correct "root=" boot option; here are the available partitions:              
[    2.395290] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)               
[    2.404568] CPU1: stopping                                                                               
[    2.407605] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.4.61 #36                                         
[    2.414339] Hardware name: Generic DT based system                                                       
[    2.419733] [<c010de6c>] (unwind_backtrace) from [<c010a614>] (show_stack+0x10/0x14)                     
[    2.428430] [<c010a614>] (show_stack) from [<c062be28>] (dump_stack+0x88/0xa4)                           
[    2.436537] [<c062be28>] (dump_stack) from [<c010c254>] (handle_IPI+0xe4/0x180)                          
[    2.444742] [<c010c254>] (handle_IPI) from [<c0316614>] (gic_handle_irq+0x70/0x78)                       
[    2.453238] [<c0316614>] (gic_handle_irq) from [<c01021cc>] (__irq_svc+0x6c/0xa8)                        
[    2.461630] Exception stack(0xc705df80 to 0xc705dfc8)                                                    
[    2.467298] df80: 00000400 c76c7334 00000000 c01147a0 00000002 c705c000 c0a03de8 c0a03e24                
[    2.476474] dfa0: 4000406a 410fc075 00000000 00000000 c0b46748 c705dfd0 c0107f68 c0107f58                
[    2.485646] dfc0: 60000013 ffffffff                                                                      
[    2.489562] [<c01021cc>] (__irq_svc) from [<c0107f58>] (arch_cpu_idle+0x1c/0x38)                         
[    2.497864] [<c0107f58>] (arch_cpu_idle) from [<c013d43c>] (do_idle+0xd4/0x128)                          
[    2.506067] [<c013d43c>] (do_idle) from [<c013d728>] (cpu_startup_entry+0x18/0x20)                       
[    2.514561] [<c013d728>] (cpu_startup_entry) from [<40102bac>] (0x40102bac)                              
[    2.522381] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) ]---

Lunch menu... pick a combo:
     1	t113-awol_evb1-tina
     2	t113-dev-tina
     3	t113-evb1_auto_nor-tina
     4	t113-evb1_auto-tina
     5	t113-evb1-tina
     6	t113_i-evb1_auto_nand-tina
     7	t113_i-evb1_auto-tina
     8	t113-pro-tina
     9	t113s2-evb1-tina
    10	t113s2-evb_axp313a-tina
Which would you like? [Default t113__i-evb1_auto]: 

Which would you like? [Default t113_i-evb1_auto]: 5
Jump to longan autoconfig
/home/any/mpu/t113s3/myirdd/T113/build.sh autoconfig -o openwrt -i t113 -b evb1 		-n default 
========ACTION List: mk_autoconfig -o openwrt -i t113 -b evb1 -n default;========
options : 

cmake -DPCB=X10 -DPCBREV=TX16S -DDEFAULT_MODE=2 -DGVARS=YES -DPPM_UNIT=US -DLUA_MIXER=YES -DCMAKE_BUILD_TYPE=Debug ../

(edgeTxEnv) any@Any-Desktop:~/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output$ cmake -DPCB=X10 -DPCBREV=TX16S -DDEFAULT_MODE=2 -DGVARS=YES -DPPM_UNIT=US -DLUA_MIXER=YES -DCMAKE_BUILD_TYPE=Debug ../
-- CMAKE_ARGS: -DDEBUG=YES;-DDEFAULT_MODE=2;-DGVARS=YES;-DHELI=NO;-DINTERNAL_GPS=YES;-DLUA=YES;-DLUA_MIXER=YES;-DPCB=X10;-DPCBREV=TX16S;-DPPM_UNIT=US
-- CMAKE_BUILD_TYPE: Debug
-- Configuring done
-- Generating done
-- Build files have been written to: /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output
(edgeTxEnv) any@Any-Desktop:~/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output$ make configure
[ 50%] Built target arm-none-eabi-configure
[ 60%] Creating directories for 'native'
[ 70%] No download step for 'native'
[ 80%] No update step for 'native'
[ 90%] No patch step for 'native'
[100%] Performing configure step for 'native'
loading initial cache file /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native-prefix/tmp/native-cache-Debug.cmake
-- Python found, version: 3.10.12
-- EdgeTX 2.11.0-selfbuild @ e303b126
-- Foxlib found at /usr/lib/x86_64-linux-gnu/libFOX-1.6.so
-- Qt Version: 5.15.3
-- SDL2 Lib: /usr/lib/x86_64-linux-gnu/libSDL2.so Libs: -L/usr/lib/x86_64-linux-gnu  -lSDL2; Headers: /usr/include/SDL2
-- Simulators library search path: ../lib/companion211
Fetched miniz source code from Github: /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native/_deps/miniz-src
Fetched yaml-cpp source code from Github: /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native/_deps/yaml-cpp-src
-- Qt Version: 5.15.3
-- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE) 
Fetched maxLibQt source code from Github: /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native/_deps/maxlibqt-src/src
TARGET companion211: cpp compiler /usr/bin/c++ v11
-- Added optional gtests-companion target
-- install /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native to /usr
-- Downloading linuxdeploy and plugins...
-- Downloading linuxdeploy and plugins finished
mv: 对 '/home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native/squashfs-root' 调用 stat 失败: 没有那个文件或目录
-- Internal GPS enabled
-- Adding support for USB serial
-- Adding support for PXX1 as internal module
-- Adding support for PXX2 as internal module
-- Adding support for MULTI as internal module
-- Adding support for CRSF as internal module
TARGET simu/libsimulator: cpp compiler /usr/bin/c++ v11
-- Added optional gtests target
-- firmware target disabled
-- Configuring done
-- Generating done
-- Build files have been written to: /home/any/Mcu/DownloadFromWeb/edgetx/edgetx_main/build-output/native
[100%] Built target native-configure
[100%] Built target configure

void test_ui_init(void)
{
    static lv_style_t fontDefault;
    lv_style_init(&fontDefault);
    lv_style_set_text_font(&fontDefault, &lv_font_montserrat_30);

    lv_obj_t * table = lv_table_create(lv_scr_act());
    // lv_obj_add_style(table, &fontDefault, 0);
    lv_obj_set_size(table, 700, 400);

    lv_table_set_cell_value(table, 0, 0, "Name");
    lv_table_set_cell_value(table, 1, 0, "Apple");
    lv_table_set_cell_value(table, 2, 0, "Banana");
    lv_table_set_cell_value(table, 3, 0, "Lemon");
    lv_table_set_cell_value(table, 4, 0, "Grape");
    lv_table_set_cell_value(table, 5, 0, "Melon");
    lv_table_set_cell_value(table, 6, 0, "Peach");
    lv_table_set_cell_value(table, 7, 0, "Nuts");

    lv_table_set_cell_value(table, 0, 1, "Price");
    lv_table_set_cell_value(table, 1, 1, "$7");
    lv_table_set_cell_value(table, 2, 1, "$4");
    lv_table_set_cell_value(table, 3, 1, "$6");
    lv_table_set_cell_value(table, 4, 1, "$2");
    lv_table_set_cell_value(table, 5, 1, "$5");
    lv_table_set_cell_value(table, 6, 1, "$1");
    lv_table_set_cell_value(table, 7, 1, "$9");

    // lv_table_set_cell_value(table, 0, 2, "Name");
    // lv_table_set_cell_value(table, 1, 2, "Apple");
    // lv_table_set_cell_value(table, 2, 2, "Banana");
    // lv_table_set_cell_value(table, 3, 2, "Lemon");
    // lv_table_set_cell_value(table, 4, 2, "Grape");
    // lv_table_set_cell_value(table, 5, 2, "Melon");
    // lv_table_set_cell_value(table, 6, 2, "Peach");
    // lv_table_set_cell_value(table, 7, 2, "Nuts");
//
    // lv_table_set_cell_value(table, 0, 3, "Price");
    // lv_table_set_cell_value(table, 1, 3, "$7");
    // lv_table_set_cell_value(table, 2, 3, "$4");
    // lv_table_set_cell_value(table, 3, 3, "$6");
    // lv_table_set_cell_value(table, 4, 3, "$2");
    // lv_table_set_cell_value(table, 5, 3, "$5");
    // lv_table_set_cell_value(table, 6, 3, "$1");
    // lv_table_set_cell_value(table, 7, 3, "$9");

    // lv_obj_set_height(table, 200);
    lv_obj_center(table);

    lv_obj_add_event_cb(table, draw_part_event_cb, LV_EVENT_DRAW_PART_BEGIN, NULL);
}

[Warn]  (60.346, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.356, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.366, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.376, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.406, +30)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.416, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)
[Warn]  (60.426, +10)    indev_pointer_proc: X is 809 which is greater than hor. res    (in lv_indev.c line #362)

dlk /> sf probe qspi01
qspi0 freq (input): 99000000Hz
qspi0 freq ( bus ): 49500000Hz
01-01 10:14:57 I/NO_TAG: Flash ID: 0xef4018
01-01 10:14:57 I/NO_TAG: Find a Winbond flash chip. Size is 167772.
qspi0 freq (input): 99000000Hz
qspi0 freq ( bus ): 99000000Hz
01-01 10:14:57 I/NO_TAG: sf_cmd flash device is initialize success.
01-01 10:14:57 I/NO_TAG: Probe SPI flash sf_cmd by SPI device qspi.
16 MB sf_cmd is current selected device.
dlk /> sf status
The sf_cmd flash status register current value is 0x00.

dlk /> test_flashdb
dlk /> [FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1784) The oldest addr is @0x00000000
[FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1800) KVDB size is 16384 bytes.
[FlashDB] FlashDB V2.1.0 is initialize success.
[FlashDB] You can get the latest version on https://github.com/armink/FlashDB .
[FlashDB][sample][kvdb][basic] ==================== kvdb_basic_sample ====================
[FlashDB][sample][kvdb][basic] get the 'boot_count' value is 1
[FlashDB][sample][kvdb][basic] set the 'boot_count' value to 2
[FlashDB][sample][kvdb][basic] ===========================================================
[FlashDB][sample][kvdb][string] ==================== kvdb_type_string_sample ====================
[FlashDB][sample][kvdb][string] create the 'temp' string KV, value is: 36C
[FlashDB][sample][kvdb][string] get the 'temp' value is: 36C
[FlashDB][sample][kvdb][string] set 'temp' value to 38C
[FlashDB][sample][kvdb][string] delete the 'temp' finish
[FlashDB][sample][kvdb][string] ===========================================================
[FlashDB][sample][kvdb][blob] ==================== kvdb_type_blob_sample ====================
[FlashDB][sample][kvdb][blob] create the 'temp' blob KV, value is: 36
[FlashDB][sample][kvdb][blob] get the 'temp' value is: 36
[FlashDB][sample][kvdb][blob] set 'temp' value to 38
[FlashDB][sample][kvdb][blob] delete the 'temp' finish
[FlashDB][sample][kvdb][blob] ===========================================================
[FlashDB][tsl][log][/data] (packages/third-party/FlashDB/src/fdb_tsdb.c:978) TSDB (log) oldest sectors is 0x00000000, current using sector                                                                                                                                     .
[FlashDB][sample][tsdb] ==================== tsdb_sample ====================
[FlashDB][sample][tsdb] append the new status.temp (36) and status.humi (85)
[FlashDB][sample][tsdb] append the new status.temp (38) and status.humi (90)
[FlashDB][sample][tsdb] [query_cb] queried a TSL: time: 1, temp: 36, humi: 85
[FlashDB][sample][tsdb] [query_cb] queried a TSL: time: 2, temp: 38, humi: 90
[FlashDB][sample][tsdb] [query_cb] queried a TSL: time: 3, temp: 36, humi: 85
[FlashDB][sample][tsdb] [query_cb] queried a TSL: time: 4, temp: 38, humi: 90
[FlashDB][sample][tsdb] [query_by_time_cb] queried a TSL: time: 1, temp: 36, humi: 85
[FlashDB][sample][tsdb] [query_by_time_cb] queried a TSL: time: 2, temp: 38, humi: 90
[FlashDB][sample][tsdb] [query_by_time_cb] queried a TSL: time: 3, temp: 36, humi: 85
[FlashDB][sample][tsdb] [query_by_time_cb] queried a TSL: time: 4, temp: 38, humi: 90
[FlashDB][sample][tsdb] query count is: 2
[FlashDB][sample][tsdb] set the TSL (time 1) status from 3 to 3
[FlashDB][sample][tsdb] set the TSL (time 2) status from 3 to 3
[FlashDB][sample][tsdb] set the TSL (time 3) status from 2 to 3
[FlashDB][sample][tsdb] set the TSL (time 4) status from 2 to 3
[FlashDB][sample][tsdb] ===========================================================

hexdump env.fdb.0
0000000 3f3f ffff 4446 3042 ffff ffff ffff ffff
0000010 ff3f ffff 564b 3030 0026 0000 c32c b664
0000020 ff08 ffff 0006 0000 7375 7265 616e 656d
0000030 7261 696d 6b6e ff3f ffff 564b 3030 0026
0000040 0000 4c95 83fc ff08 ffff 0006 0000 6170
0000050 7373 6f77 6472 3231 3433 3635 ff0f ffff
0000060 564b 3030 0026 0000 f64e efde ff0a ffff
0000070 0004 0000 6f62 746f 635f 756f 746e 0000
0000080 0000 ff3f ffff 564b 3030 0071 0000 1dce
0000090 135c ff09 ffff 0050 0000 6f62 746f 745f
00000a0 6d69 0065 0000 0000 0000 0100 0000 0000
00000b0 0000 0200 0000 0000 0000 0300 0000 0000
00000c0 0000 0000 0000 0000 0000 0000 0000 0000
*
00000f0 0000 3f00 ffff 4bff 3056 2730 0000 a700
0000100 d62e 0b29 ffff 04ff 0000 5f00 765f 7265
0000110 6e5f 6d75 5f5f 0000 0000 ff3f ffff 564b
0000120 3030 0026 0000 912b 5762 ff0a ffff 0004
0000130 0000 6f62 746f 635f 756f 746e 0001 0000
0000140 ff0f ffff 564b 3030 001f 0000 b630 fa55
0000150 ff04 ffff 0003 0000 6574 706d 3633 0f43
0000160 ffff 4bff 3056 1f30 0000 be00 d69b 0464
0000170 ffff 03ff 0000 7400 6d65 3370 4338 ff0f
0000180 ffff 564b 3030 0020 0000 89da b6c5 ff04
0000190 ffff 0004 0000 6574 706d 0024 0000 ff0f
00001a0 ffff 564b 3030 0020 0000 4151 1ccc ff04
00001b0 ffff 0004 0000 6574 706d 0026 0000 ffff
00001c0 ffff ffff ffff ffff ffff ffff ffff ffff
*
0001000

dlk /> test_flashdb
dlk /> [FlashDB][kv][(null)

dlk /> test_flashdb
dlk /> [FlashDB][sample][kvdb][basic] ==================== kvdb_basic_sample ====================
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][basic] get the 'boot_count' value is 0
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][basic] set the 'boot_count' value to 1
[FlashDB][sample][kvdb][basic] ===========================================================
[FlashDB][sample][kvdb][string] ==================== kvdb_type_string_sample ====================
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][string] create the 'temp' string KV, value is: 36C
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][string] set 'temp' value to 38C
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][string] delete the 'temp' finish
[FlashDB][sample][kvdb][string] ===========================================================
[FlashDB][sample][kvdb][blob] ==================== kvdb_type_blob_sample ====================
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][blob] create the 'temp' blob KV, value is: 36
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][blob] get the 'temp' value is: 0
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][blob] set 'temp' value to 38
[FlashDB][kv][(null)][(null)] Error: KV ((null)) isn't initialize OK.
[FlashDB][sample][kvdb][blob] delete the 'temp' finish
[FlashDB][sample][kvdb][blob] ===========================================================
[FlashDB] Error: Partition (fdb_tsdb1) not found.
[FlashDB] Error: TSDB (log

lk /> test_flashdb
dlk /> [FlashDB] (db->sec_size != 0) has assert failed at _fdb_init_ex.

bool file_mode = true;
uint32_t sec_size = 4096, db_size = sec_size * 4;

/* set the sector and database max size */
fdb_kvdb_control(&kvdb, FDB_KVDB_CTRL_SET_SEC_SIZE, &sec_size);
fdb_kvdb_control(&kvdb, FDB_KVDB_CTRL_SET_MAX_SIZE, &db_size);
/* enable file mode */      
fdb_kvdb_control(&kvdb, FDB_KVDB_CTRL_SET_FILE_MODE, &file_mode);

dlk /> test_flashdb
dlk /> [FlashDB][kv][env][/dev/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1784) The oldest addr is @0x00000000
[FlashDB][kv][env][/dev/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1800) KVDB size is 16384 bytes.
[FlashDB][kv][env][/dev/data] Sector header info is incorrect. Auto format this sector (0x00000000).
[FlashDB][file] Error: open (/dev/data/env.fdb.0) file failed.
[FlashDB][kv][env][/dev/data] Sector header info is incorrect. Auto format this sector (0x00001000).
[FlashDB][file] Error: open (/dev/data/env.fdb.1) file failed.
[FlashDB][kv][env][/dev/data] Sector header info is incorrect. Auto format this sector (0x00002000).
[FlashDB][file] Error: open (/dev/data/env.fdb.2) file failed.
[FlashDB][kv][env][/dev/data] Sector header info is incorrect. Auto format this sector (0x00003000).
[FlashDB][file] Error: open (/dev/data/env.fdb.3) file failed.
[FlashDB][kv][env][/dev/data] All sector header is incorrect. Set it to default.
[FlashDB][file] Error: open (/dev/data/env.fdb.0) file failed.
[FlashDB] FlashDB V2.1.0 is initialize success.
[FlashDB] You can get the latest version on https://github.com/armink/FlashDB .
[FlashDB][sample][kvdb][basic] ==================== kvdb_basic_sample ====================
[FlashDB][sample][kvdb][basic] get the 'boot_count' failed
[FlashDB][sample][kvdb][basic] set the 'boot_count' value to 1
[FlashDB][sample][kvdb][basic] ===========================================================
[FlashDB][sample][kvdb][string] ==================== kvdb_type_string_sample ====================
[FlashDB][sample][kvdb][string] create the 'temp' string KV, value is: 36C
[FlashDB][sample][kvdb][string] set 'temp' value to 38C
[FlashDB][kv][env][/dev/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:954) Not found 'temp' in KV.
[FlashDB][sample][kvdb][string] delete the 'temp' finish
[FlashDB][sample][kvdb][string] ===========================================================
[FlashDB][sample][kvdb][blob] ==================== kvdb_type_blob_sample ====================
[FlashDB][sample][kvdb][blob] create the 'temp' blob KV, value is: 36
[FlashDB][sample][kvdb][blob] set 'temp' value to 38
[FlashDB][kv][env][/dev/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:954) Not found 'temp' in KV.
[FlashDB][sample][kvdb][blob] delete the 'temp' finish
[FlashDB][sample][kvdb][blob] ===========================================================
[FlashDB][tsl][log][/dev/data] Sector (0x00000000) header info is incorrect.
[FlashDB][file] Error: open (/dev/data/log.fdb.0) file failed.
[FlashDB][file] Error: open (/dev/data/log.fdb.1) file failed.
[FlashDB][file] Error: open (/dev/data/log.fdb.2) file failed.
[FlashDB][file] Error: open (/dev/data/log.fdb.3) file failed.
[FlashDB][tsl][log][/dev/data] All sector format finished.
[FlashDB][tsl][log][/dev/data] (packages/third-party/FlashDB/src/fdb_tsdb.c:978) TSDB (log) oldest sectors is 0x00000000, current using sec                                                                                                                                    .
[FlashDB][sample][tsdb] ==================== tsdb_sample ====================
[FlashDB][tsl][log][/dev/data] Error: write tsl failed (3)[FlashDB][sample][tsdb] append the new status.temp (36) and status.humi (85)
[FlashDB][tsl][log][/dev/data] Error: write tsl failed (3)[FlashDB][sample][tsdb] append the new status.temp (38) and status.humi (90)
[FlashDB][sample][tsdb] query count is: 0
[FlashDB][sample][tsdb] ===========================================================

35  /* Using file storage mode by LIBC file API, like fopen/fread/fwrte/fclose */
  1 #define FDB_USING_FILE_LIBC_MODE
  2                                                                                                      
  3 /* Using file storage mode by POSIX file API, like open/read/write/close */                          
  4 // #define FDB_USING_FILE_POSIX_MODE

dlk /> test_flashdb
dlk /> [FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1784) The oldest addr is @0x00000000
[FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:1800) KVDB size is 16384 bytes.
[FlashDB][kv][env][/data] Sector header info is incorrect. Auto format this sector (0x00000000).
[FlashDB][kv][env][/data] Sector header info is incorrect. Auto format this sector (0x00001000).
[FlashDB][kv][env][/data] Sector header info is incorrect. Auto format this sector (0x00002000).
[FlashDB][kv][env][/data] Sector header info is incorrect. Auto format this sector (0x00003000).
[FlashDB][kv][env][/data] All sector header is incorrect. Set it to default.
[FlashDB] FlashDB V2.1.0 is initialize success.
[FlashDB] You can get the latest version on https://github.com/armink/FlashDB .
[FlashDB][sample][kvdb][basic] ==================== kvdb_basic_sample ====================
[FlashDB][sample][kvdb][basic] get the 'boot_count' failed
[FlashDB][sample][kvdb][basic] set the 'boot_count' value to 1
[FlashDB][sample][kvdb][basic] ===========================================================
[FlashDB][sample][kvdb][string] ==================== kvdb_type_string_sample ====================
[FlashDB][kv][env][/data] Error: The KV @0x00000024 length has an error.
[FlashDB][sample][kvdb][string] create the 'temp' string KV, value is: 36C
[FlashDB][sample][kvdb][string] set 'temp' value to 38C
[FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:954) Not found 'temp' in KV.
[FlashDB][sample][kvdb][string] delete the 'temp' finish
[FlashDB][sample][kvdb][string] ===========================================================
[FlashDB][sample][kvdb][blob] ==================== kvdb_type_blob_sample ====================
[FlashDB][sample][kvdb][blob] create the 'temp' blob KV, value is: 36
[FlashDB][sample][kvdb][blob] set 'temp' value to 38
[FlashDB][kv][env][/data] (packages/third-party/FlashDB/src/fdb_kvdb.c:954) Not found 'temp' in KV.
[FlashDB][sample][kvdb][blob] delete the 'temp' finish
[FlashDB][sample][kvdb][blob] ===========================================================
[FlashDB][tsl][log][/data] Sector (0x00000000) header info is incorrect.
[FlashDB][tsl][log][/data] All sector format finished.
[FlashDB][tsl][log][/data] (packages/third-party/FlashDB/src/fdb_tsdb.c:978) TSDB (log) oldest sectors is 0x00000000, current using sector                                                                                                                                     .
[FlashDB][sample][tsdb] ==================== tsdb_sample ====================
[FlashDB][tsl][log][/data] Error: write tsl failed (2)[FlashDB][sample][tsdb] append the new status.temp (36) and status.humi (85)
[FlashDB][tsl][log][/data] Error: write tsl failed (2)[FlashDB][sample][tsdb] append the new status.temp (38) and status.humi (90)
[FlashDB][sample][tsdb] query count is: 0
[FlashDB][sample][tsdb] ===========================================================

dlk /> cd /data
dlk /data> ls
Directory /data:
env.fdb.0           4096                     
env.fdb.1           4096                     
env.fdb.2           4096                     
env.fdb.3           4096                     
log.fdb.0           4096                     
log.fdb.1           4096                     
log.fdb.2           4096                     
log.fdb.3           4096  

dlk /data> create_student_tbl
/data/stu_info.dbdlk /data> 
dlk /data> ls
Directory /data:
stu_info.db         12288                    
dlk /data> stu add 10
Insert 10 record(s): 1166ms, speed: 116ms/record
dlk /data> stu
test get all students
id:1    name:Student44408       score:40
id:2    name:Student44409       score:41
id:3    name:Student44411       score:43
id:4    name:Student44414       score:46
id:5    name:Student44418       score:50
id:6    name:Student44423       score:55
id:7    name:Student44429       score:61
id:8    name:Student44436       score:68
id:9    name:Student44444       score:76
id:10   name:Student44453       score:85
record(s):10
dlk /data> stu score 40 60

bind failed errmsg:database disk image is malformed

dlk /> df /rodata                                                               
disk free: 4.8 MB [ 9968 block, 512 bytes per block ]                           
dlk /> df /data                                                                 
disk free: 6.8 MB [ 1764 block, 4096 bytes per block ]                          
dlk /> create_student_tbl                                                       
/rodata/stu_info.db

static int create_student_tbl(void)
{
    int fd = 0;

    db_set_name("/data/stu_info.db");
    fd = open(db_get_name(), O_RDONLY);
    rt_kprintf(db_get_name());
    if (fd < 0)
    {
        /* there is not the .db file.create db and table */
        const char *sql = "CREATE TABLE student(id INTEGER PRIMARY KEY AUTOINCREMENT,name varchar(32) NOT NULL,score INT NOT NULL);";
        return db_create_database(sql);
    }
    else if (db_table_is_exist("student") > 0)
    {
        /* there is the table int db.close the db. */
        close(fd);
        LOG_I("The table has already existed!\n");
        return RT_EOK;
    }
    else
    {
        /* there is not the table int db.create the table */
        const char *sql = "CREATE TABLE student(id INTEGER PRIMARY KEY AUTOINCREMENT,name varchar(32) NOT NULL,score INT NOT NULL);";
        return db_create_database(sql);
    }
}
MSH_CMD_EXPORT(create_student_tbl, create sqlite db);

    //enable CAN TX interrupt
    rt_device_control(can_tx_dev, RT_DEVICE_CTRL_SET_INT, NULL);

    // disp_drv.rotated = LV_DISP_ROT_180;

> Board options > Display Parameter ────────────────────────────────

┌───────────────── framebuffer rotation degree ─────────────────┐
│  Use the arrow keys to navigate this window or press the      │  
│  hotkey of the item you wish to select followed by the <SPACE │  
│  BAR>. Press <?> for additional information about this        │  
│ ┌───────────────────────────────────────────────────────────┐ │  
│ │                          (X) 0                            │ │  
│ │                          ( ) 90                           │ │  
│ │                          ( ) 180                          │ │  
│ │                          ( ) 270                          │ │  
│ │                                                           │ │  
│ │                                                           │ │  
│ └───────────────────────────────────────────────────────────┘ │  
├───────────────────────────────────────────────────────────────┤  
│                    <Select>      < Help >                     │  
└───────────────────────────────────────────────────────────────┘  
                                                                                                      

irqreturn_t hal_can_isr_handler(int irq_num, void *arg)
{
    u32 int_status;
    can_handle *phandle = (can_handle *)arg;

    int_status = readl(phandle->can_base + CAN_INTR_REG);

    if (int_status & (CAN_INTR_ERRB | CAN_INTR_ARBLOST | CAN_INTR_ERRP |
                CAN_INTR_WAKEUP | CAN_INTR_OVF | CAN_INTR_ERRW))
        hal_can_error_handle(phandle, int_status);

    if (int_status & CAN_INTR_TX) {
        phandle->status.sndpkgcnt++;
        if (phandle->callback)
            phandle->callback(phandle, (void *)CAN_EVENT_TX_DONE);
    }

    if ((int_status & CAN_INTR_RX) && !(int_status & CAN_INTR_OVF)) {
        hal_can_rx_frame(phandle->can_base, &phandle->msg);
        if (phandle->callback)
            phandle->callback(phandle, (void *)CAN_EVENT_RX_IND);
    }

    writel(int_status, phandle->can_base + CAN_INTR_REG);
    return IRQ_HANDLED;
}

void test_ui_init()
{
    lv_obj_t * btn = lv_btn_create(lv_scr_act());     /*Add a button the current screen*/
    lv_obj_set_pos(btn, 50, 50);                            /*Set its position*/
    lv_obj_set_size(btn, 120, 50);                          /*Set its size*/
    lv_obj_add_event_cb(btn, btn_event_cb, LV_EVENT_ALL, NULL);           /*Assign a callback to the button*/

    lv_obj_t * label = lv_label_create(btn);          /*Add a label to the button*/
    lv_label_set_text(label, "get ip address");                     /*Set the labels text*/
    lv_obj_center(label);

    rt_thread_mdelay(1);

    labelIpaddr = lv_label_create(lv_scr_act());
    lv_label_set_text_fmt(labelIpaddr, "local ip addr:0x%X", 0xaa55);
    lv_label_set_text_fmt(labelIpaddr, "local ip addr: %s", ip4addr_ntoa(&netif_list->ip_addr));
    lv_obj_set_pos(labelIpaddr, 200, 50);
    lv_obj_set_size(labelIpaddr, 400, 50);
}